X86InstrFragmentsSIMD.td revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
1//===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file provides pattern fragments useful for SIMD instructions. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// MMX Pattern Fragments 16//===----------------------------------------------------------------------===// 17 18def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>; 19def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>; 20 21//===----------------------------------------------------------------------===// 22// SSE specific DAG Nodes. 23//===----------------------------------------------------------------------===// 24 25def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>, 26 SDTCisFP<0>, SDTCisInt<2> ]>; 27def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, 28 SDTCisFP<1>, SDTCisVT<3, i8>, 29 SDTCisVec<1>]>; 30 31def X86umin : SDNode<"X86ISD::UMIN", SDTIntBinOp>; 32def X86umax : SDNode<"X86ISD::UMAX", SDTIntBinOp>; 33def X86smin : SDNode<"X86ISD::SMIN", SDTIntBinOp>; 34def X86smax : SDNode<"X86ISD::SMAX", SDTIntBinOp>; 35 36def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>; 37def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>; 38 39// Commutative and Associative FMIN and FMAX. 40def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp, 41 [SDNPCommutative, SDNPAssociative]>; 42def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp, 43 [SDNPCommutative, SDNPAssociative]>; 44 45def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp, 46 [SDNPCommutative, SDNPAssociative]>; 47def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp, 48 [SDNPCommutative, SDNPAssociative]>; 49def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp, 50 [SDNPCommutative, SDNPAssociative]>; 51def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp, 52 [SDNPCommutative, SDNPAssociative]>; 53def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>; 54def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>; 55def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>; 56def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>; 57def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>; 58def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>; 59def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>; 60def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>; 61def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>; 62def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>; 63def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>; 64//def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>; 65def X86pshufb : SDNode<"X86ISD::PSHUFB", 66 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 67 SDTCisSameAs<0,2>]>>; 68def X86andnp : SDNode<"X86ISD::ANDNP", 69 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 70 SDTCisSameAs<0,2>]>>; 71def X86psign : SDNode<"X86ISD::PSIGN", 72 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 73 SDTCisSameAs<0,2>]>>; 74def X86pextrb : SDNode<"X86ISD::PEXTRB", 75 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>; 76def X86pextrw : SDNode<"X86ISD::PEXTRW", 77 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>; 78def X86pinsrb : SDNode<"X86ISD::PINSRB", 79 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, 80 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; 81def X86pinsrw : SDNode<"X86ISD::PINSRW", 82 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>, 83 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; 84def X86insertps : SDNode<"X86ISD::INSERTPS", 85 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>, 86 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>; 87def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL", 88 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>; 89 90def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad, 91 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 92 93def X86vzext : SDNode<"X86ISD::VZEXT", 94 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 95 SDTCisInt<0>, SDTCisInt<1>, 96 SDTCisOpSmallerThanOp<1, 0>]>>; 97 98def X86vsext : SDNode<"X86ISD::VSEXT", 99 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 100 SDTCisInt<0>, SDTCisInt<1>, 101 SDTCisOpSmallerThanOp<1, 0>]>>; 102 103def X86vtrunc : SDNode<"X86ISD::VTRUNC", 104 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 105 SDTCisInt<0>, SDTCisInt<1>, 106 SDTCisOpSmallerThanOp<0, 1>]>>; 107def X86trunc : SDNode<"X86ISD::TRUNC", 108 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>, 109 SDTCisOpSmallerThanOp<0, 1>]>>; 110 111def X86vtruncm : SDNode<"X86ISD::VTRUNCM", 112 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 113 SDTCisInt<0>, SDTCisInt<1>, 114 SDTCisVec<2>, SDTCisInt<2>, 115 SDTCisOpSmallerThanOp<0, 2>]>>; 116def X86vfpext : SDNode<"X86ISD::VFPEXT", 117 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 118 SDTCisFP<0>, SDTCisFP<1>, 119 SDTCisOpSmallerThanOp<1, 0>]>>; 120def X86vfpround: SDNode<"X86ISD::VFPROUND", 121 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 122 SDTCisFP<0>, SDTCisFP<1>, 123 SDTCisOpSmallerThanOp<0, 1>]>>; 124 125def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>; 126def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>; 127def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>; 128def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>; 129def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>; 130 131def X86IntCmpMask : SDTypeProfile<1, 2, 132 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>; 133def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>; 134def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>; 135 136def X86CmpMaskCC : 137 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<0>, SDTCisVec<1>, 138 SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 139def X86CmpMaskCCScalar : 140 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 141 142def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>; 143def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>; 144def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>; 145 146def X86vshl : SDNode<"X86ISD::VSHL", 147 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 148 SDTCisVec<2>]>>; 149def X86vsrl : SDNode<"X86ISD::VSRL", 150 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 151 SDTCisVec<2>]>>; 152def X86vsra : SDNode<"X86ISD::VSRA", 153 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 154 SDTCisVec<2>]>>; 155 156def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>; 157def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>; 158def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>; 159 160def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 161 SDTCisVec<1>, 162 SDTCisSameAs<2, 1>]>; 163def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>; 164def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>; 165def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>; 166def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>; 167def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>, 168 SDTCisVec<1>, 169 SDTCisSameAs<2, 1>]>>; 170def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>, 171 SDTCisVec<1>, 172 SDTCisSameAs<2, 1>]>>; 173def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>; 174 175def X86pmuludq : SDNode<"X86ISD::PMULUDQ", 176 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 177 SDTCisSameAs<1,2>]>>; 178def X86pmuldq : SDNode<"X86ISD::PMULDQ", 179 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 180 SDTCisSameAs<1,2>]>>; 181 182// Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get 183// translated into one of the target nodes below during lowering. 184// Note: this is a work in progress... 185def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>; 186def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 187 SDTCisSameAs<0,2>]>; 188def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 189 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>; 190 191def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>, 192 SDTCisSameAs<0,1>, SDTCisInt<2>]>; 193def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 194 SDTCisSameAs<0,2>, SDTCisInt<3>]>; 195 196def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>; 197def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>; 198 199def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 200 SDTCisSameAs<1,2>, SDTCisVT<3, i32>]>; 201 202def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>, 203 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>; 204 205def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>; 206 207def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>; 208def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>; 209def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>; 210 211def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>; 212 213def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>; 214def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>; 215def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>; 216 217def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>; 218def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>; 219 220def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>; 221def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>; 222def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>; 223 224def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>; 225def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>; 226 227def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>; 228def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>; 229 230def X86VPermilp : SDNode<"X86ISD::VPERMILP", SDTShuff2OpI>; 231def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>; 232def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>; 233def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>; 234def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>; 235 236def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>; 237 238def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>; 239def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>; 240def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3, 241 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 242def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2, 243 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>; 244 245def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>; 246def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>; 247def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>; 248def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>; 249def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>; 250def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>; 251def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>; 252 253def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 254 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>, 255 SDTCisVT<4, i8>]>; 256def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 257 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>, 258 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>, 259 SDTCisVT<6, i8>]>; 260 261def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>; 262def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>; 263 264//===----------------------------------------------------------------------===// 265// SSE Complex Patterns 266//===----------------------------------------------------------------------===// 267 268// These are 'extloads' from a scalar to the low element of a vector, zeroing 269// the top elements. These are used for the SSE 'ss' and 'sd' instruction 270// forms. 271def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [], 272 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, 273 SDNPWantRoot]>; 274def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [], 275 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, 276 SDNPWantRoot]>; 277 278def ssmem : Operand<v4f32> { 279 let PrintMethod = "printf32mem"; 280 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); 281 let ParserMatchClass = X86Mem32AsmOperand; 282 let OperandType = "OPERAND_MEMORY"; 283} 284def sdmem : Operand<v2f64> { 285 let PrintMethod = "printf64mem"; 286 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); 287 let ParserMatchClass = X86Mem64AsmOperand; 288 let OperandType = "OPERAND_MEMORY"; 289} 290 291//===----------------------------------------------------------------------===// 292// SSE pattern fragments 293//===----------------------------------------------------------------------===// 294 295// 128-bit load pattern fragments 296// NOTE: all 128-bit integer vector loads are promoted to v2i64 297def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>; 298def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>; 299def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>; 300 301// 256-bit load pattern fragments 302// NOTE: all 256-bit integer vector loads are promoted to v4i64 303def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>; 304def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>; 305def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>; 306 307// 512-bit load pattern fragments 308def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>; 309def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>; 310def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>; 311def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>; 312 313// 128-/256-/512-bit extload pattern fragments 314def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>; 315def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>; 316def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>; 317 318// Like 'store', but always requires 128-bit vector alignment. 319def alignedstore : PatFrag<(ops node:$val, node:$ptr), 320 (store node:$val, node:$ptr), [{ 321 return cast<StoreSDNode>(N)->getAlignment() >= 16; 322}]>; 323 324// Like 'store', but always requires 256-bit vector alignment. 325def alignedstore256 : PatFrag<(ops node:$val, node:$ptr), 326 (store node:$val, node:$ptr), [{ 327 return cast<StoreSDNode>(N)->getAlignment() >= 32; 328}]>; 329 330// Like 'store', but always requires 512-bit vector alignment. 331def alignedstore512 : PatFrag<(ops node:$val, node:$ptr), 332 (store node:$val, node:$ptr), [{ 333 return cast<StoreSDNode>(N)->getAlignment() >= 64; 334}]>; 335 336// Like 'load', but always requires 128-bit vector alignment. 337def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 338 return cast<LoadSDNode>(N)->getAlignment() >= 16; 339}]>; 340 341// Like 'X86vzload', but always requires 128-bit vector alignment. 342def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{ 343 return cast<MemSDNode>(N)->getAlignment() >= 16; 344}]>; 345 346// Like 'load', but always requires 256-bit vector alignment. 347def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 348 return cast<LoadSDNode>(N)->getAlignment() >= 32; 349}]>; 350 351// Like 'load', but always requires 512-bit vector alignment. 352def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 353 return cast<LoadSDNode>(N)->getAlignment() >= 64; 354}]>; 355 356def alignedloadfsf32 : PatFrag<(ops node:$ptr), 357 (f32 (alignedload node:$ptr))>; 358def alignedloadfsf64 : PatFrag<(ops node:$ptr), 359 (f64 (alignedload node:$ptr))>; 360 361// 128-bit aligned load pattern fragments 362// NOTE: all 128-bit integer vector loads are promoted to v2i64 363def alignedloadv4f32 : PatFrag<(ops node:$ptr), 364 (v4f32 (alignedload node:$ptr))>; 365def alignedloadv2f64 : PatFrag<(ops node:$ptr), 366 (v2f64 (alignedload node:$ptr))>; 367def alignedloadv2i64 : PatFrag<(ops node:$ptr), 368 (v2i64 (alignedload node:$ptr))>; 369 370// 256-bit aligned load pattern fragments 371// NOTE: all 256-bit integer vector loads are promoted to v4i64 372def alignedloadv8f32 : PatFrag<(ops node:$ptr), 373 (v8f32 (alignedload256 node:$ptr))>; 374def alignedloadv4f64 : PatFrag<(ops node:$ptr), 375 (v4f64 (alignedload256 node:$ptr))>; 376def alignedloadv4i64 : PatFrag<(ops node:$ptr), 377 (v4i64 (alignedload256 node:$ptr))>; 378 379// 512-bit aligned load pattern fragments 380def alignedloadv16f32 : PatFrag<(ops node:$ptr), 381 (v16f32 (alignedload512 node:$ptr))>; 382def alignedloadv16i32 : PatFrag<(ops node:$ptr), 383 (v16i32 (alignedload512 node:$ptr))>; 384def alignedloadv8f64 : PatFrag<(ops node:$ptr), 385 (v8f64 (alignedload512 node:$ptr))>; 386def alignedloadv8i64 : PatFrag<(ops node:$ptr), 387 (v8i64 (alignedload512 node:$ptr))>; 388 389// Like 'load', but uses special alignment checks suitable for use in 390// memory operands in most SSE instructions, which are required to 391// be naturally aligned on some targets but not on others. If the subtarget 392// allows unaligned accesses, match any load, though this may require 393// setting a feature bit in the processor (on startup, for example). 394// Opteron 10h and later implement such a feature. 395def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 396 return Subtarget->hasVectorUAMem() 397 || cast<LoadSDNode>(N)->getAlignment() >= 16; 398}]>; 399 400def memop4 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 401 return Subtarget->hasVectorUAMem() 402 || cast<LoadSDNode>(N)->getAlignment() >= 4; 403}]>; 404 405def memop8 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 406 return Subtarget->hasVectorUAMem() 407 || cast<LoadSDNode>(N)->getAlignment() >= 8; 408}]>; 409 410def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>; 411def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>; 412 413// 128-bit memop pattern fragments 414// NOTE: all 128-bit integer vector loads are promoted to v2i64 415def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>; 416def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>; 417def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>; 418 419// 256-bit memop pattern fragments 420// NOTE: all 256-bit integer vector loads are promoted to v4i64 421def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>; 422def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>; 423def memopv4i64 : PatFrag<(ops node:$ptr), (v4i64 (memop node:$ptr))>; 424 425// 512-bit memop pattern fragments 426def memopv16f32 : PatFrag<(ops node:$ptr), (v16f32 (memop4 node:$ptr))>; 427def memopv8f64 : PatFrag<(ops node:$ptr), (v8f64 (memop8 node:$ptr))>; 428def memopv16i32 : PatFrag<(ops node:$ptr), (v16i32 (memop4 node:$ptr))>; 429def memopv8i64 : PatFrag<(ops node:$ptr), (v8i64 (memop8 node:$ptr))>; 430 431// SSSE3 uses MMX registers for some instructions. They aren't aligned on a 432// 16-byte boundary. 433// FIXME: 8 byte alignment for mmx reads is not required 434def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 435 return cast<LoadSDNode>(N)->getAlignment() >= 8; 436}]>; 437 438def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>; 439 440// MOVNT Support 441// Like 'store', but requires the non-temporal bit to be set 442def nontemporalstore : PatFrag<(ops node:$val, node:$ptr), 443 (st node:$val, node:$ptr), [{ 444 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) 445 return ST->isNonTemporal(); 446 return false; 447}]>; 448 449def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 450 (st node:$val, node:$ptr), [{ 451 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) 452 return ST->isNonTemporal() && !ST->isTruncatingStore() && 453 ST->getAddressingMode() == ISD::UNINDEXED && 454 ST->getAlignment() >= 16; 455 return false; 456}]>; 457 458def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 459 (st node:$val, node:$ptr), [{ 460 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) 461 return ST->isNonTemporal() && 462 ST->getAlignment() < 16; 463 return false; 464}]>; 465 466// 128-bit bitconvert pattern fragments 467def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>; 468def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>; 469def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>; 470def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>; 471def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>; 472def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>; 473 474// 256-bit bitconvert pattern fragments 475def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>; 476def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>; 477def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>; 478def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>; 479def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>; 480 481// 512-bit bitconvert pattern fragments 482def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>; 483def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>; 484def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>; 485def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>; 486 487def vzmovl_v2i64 : PatFrag<(ops node:$src), 488 (bitconvert (v2i64 (X86vzmovl 489 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>; 490def vzmovl_v4i32 : PatFrag<(ops node:$src), 491 (bitconvert (v4i32 (X86vzmovl 492 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>; 493 494def vzload_v2i64 : PatFrag<(ops node:$src), 495 (bitconvert (v2i64 (X86vzload node:$src)))>; 496 497 498def fp32imm0 : PatLeaf<(f32 fpimm), [{ 499 return N->isExactlyValue(+0.0); 500}]>; 501 502def I8Imm : SDNodeXForm<imm, [{ 503 // Transformation function: get the low 8 bits. 504 return getI8Imm((uint8_t)N->getZExtValue()); 505}]>; 506 507def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>; 508def FROUND_CURRENT : ImmLeaf<i32, [{ return Imm == 4; }]>; 509 510// BYTE_imm - Transform bit immediates into byte immediates. 511def BYTE_imm : SDNodeXForm<imm, [{ 512 // Transformation function: imm >> 3 513 return getI32Imm(N->getZExtValue() >> 3); 514}]>; 515 516// EXTRACT_get_vextract128_imm xform function: convert extract_subvector index 517// to VEXTRACTF128/VEXTRACTI128 imm. 518def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{ 519 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N)); 520}]>; 521 522// INSERT_get_vinsert128_imm xform function: convert insert_subvector index to 523// VINSERTF128/VINSERTI128 imm. 524def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{ 525 return getI8Imm(X86::getInsertVINSERT128Immediate(N)); 526}]>; 527 528// EXTRACT_get_vextract256_imm xform function: convert extract_subvector index 529// to VEXTRACTF64x4 imm. 530def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{ 531 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N)); 532}]>; 533 534// INSERT_get_vinsert256_imm xform function: convert insert_subvector index to 535// VINSERTF64x4 imm. 536def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{ 537 return getI8Imm(X86::getInsertVINSERT256Immediate(N)); 538}]>; 539 540def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index), 541 (extract_subvector node:$bigvec, 542 node:$index), [{ 543 return X86::isVEXTRACT128Index(N); 544}], EXTRACT_get_vextract128_imm>; 545 546def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec, 547 node:$index), 548 (insert_subvector node:$bigvec, node:$smallvec, 549 node:$index), [{ 550 return X86::isVINSERT128Index(N); 551}], INSERT_get_vinsert128_imm>; 552 553 554def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index), 555 (extract_subvector node:$bigvec, 556 node:$index), [{ 557 return X86::isVEXTRACT256Index(N); 558}], EXTRACT_get_vextract256_imm>; 559 560def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec, 561 node:$index), 562 (insert_subvector node:$bigvec, node:$smallvec, 563 node:$index), [{ 564 return X86::isVINSERT256Index(N); 565}], INSERT_get_vinsert256_imm>; 566 567