X86InstrInfo.cpp revision 7107aded170612748f46380f21ec6b71dfaf4910 
1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86InstrInfo.h"
15#include "X86.h"
16#include "X86InstrBuilder.h"
17#include "X86MachineFunctionInfo.h"
18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/CodeGen/LiveVariables.h"
22#include "llvm/CodeGen/MachineConstantPool.h"
23#include "llvm/CodeGen/MachineDominators.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineRegisterInfo.h"
27#include "llvm/CodeGen/StackMaps.h"
28#include "llvm/IR/DerivedTypes.h"
29#include "llvm/IR/LLVMContext.h"
30#include "llvm/MC/MCAsmInfo.h"
31#include "llvm/MC/MCInst.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/Debug.h"
34#include "llvm/Support/ErrorHandling.h"
35#include "llvm/Support/raw_ostream.h"
36#include "llvm/Target/TargetOptions.h"
37#include <limits>
38
39#define GET_INSTRINFO_CTOR
40#include "X86GenInstrInfo.inc"
41
42using namespace llvm;
43
44static cl::opt<bool>
45NoFusing("disable-spill-fusing",
46         cl::desc("Disable fusing of spill code into instructions"));
47static cl::opt<bool>
48PrintFailedFusing("print-failed-fuse-candidates",
49                  cl::desc("Print instructions that the allocator wants to"
50                           " fuse, but the X86 backend currently can't"),
51                  cl::Hidden);
52static cl::opt<bool>
53ReMatPICStubLoad("remat-pic-stub-load",
54                 cl::desc("Re-materialize load from stub in PIC mode"),
55                 cl::init(false), cl::Hidden);
56
57enum {
58  // Select which memory operand is being unfolded.
59  // (stored in bits 0 - 3)
60  TB_INDEX_0    = 0,
61  TB_INDEX_1    = 1,
62  TB_INDEX_2    = 2,
63  TB_INDEX_3    = 3,
64  TB_INDEX_MASK = 0xf,
65
66  // Do not insert the reverse map (MemOp -> RegOp) into the table.
67  // This may be needed because there is a many -> one mapping.
68  TB_NO_REVERSE   = 1 << 4,
69
70  // Do not insert the forward map (RegOp -> MemOp) into the table.
71  // This is needed for Native Client, which prohibits branch
72  // instructions from using a memory operand.
73  TB_NO_FORWARD   = 1 << 5,
74
75  TB_FOLDED_LOAD  = 1 << 6,
76  TB_FOLDED_STORE = 1 << 7,
77
78  // Minimum alignment required for load/store.
79  // Used for RegOp->MemOp conversion.
80  // (stored in bits 8 - 15)
81  TB_ALIGN_SHIFT = 8,
82  TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
83  TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
84  TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
85  TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
86  TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
87};
88
89struct X86OpTblEntry {
90  uint16_t RegOp;
91  uint16_t MemOp;
92  uint16_t Flags;
93};
94
95X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
96  : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
97                     ? X86::ADJCALLSTACKDOWN64
98                     : X86::ADJCALLSTACKDOWN32),
99                    (tm.getSubtarget<X86Subtarget>().is64Bit()
100                     ? X86::ADJCALLSTACKUP64
101                     : X86::ADJCALLSTACKUP32)),
102    TM(tm), RI(tm) {
103
104  static const X86OpTblEntry OpTbl2Addr[] = {
105    { X86::ADC32ri,     X86::ADC32mi,    0 },
106    { X86::ADC32ri8,    X86::ADC32mi8,   0 },
107    { X86::ADC32rr,     X86::ADC32mr,    0 },
108    { X86::ADC64ri32,   X86::ADC64mi32,  0 },
109    { X86::ADC64ri8,    X86::ADC64mi8,   0 },
110    { X86::ADC64rr,     X86::ADC64mr,    0 },
111    { X86::ADD16ri,     X86::ADD16mi,    0 },
112    { X86::ADD16ri8,    X86::ADD16mi8,   0 },
113    { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
114    { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
115    { X86::ADD16rr,     X86::ADD16mr,    0 },
116    { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
117    { X86::ADD32ri,     X86::ADD32mi,    0 },
118    { X86::ADD32ri8,    X86::ADD32mi8,   0 },
119    { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
120    { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
121    { X86::ADD32rr,     X86::ADD32mr,    0 },
122    { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
123    { X86::ADD64ri32,   X86::ADD64mi32,  0 },
124    { X86::ADD64ri8,    X86::ADD64mi8,   0 },
125    { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
126    { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
127    { X86::ADD64rr,     X86::ADD64mr,    0 },
128    { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
129    { X86::ADD8ri,      X86::ADD8mi,     0 },
130    { X86::ADD8rr,      X86::ADD8mr,     0 },
131    { X86::AND16ri,     X86::AND16mi,    0 },
132    { X86::AND16ri8,    X86::AND16mi8,   0 },
133    { X86::AND16rr,     X86::AND16mr,    0 },
134    { X86::AND32ri,     X86::AND32mi,    0 },
135    { X86::AND32ri8,    X86::AND32mi8,   0 },
136    { X86::AND32rr,     X86::AND32mr,    0 },
137    { X86::AND64ri32,   X86::AND64mi32,  0 },
138    { X86::AND64ri8,    X86::AND64mi8,   0 },
139    { X86::AND64rr,     X86::AND64mr,    0 },
140    { X86::AND8ri,      X86::AND8mi,     0 },
141    { X86::AND8rr,      X86::AND8mr,     0 },
142    { X86::DEC16r,      X86::DEC16m,     0 },
143    { X86::DEC32r,      X86::DEC32m,     0 },
144    { X86::DEC64_16r,   X86::DEC64_16m,  0 },
145    { X86::DEC64_32r,   X86::DEC64_32m,  0 },
146    { X86::DEC64r,      X86::DEC64m,     0 },
147    { X86::DEC8r,       X86::DEC8m,      0 },
148    { X86::INC16r,      X86::INC16m,     0 },
149    { X86::INC32r,      X86::INC32m,     0 },
150    { X86::INC64_16r,   X86::INC64_16m,  0 },
151    { X86::INC64_32r,   X86::INC64_32m,  0 },
152    { X86::INC64r,      X86::INC64m,     0 },
153    { X86::INC8r,       X86::INC8m,      0 },
154    { X86::NEG16r,      X86::NEG16m,     0 },
155    { X86::NEG32r,      X86::NEG32m,     0 },
156    { X86::NEG64r,      X86::NEG64m,     0 },
157    { X86::NEG8r,       X86::NEG8m,      0 },
158    { X86::NOT16r,      X86::NOT16m,     0 },
159    { X86::NOT32r,      X86::NOT32m,     0 },
160    { X86::NOT64r,      X86::NOT64m,     0 },
161    { X86::NOT8r,       X86::NOT8m,      0 },
162    { X86::OR16ri,      X86::OR16mi,     0 },
163    { X86::OR16ri8,     X86::OR16mi8,    0 },
164    { X86::OR16rr,      X86::OR16mr,     0 },
165    { X86::OR32ri,      X86::OR32mi,     0 },
166    { X86::OR32ri8,     X86::OR32mi8,    0 },
167    { X86::OR32rr,      X86::OR32mr,     0 },
168    { X86::OR64ri32,    X86::OR64mi32,   0 },
169    { X86::OR64ri8,     X86::OR64mi8,    0 },
170    { X86::OR64rr,      X86::OR64mr,     0 },
171    { X86::OR8ri,       X86::OR8mi,      0 },
172    { X86::OR8rr,       X86::OR8mr,      0 },
173    { X86::ROL16r1,     X86::ROL16m1,    0 },
174    { X86::ROL16rCL,    X86::ROL16mCL,   0 },
175    { X86::ROL16ri,     X86::ROL16mi,    0 },
176    { X86::ROL32r1,     X86::ROL32m1,    0 },
177    { X86::ROL32rCL,    X86::ROL32mCL,   0 },
178    { X86::ROL32ri,     X86::ROL32mi,    0 },
179    { X86::ROL64r1,     X86::ROL64m1,    0 },
180    { X86::ROL64rCL,    X86::ROL64mCL,   0 },
181    { X86::ROL64ri,     X86::ROL64mi,    0 },
182    { X86::ROL8r1,      X86::ROL8m1,     0 },
183    { X86::ROL8rCL,     X86::ROL8mCL,    0 },
184    { X86::ROL8ri,      X86::ROL8mi,     0 },
185    { X86::ROR16r1,     X86::ROR16m1,    0 },
186    { X86::ROR16rCL,    X86::ROR16mCL,   0 },
187    { X86::ROR16ri,     X86::ROR16mi,    0 },
188    { X86::ROR32r1,     X86::ROR32m1,    0 },
189    { X86::ROR32rCL,    X86::ROR32mCL,   0 },
190    { X86::ROR32ri,     X86::ROR32mi,    0 },
191    { X86::ROR64r1,     X86::ROR64m1,    0 },
192    { X86::ROR64rCL,    X86::ROR64mCL,   0 },
193    { X86::ROR64ri,     X86::ROR64mi,    0 },
194    { X86::ROR8r1,      X86::ROR8m1,     0 },
195    { X86::ROR8rCL,     X86::ROR8mCL,    0 },
196    { X86::ROR8ri,      X86::ROR8mi,     0 },
197    { X86::SAR16r1,     X86::SAR16m1,    0 },
198    { X86::SAR16rCL,    X86::SAR16mCL,   0 },
199    { X86::SAR16ri,     X86::SAR16mi,    0 },
200    { X86::SAR32r1,     X86::SAR32m1,    0 },
201    { X86::SAR32rCL,    X86::SAR32mCL,   0 },
202    { X86::SAR32ri,     X86::SAR32mi,    0 },
203    { X86::SAR64r1,     X86::SAR64m1,    0 },
204    { X86::SAR64rCL,    X86::SAR64mCL,   0 },
205    { X86::SAR64ri,     X86::SAR64mi,    0 },
206    { X86::SAR8r1,      X86::SAR8m1,     0 },
207    { X86::SAR8rCL,     X86::SAR8mCL,    0 },
208    { X86::SAR8ri,      X86::SAR8mi,     0 },
209    { X86::SBB32ri,     X86::SBB32mi,    0 },
210    { X86::SBB32ri8,    X86::SBB32mi8,   0 },
211    { X86::SBB32rr,     X86::SBB32mr,    0 },
212    { X86::SBB64ri32,   X86::SBB64mi32,  0 },
213    { X86::SBB64ri8,    X86::SBB64mi8,   0 },
214    { X86::SBB64rr,     X86::SBB64mr,    0 },
215    { X86::SHL16rCL,    X86::SHL16mCL,   0 },
216    { X86::SHL16ri,     X86::SHL16mi,    0 },
217    { X86::SHL32rCL,    X86::SHL32mCL,   0 },
218    { X86::SHL32ri,     X86::SHL32mi,    0 },
219    { X86::SHL64rCL,    X86::SHL64mCL,   0 },
220    { X86::SHL64ri,     X86::SHL64mi,    0 },
221    { X86::SHL8rCL,     X86::SHL8mCL,    0 },
222    { X86::SHL8ri,      X86::SHL8mi,     0 },
223    { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
224    { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
225    { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
226    { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
227    { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
228    { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
229    { X86::SHR16r1,     X86::SHR16m1,    0 },
230    { X86::SHR16rCL,    X86::SHR16mCL,   0 },
231    { X86::SHR16ri,     X86::SHR16mi,    0 },
232    { X86::SHR32r1,     X86::SHR32m1,    0 },
233    { X86::SHR32rCL,    X86::SHR32mCL,   0 },
234    { X86::SHR32ri,     X86::SHR32mi,    0 },
235    { X86::SHR64r1,     X86::SHR64m1,    0 },
236    { X86::SHR64rCL,    X86::SHR64mCL,   0 },
237    { X86::SHR64ri,     X86::SHR64mi,    0 },
238    { X86::SHR8r1,      X86::SHR8m1,     0 },
239    { X86::SHR8rCL,     X86::SHR8mCL,    0 },
240    { X86::SHR8ri,      X86::SHR8mi,     0 },
241    { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
242    { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
243    { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
244    { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
245    { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
246    { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
247    { X86::SUB16ri,     X86::SUB16mi,    0 },
248    { X86::SUB16ri8,    X86::SUB16mi8,   0 },
249    { X86::SUB16rr,     X86::SUB16mr,    0 },
250    { X86::SUB32ri,     X86::SUB32mi,    0 },
251    { X86::SUB32ri8,    X86::SUB32mi8,   0 },
252    { X86::SUB32rr,     X86::SUB32mr,    0 },
253    { X86::SUB64ri32,   X86::SUB64mi32,  0 },
254    { X86::SUB64ri8,    X86::SUB64mi8,   0 },
255    { X86::SUB64rr,     X86::SUB64mr,    0 },
256    { X86::SUB8ri,      X86::SUB8mi,     0 },
257    { X86::SUB8rr,      X86::SUB8mr,     0 },
258    { X86::XOR16ri,     X86::XOR16mi,    0 },
259    { X86::XOR16ri8,    X86::XOR16mi8,   0 },
260    { X86::XOR16rr,     X86::XOR16mr,    0 },
261    { X86::XOR32ri,     X86::XOR32mi,    0 },
262    { X86::XOR32ri8,    X86::XOR32mi8,   0 },
263    { X86::XOR32rr,     X86::XOR32mr,    0 },
264    { X86::XOR64ri32,   X86::XOR64mi32,  0 },
265    { X86::XOR64ri8,    X86::XOR64mi8,   0 },
266    { X86::XOR64rr,     X86::XOR64mr,    0 },
267    { X86::XOR8ri,      X86::XOR8mi,     0 },
268    { X86::XOR8rr,      X86::XOR8mr,     0 }
269  };
270
271  for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
272    unsigned RegOp = OpTbl2Addr[i].RegOp;
273    unsigned MemOp = OpTbl2Addr[i].MemOp;
274    unsigned Flags = OpTbl2Addr[i].Flags;
275    AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
276                  RegOp, MemOp,
277                  // Index 0, folded load and store, no alignment requirement.
278                  Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
279  }
280
281  static const X86OpTblEntry OpTbl0[] = {
282    { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
283    { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
284    { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
285    { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
286    { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
287    { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
288    { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
289    { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
290    { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
291    { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
292    { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
293    { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
294    { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
295    { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
296    { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
297    { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
298    { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
299    { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
300    { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
301    { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
302    { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
303    { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
304    { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
305    { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
306    { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
307    { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
308    { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
309    { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
310    { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
311    { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
312    { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
313    { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
314    { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
315    { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
316    { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
317    { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
318    { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
319    { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
320    { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
321    { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
322    { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
323    { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
324    { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
325    { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
326    { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
327    { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
328    { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
329    { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
330    { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
331    { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
332    { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
333    { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
334    { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
335    { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
336    { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
337    { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
338    { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
339    { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
340    { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
341    { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
342    { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
343    { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
344    { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
345    { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
346    { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
347    { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
348    { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
349    { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
350    { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
351    { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
352    { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
353    { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
354    { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
355    { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
356    { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
357    // AVX 128-bit versions of foldable instructions
358    { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
359    { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
360    { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
361    { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
362    { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
363    { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
364    { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
365    { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
366    { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
367    { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
368    { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
369    // AVX 256-bit foldable instructions
370    { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
371    { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
372    { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
373    { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
374    { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
375    { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
376    // AVX-512 foldable instructions
377    { X86::VMOVPDI2DIZrr,X86::VMOVPDI2DIZmr,  TB_FOLDED_STORE }
378  };
379
380  for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
381    unsigned RegOp      = OpTbl0[i].RegOp;
382    unsigned MemOp      = OpTbl0[i].MemOp;
383    unsigned Flags      = OpTbl0[i].Flags;
384    AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
385                  RegOp, MemOp, TB_INDEX_0 | Flags);
386  }
387
388  static const X86OpTblEntry OpTbl1[] = {
389    { X86::CMP16rr,         X86::CMP16rm,             0 },
390    { X86::CMP32rr,         X86::CMP32rm,             0 },
391    { X86::CMP64rr,         X86::CMP64rm,             0 },
392    { X86::CMP8rr,          X86::CMP8rm,              0 },
393    { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
394    { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
395    { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
396    { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
397    { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
398    { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
399    { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
400    { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
401    { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
402    { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
403    { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
404    { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
405    { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
406    { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
407    { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
408    { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
409    { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
410    { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
411    { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
412    { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
413    { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
414    { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
415    { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
416    { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
417    { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
418    { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
419    { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
420    { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
421    { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
422    { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
423    { X86::MOV16rr,         X86::MOV16rm,             0 },
424    { X86::MOV32rr,         X86::MOV32rm,             0 },
425    { X86::MOV64rr,         X86::MOV64rm,             0 },
426    { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
427    { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
428    { X86::MOV8rr,          X86::MOV8rm,              0 },
429    { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
430    { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
431    { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
432    { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
433    { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
434    { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
435    { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
436    { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
437    { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
438    { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
439    { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
440    { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
441    { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
442    { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
443    { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
444    { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
445    { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm,        0 },
446    { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
447    { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
448    { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
449    { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
450    { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
451    { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
452    { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
453    { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
454    { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
455    { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
456    { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
457    { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
458    { X86::RCPPSr_Int,      X86::RCPPSm_Int,          TB_ALIGN_16 },
459    { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
460    { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int,        TB_ALIGN_16 },
461    { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
462    { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
463    { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
464    { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
465    { X86::SQRTSDr,         X86::SQRTSDm,             0 },
466    { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
467    { X86::SQRTSSr,         X86::SQRTSSm,             0 },
468    { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
469    { X86::TEST16rr,        X86::TEST16rm,            0 },
470    { X86::TEST32rr,        X86::TEST32rm,            0 },
471    { X86::TEST64rr,        X86::TEST64rm,            0 },
472    { X86::TEST8rr,         X86::TEST8rm,             0 },
473    // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
474    { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
475    { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
476    // AVX 128-bit versions of foldable instructions
477    { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
478    { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
479    { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
480    { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
481    { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
482    { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
483    { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
484    { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
485    { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
486    { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
487    { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
488    { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
489    { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
490    { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
491    { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
492    { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
493    { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
494    { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
495    { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
496    { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
497    { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
498    { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
499    { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
500    { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
501    { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         TB_ALIGN_16 },
502    { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         TB_ALIGN_16 },
503    { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
504    { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
505    { X86::VMOVZQI2PQIrr,   X86::VMOVZQI2PQIrm,       0 },
506    { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
507    { X86::VPABSBrr128,     X86::VPABSBrm128,         0 },
508    { X86::VPABSDrr128,     X86::VPABSDrm128,         0 },
509    { X86::VPABSWrr128,     X86::VPABSWrm128,         0 },
510    { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
511    { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
512    { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
513    { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
514    { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
515    { X86::VRCPPSr,         X86::VRCPPSm,             0 },
516    { X86::VRCPPSr_Int,     X86::VRCPPSm_Int,         0 },
517    { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
518    { X86::VRSQRTPSr_Int,   X86::VRSQRTPSm_Int,       0 },
519    { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
520    { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
521    { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
522    { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
523    { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
524
525    // AVX 256-bit foldable instructions
526    { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
527    { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
528    { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
529    { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
530    { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
531    { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
532    { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
533
534    // AVX2 foldable instructions
535    { X86::VPABSBrr256,     X86::VPABSBrm256,         0 },
536    { X86::VPABSDrr256,     X86::VPABSDrm256,         0 },
537    { X86::VPABSWrr256,     X86::VPABSWrm256,         0 },
538    { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
539    { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
540    { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
541    { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
542    { X86::VRCPPSYr_Int,    X86::VRCPPSYm_Int,        0 },
543    { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
544    { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
545    { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
546    { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
547    { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
548
549    // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
550    { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
551    { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
552    { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
553    { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
554    { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
555    { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
556    { X86::BLCI32rr,        X86::BLCI32rm,            0 },
557    { X86::BLCI64rr,        X86::BLCI64rm,            0 },
558    { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
559    { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
560    { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
561    { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
562    { X86::BLCS32rr,        X86::BLCS32rm,            0 },
563    { X86::BLCS64rr,        X86::BLCS64rm,            0 },
564    { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
565    { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
566    { X86::BLSI32rr,        X86::BLSI32rm,            0 },
567    { X86::BLSI64rr,        X86::BLSI64rm,            0 },
568    { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
569    { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
570    { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
571    { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
572    { X86::BLSR32rr,        X86::BLSR32rm,            0 },
573    { X86::BLSR64rr,        X86::BLSR64rm,            0 },
574    { X86::BZHI32rr,        X86::BZHI32rm,            0 },
575    { X86::BZHI64rr,        X86::BZHI64rm,            0 },
576    { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
577    { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
578    { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
579    { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
580    { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
581    { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
582    { X86::RORX32ri,        X86::RORX32mi,            0 },
583    { X86::RORX64ri,        X86::RORX64mi,            0 },
584    { X86::SARX32rr,        X86::SARX32rm,            0 },
585    { X86::SARX64rr,        X86::SARX64rm,            0 },
586    { X86::SHRX32rr,        X86::SHRX32rm,            0 },
587    { X86::SHRX64rr,        X86::SHRX64rm,            0 },
588    { X86::SHLX32rr,        X86::SHLX32rm,            0 },
589    { X86::SHLX64rr,        X86::SHLX64rm,            0 },
590    { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
591    { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
592    { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
593    { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
594    { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
595    { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
596    { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
597
598    // AVX-512 foldable instructions
599    { X86::VMOV64toPQIZrr,  X86::VMOVQI2PQIZrm,       0 },
600    { X86::VMOVDI2SSZrr,    X86::VMOVDI2SSZrm,        0 },
601    { X86::VMOVDQA32rr,     X86::VMOVDQA32rm,         TB_ALIGN_64 },
602    { X86::VMOVDQA64rr,     X86::VMOVDQA64rm,         TB_ALIGN_64 },
603    { X86::VMOVDQU32rr,     X86::VMOVDQU32rm,         0 },
604    { X86::VMOVDQU64rr,     X86::VMOVDQU64rm,         0 },
605
606    // AES foldable instructions
607    { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
608    { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
609    { X86::VAESIMCrr,             X86::VAESIMCrm,             TB_ALIGN_16 },
610    { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, TB_ALIGN_16 },
611  };
612
613  for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
614    unsigned RegOp = OpTbl1[i].RegOp;
615    unsigned MemOp = OpTbl1[i].MemOp;
616    unsigned Flags = OpTbl1[i].Flags;
617    AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
618                  RegOp, MemOp,
619                  // Index 1, folded load
620                  Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
621  }
622
623  static const X86OpTblEntry OpTbl2[] = {
624    { X86::ADC32rr,         X86::ADC32rm,       0 },
625    { X86::ADC64rr,         X86::ADC64rm,       0 },
626    { X86::ADD16rr,         X86::ADD16rm,       0 },
627    { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
628    { X86::ADD32rr,         X86::ADD32rm,       0 },
629    { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
630    { X86::ADD64rr,         X86::ADD64rm,       0 },
631    { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
632    { X86::ADD8rr,          X86::ADD8rm,        0 },
633    { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
634    { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
635    { X86::ADDSDrr,         X86::ADDSDrm,       0 },
636    { X86::ADDSSrr,         X86::ADDSSrm,       0 },
637    { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
638    { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
639    { X86::AND16rr,         X86::AND16rm,       0 },
640    { X86::AND32rr,         X86::AND32rm,       0 },
641    { X86::AND64rr,         X86::AND64rm,       0 },
642    { X86::AND8rr,          X86::AND8rm,        0 },
643    { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
644    { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
645    { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
646    { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
647    { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
648    { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
649    { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
650    { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
651    { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
652    { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
653    { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
654    { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
655    { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
656    { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
657    { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
658    { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
659    { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
660    { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
661    { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
662    { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
663    { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
664    { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
665    { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
666    { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
667    { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
668    { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
669    { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
670    { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
671    { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
672    { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
673    { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
674    { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
675    { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
676    { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
677    { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
678    { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
679    { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
680    { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
681    { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
682    { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
683    { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
684    { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
685    { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
686    { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
687    { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
688    { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
689    { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
690    { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
691    { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
692    { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
693    { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
694    { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
695    { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
696    { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
697    { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
698    { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
699    { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
700    { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
701    { X86::CMPSDrr,         X86::CMPSDrm,       0 },
702    { X86::CMPSSrr,         X86::CMPSSrm,       0 },
703    { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
704    { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
705    { X86::DIVSDrr,         X86::DIVSDrm,       0 },
706    { X86::DIVSSrr,         X86::DIVSSrm,       0 },
707    { X86::FsANDNPDrr,      X86::FsANDNPDrm,    TB_ALIGN_16 },
708    { X86::FsANDNPSrr,      X86::FsANDNPSrm,    TB_ALIGN_16 },
709    { X86::FsANDPDrr,       X86::FsANDPDrm,     TB_ALIGN_16 },
710    { X86::FsANDPSrr,       X86::FsANDPSrm,     TB_ALIGN_16 },
711    { X86::FsORPDrr,        X86::FsORPDrm,      TB_ALIGN_16 },
712    { X86::FsORPSrr,        X86::FsORPSrm,      TB_ALIGN_16 },
713    { X86::FsXORPDrr,       X86::FsXORPDrm,     TB_ALIGN_16 },
714    { X86::FsXORPSrr,       X86::FsXORPSrm,     TB_ALIGN_16 },
715    { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
716    { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
717    { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
718    { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
719    { X86::IMUL16rr,        X86::IMUL16rm,      0 },
720    { X86::IMUL32rr,        X86::IMUL32rm,      0 },
721    { X86::IMUL64rr,        X86::IMUL64rm,      0 },
722    { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
723    { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
724    { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
725    { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
726    { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
727    { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
728    { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
729    { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
730    { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
731    { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
732    { X86::MAXSDrr,         X86::MAXSDrm,       0 },
733    { X86::MAXSSrr,         X86::MAXSSrm,       0 },
734    { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
735    { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
736    { X86::MINSDrr,         X86::MINSDrm,       0 },
737    { X86::MINSSrr,         X86::MINSSrm,       0 },
738    { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
739    { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
740    { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
741    { X86::MULSDrr,         X86::MULSDrm,       0 },
742    { X86::MULSSrr,         X86::MULSSrm,       0 },
743    { X86::OR16rr,          X86::OR16rm,        0 },
744    { X86::OR32rr,          X86::OR32rm,        0 },
745    { X86::OR64rr,          X86::OR64rm,        0 },
746    { X86::OR8rr,           X86::OR8rm,         0 },
747    { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
748    { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
749    { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
750    { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
751    { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
752    { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
753    { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
754    { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
755    { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
756    { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
757    { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
758    { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
759    { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
760    { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
761    { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
762    { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
763    { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
764    { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
765    { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
766    { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
767    { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
768    { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
769    { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
770    { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
771    { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
772    { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
773    { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
774    { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
775    { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
776    { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
777    { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
778    { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
779    { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
780    { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
781    { X86::PINSRWrri,       X86::PINSRWrmi,     TB_ALIGN_16 },
782    { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
783    { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
784    { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
785    { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
786    { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
787    { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
788    { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
789    { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
790    { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
791    { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
792    { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
793    { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
794    { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
795    { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
796    { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
797    { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
798    { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
799    { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
800    { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
801    { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
802    { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
803    { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
804    { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
805    { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
806    { X86::PSIGNBrr,        X86::PSIGNBrm,      TB_ALIGN_16 },
807    { X86::PSIGNWrr,        X86::PSIGNWrm,      TB_ALIGN_16 },
808    { X86::PSIGNDrr,        X86::PSIGNDrm,      TB_ALIGN_16 },
809    { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
810    { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
811    { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
812    { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
813    { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
814    { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
815    { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
816    { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
817    { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
818    { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
819    { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
820    { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
821    { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
822    { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
823    { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
824    { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
825    { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
826    { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
827    { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
828    { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
829    { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
830    { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
831    { X86::SBB32rr,         X86::SBB32rm,       0 },
832    { X86::SBB64rr,         X86::SBB64rm,       0 },
833    { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
834    { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
835    { X86::SUB16rr,         X86::SUB16rm,       0 },
836    { X86::SUB32rr,         X86::SUB32rm,       0 },
837    { X86::SUB64rr,         X86::SUB64rm,       0 },
838    { X86::SUB8rr,          X86::SUB8rm,        0 },
839    { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
840    { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
841    { X86::SUBSDrr,         X86::SUBSDrm,       0 },
842    { X86::SUBSSrr,         X86::SUBSSrm,       0 },
843    // FIXME: TEST*rr -> swapped operand of TEST*mr.
844    { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
845    { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
846    { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
847    { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
848    { X86::XOR16rr,         X86::XOR16rm,       0 },
849    { X86::XOR32rr,         X86::XOR32rm,       0 },
850    { X86::XOR64rr,         X86::XOR64rm,       0 },
851    { X86::XOR8rr,          X86::XOR8rm,        0 },
852    { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
853    { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
854    // AVX 128-bit versions of foldable instructions
855    { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
856    { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
857    { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
858    { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
859    { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
860    { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
861    { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
862    { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
863    { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
864    { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
865    { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
866    { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
867    { X86::VCVTTPD2DQrr,      X86::VCVTTPD2DQXrm,      0 },
868    { X86::VCVTTPS2DQrr,      X86::VCVTTPS2DQrm,       0 },
869    { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
870    { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
871    { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
872    { X86::VADDPDrr,          X86::VADDPDrm,           0 },
873    { X86::VADDPSrr,          X86::VADDPSrm,           0 },
874    { X86::VADDSDrr,          X86::VADDSDrm,           0 },
875    { X86::VADDSSrr,          X86::VADDSSrm,           0 },
876    { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
877    { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
878    { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
879    { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
880    { X86::VANDPDrr,          X86::VANDPDrm,           0 },
881    { X86::VANDPSrr,          X86::VANDPSrm,           0 },
882    { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
883    { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
884    { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
885    { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
886    { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
887    { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
888    { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
889    { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
890    { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
891    { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
892    { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
893    { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
894    { X86::VFsANDNPDrr,       X86::VFsANDNPDrm,        TB_ALIGN_16 },
895    { X86::VFsANDNPSrr,       X86::VFsANDNPSrm,        TB_ALIGN_16 },
896    { X86::VFsANDPDrr,        X86::VFsANDPDrm,         TB_ALIGN_16 },
897    { X86::VFsANDPSrr,        X86::VFsANDPSrm,         TB_ALIGN_16 },
898    { X86::VFsORPDrr,         X86::VFsORPDrm,          TB_ALIGN_16 },
899    { X86::VFsORPSrr,         X86::VFsORPSrm,          TB_ALIGN_16 },
900    { X86::VFsXORPDrr,        X86::VFsXORPDrm,         TB_ALIGN_16 },
901    { X86::VFsXORPSrr,        X86::VFsXORPSrm,         TB_ALIGN_16 },
902    { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
903    { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
904    { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
905    { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
906    { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
907    { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
908    { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
909    { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
910    { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
911    { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
912    { X86::VMINPDrr,          X86::VMINPDrm,           0 },
913    { X86::VMINPSrr,          X86::VMINPSrm,           0 },
914    { X86::VMINSDrr,          X86::VMINSDrm,           0 },
915    { X86::VMINSSrr,          X86::VMINSSrm,           0 },
916    { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
917    { X86::VMULPDrr,          X86::VMULPDrm,           0 },
918    { X86::VMULPSrr,          X86::VMULPSrm,           0 },
919    { X86::VMULSDrr,          X86::VMULSDrm,           0 },
920    { X86::VMULSSrr,          X86::VMULSSrm,           0 },
921    { X86::VORPDrr,           X86::VORPDrm,            0 },
922    { X86::VORPSrr,           X86::VORPSrm,            0 },
923    { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
924    { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
925    { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
926    { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
927    { X86::VPADDBrr,          X86::VPADDBrm,           0 },
928    { X86::VPADDDrr,          X86::VPADDDrm,           0 },
929    { X86::VPADDQrr,          X86::VPADDQrm,           0 },
930    { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
931    { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
932    { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
933    { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
934    { X86::VPADDWrr,          X86::VPADDWrm,           0 },
935    { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      0 },
936    { X86::VPANDNrr,          X86::VPANDNrm,           0 },
937    { X86::VPANDrr,           X86::VPANDrm,            0 },
938    { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
939    { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
940    { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
941    { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
942    { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
943    { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
944    { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
945    { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
946    { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
947    { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
948    { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
949    { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
950    { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
951    { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
952    { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
953    { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
954    { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
955    { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
956    { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
957    { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
958    { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
959    { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
960    { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
961    { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
962    { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
963    { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
964    { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
965    { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
966    { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
967    { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
968    { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
969    { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
970    { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
971    { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
972    { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
973    { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
974    { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
975    { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
976    { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
977    { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
978    { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
979    { X86::VPORrr,            X86::VPORrm,             0 },
980    { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
981    { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
982    { X86::VPSIGNBrr,         X86::VPSIGNBrm,          0 },
983    { X86::VPSIGNWrr,         X86::VPSIGNWrm,          0 },
984    { X86::VPSIGNDrr,         X86::VPSIGNDrm,          0 },
985    { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
986    { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
987    { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
988    { X86::VPSRADrr,          X86::VPSRADrm,           0 },
989    { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
990    { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
991    { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
992    { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
993    { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
994    { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
995    { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
996    { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
997    { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
998    { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
999    { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1000    { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1001    { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1002    { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1003    { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1004    { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1005    { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1006    { X86::VPXORrr,           X86::VPXORrm,            0 },
1007    { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1008    { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1009    { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1010    { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1011    { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1012    { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1013    { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1014    { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1015    { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1016    { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1017    { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1018    { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1019    // AVX 256-bit foldable instructions
1020    { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1021    { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1022    { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1023    { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1024    { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1025    { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1026    { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1027    { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1028    { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1029    { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1030    { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1031    { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1032    { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1033    { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1034    { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1035    { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1036    { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1037    { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1038    { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1039    { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1040    { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1041    { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1042    { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1043    { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1044    { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1045    { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1046    { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1047    { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1048    { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1049    { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1050    { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1051    { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1052    { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1053    { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1054    { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1055    { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1056    { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1057    { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1058    { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1059    { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1060    { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1061    { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1062    // AVX2 foldable instructions
1063    { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1064    { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1065    { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1066    { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1067    { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1068    { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1069    { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1070    { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1071    { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1072    { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1073    { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1074    { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1075    { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1076    { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      0 },
1077    { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1078    { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1079    { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1080    { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1081    { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1082    { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1083    { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1084    { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1085    { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1086    { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1087    { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1088    { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1089    { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1090    { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1091    { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1092    { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1093    { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1094    { X86::VPERMPDYri,        X86::VPERMPDYmi,         0 },
1095    { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1096    { X86::VPERMQYri,         X86::VPERMQYmi,          0 },
1097    { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1098    { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1099    { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1100    { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1101    { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1102    { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1103    { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
1104    { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1105    { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1106    { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1107    { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1108    { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1109    { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1110    { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1111    { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1112    { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1113    { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1114    { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1115    { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1116    { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1117    { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1118    { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1119    { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
1120    { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1121    { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1122    { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1123    { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1124    { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1125    { X86::VPORYrr,           X86::VPORYrm,            0 },
1126    { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1127    { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1128    { X86::VPSIGNBYrr,        X86::VPSIGNBYrm,         0 },
1129    { X86::VPSIGNWYrr,        X86::VPSIGNWYrm,         0 },
1130    { X86::VPSIGNDYrr,        X86::VPSIGNDYrm,         0 },
1131    { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1132    { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1133    { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1134    { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1135    { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1136    { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1137    { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1138    { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1139    { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1140    { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1141    { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1142    { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1143    { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1144    { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1145    { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1146    { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1147    { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1148    { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1149    { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1150    { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1151    { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1152    { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1153    { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1154    { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1155    { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1156    { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1157    { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1158    { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1159    { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1160    { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1161    { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1162    { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1163    // FIXME: add AVX 256-bit foldable instructions
1164
1165    // FMA4 foldable patterns
1166    { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        0           },
1167    { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        0           },
1168    { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_16 },
1169    { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_16 },
1170    { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       TB_ALIGN_32 },
1171    { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       TB_ALIGN_32 },
1172    { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       0           },
1173    { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       0           },
1174    { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_16 },
1175    { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_16 },
1176    { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      TB_ALIGN_32 },
1177    { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      TB_ALIGN_32 },
1178    { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        0           },
1179    { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        0           },
1180    { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_16 },
1181    { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_16 },
1182    { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       TB_ALIGN_32 },
1183    { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       TB_ALIGN_32 },
1184    { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       0           },
1185    { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       0           },
1186    { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_16 },
1187    { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_16 },
1188    { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      TB_ALIGN_32 },
1189    { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      TB_ALIGN_32 },
1190    { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_16 },
1191    { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_16 },
1192    { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    TB_ALIGN_32 },
1193    { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    TB_ALIGN_32 },
1194    { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_16 },
1195    { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_16 },
1196    { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    TB_ALIGN_32 },
1197    { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    TB_ALIGN_32 },
1198
1199    // BMI/BMI2 foldable instructions
1200    { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1201    { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1202    { X86::MULX32rr,          X86::MULX32rm,            0 },
1203    { X86::MULX64rr,          X86::MULX64rm,            0 },
1204    { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1205    { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1206    { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1207    { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1208
1209    // AVX-512 foldable instructions
1210    { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1211    { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1212    { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1213    { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1214    { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
1215    { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
1216    { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1217    { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1218    { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1219    { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1220    { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1221    { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1222    { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1223    { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1224    { X86::VPERMPDZri,        X86::VPERMPDZmi,          0 },
1225    { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1226    { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1227    { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1228    { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1229    { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1230    { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1231    { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
1232    { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
1233    { X86::VALIGNQrri,        X86::VALIGNQrmi,          0 },
1234    { X86::VALIGNDrri,        X86::VALIGNDrmi,          0 },
1235
1236    // AES foldable instructions
1237    { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
1238    { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
1239    { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
1240    { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
1241    { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       TB_ALIGN_16 },
1242    { X86::VAESDECrr,         X86::VAESDECrm,           TB_ALIGN_16 },
1243    { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       TB_ALIGN_16 },
1244    { X86::VAESENCrr,         X86::VAESENCrm,           TB_ALIGN_16 },
1245
1246    // SHA foldable instructions
1247    { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
1248    { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
1249    { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
1250    { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
1251    { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
1252    { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
1253    { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 },
1254  };
1255
1256  for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
1257    unsigned RegOp = OpTbl2[i].RegOp;
1258    unsigned MemOp = OpTbl2[i].MemOp;
1259    unsigned Flags = OpTbl2[i].Flags;
1260    AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1261                  RegOp, MemOp,
1262                  // Index 2, folded load
1263                  Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1264  }
1265
1266  static const X86OpTblEntry OpTbl3[] = {
1267    // FMA foldable instructions
1268    { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         0 },
1269    { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         0 },
1270    { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         0 },
1271    { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         0 },
1272    { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         0 },
1273    { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         0 },
1274    { X86::VFMADDSSr213r_Int,     X86::VFMADDSSr213m_Int,     0 },
1275    { X86::VFMADDSDr213r_Int,     X86::VFMADDSDr213m_Int,     0 },
1276
1277    { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_16 },
1278    { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_16 },
1279    { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_16 },
1280    { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_16 },
1281    { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_16 },
1282    { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_16 },
1283    { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_32 },
1284    { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_32 },
1285    { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_32 },
1286    { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_32 },
1287    { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_32 },
1288    { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_32 },
1289
1290    { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        0 },
1291    { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        0 },
1292    { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        0 },
1293    { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        0 },
1294    { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        0 },
1295    { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        0 },
1296    { X86::VFNMADDSSr213r_Int,    X86::VFNMADDSSr213m_Int,    0 },
1297    { X86::VFNMADDSDr213r_Int,    X86::VFNMADDSDr213m_Int,    0 },
1298
1299    { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_16 },
1300    { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_16 },
1301    { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_16 },
1302    { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_16 },
1303    { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_16 },
1304    { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_16 },
1305    { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_32 },
1306    { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_32 },
1307    { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_32 },
1308    { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_32 },
1309    { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_32 },
1310    { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_32 },
1311
1312    { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         0 },
1313    { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         0 },
1314    { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         0 },
1315    { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         0 },
1316    { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         0 },
1317    { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         0 },
1318    { X86::VFMSUBSSr213r_Int,     X86::VFMSUBSSr213m_Int,     0 },
1319    { X86::VFMSUBSDr213r_Int,     X86::VFMSUBSDr213m_Int,     0 },
1320
1321    { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_16 },
1322    { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_16 },
1323    { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_16 },
1324    { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_16 },
1325    { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_16 },
1326    { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_16 },
1327    { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_32 },
1328    { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_32 },
1329    { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_32 },
1330    { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_32 },
1331    { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_32 },
1332    { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_32 },
1333
1334    { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        0 },
1335    { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        0 },
1336    { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        0 },
1337    { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        0 },
1338    { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        0 },
1339    { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        0 },
1340    { X86::VFNMSUBSSr213r_Int,    X86::VFNMSUBSSr213m_Int,    0 },
1341    { X86::VFNMSUBSDr213r_Int,    X86::VFNMSUBSDr213m_Int,    0 },
1342
1343    { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_16 },
1344    { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_16 },
1345    { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_16 },
1346    { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_16 },
1347    { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_16 },
1348    { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_16 },
1349    { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_32 },
1350    { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_32 },
1351    { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_32 },
1352    { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_32 },
1353    { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_32 },
1354    { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_32 },
1355
1356    { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_16 },
1357    { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_16 },
1358    { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_16 },
1359    { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_16 },
1360    { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_16 },
1361    { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_16 },
1362    { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_32 },
1363    { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_32 },
1364    { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_32 },
1365    { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_32 },
1366    { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_32 },
1367    { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_32 },
1368
1369    { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_16 },
1370    { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_16 },
1371    { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_16 },
1372    { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_16 },
1373    { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_16 },
1374    { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_16 },
1375    { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_32 },
1376    { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_32 },
1377    { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_32 },
1378    { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_32 },
1379    { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_32 },
1380    { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_32 },
1381
1382    // FMA4 foldable patterns
1383    { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           0           },
1384    { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           0           },
1385    { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_16 },
1386    { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_16 },
1387    { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_32 },
1388    { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_32 },
1389    { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          0           },
1390    { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          0           },
1391    { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_16 },
1392    { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_16 },
1393    { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_32 },
1394    { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_32 },
1395    { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           0           },
1396    { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           0           },
1397    { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_16 },
1398    { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_16 },
1399    { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_32 },
1400    { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_32 },
1401    { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          0           },
1402    { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          0           },
1403    { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_16 },
1404    { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_16 },
1405    { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_32 },
1406    { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_32 },
1407    { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_16 },
1408    { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_16 },
1409    { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_32 },
1410    { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_32 },
1411    { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_16 },
1412    { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_16 },
1413    { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_32 },
1414    { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_32 },
1415    // AVX-512 VPERMI instructions with 3 source operands.
1416    { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
1417    { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
1418    { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
1419    { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
1420  };
1421
1422  for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1423    unsigned RegOp = OpTbl3[i].RegOp;
1424    unsigned MemOp = OpTbl3[i].MemOp;
1425    unsigned Flags = OpTbl3[i].Flags;
1426    AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1427                  RegOp, MemOp,
1428                  // Index 3, folded load
1429                  Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1430  }
1431
1432}
1433
1434void
1435X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1436                            MemOp2RegOpTableType &M2RTable,
1437                            unsigned RegOp, unsigned MemOp, unsigned Flags) {
1438    if ((Flags & TB_NO_FORWARD) == 0) {
1439      assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1440      R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1441    }
1442    if ((Flags & TB_NO_REVERSE) == 0) {
1443      assert(!M2RTable.count(MemOp) &&
1444           "Duplicated entries in unfolding maps?");
1445      M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1446    }
1447}
1448
1449bool
1450X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1451                                    unsigned &SrcReg, unsigned &DstReg,
1452                                    unsigned &SubIdx) const {
1453  switch (MI.getOpcode()) {
1454  default: break;
1455  case X86::MOVSX16rr8:
1456  case X86::MOVZX16rr8:
1457  case X86::MOVSX32rr8:
1458  case X86::MOVZX32rr8:
1459  case X86::MOVSX64rr8:
1460    if (!TM.getSubtarget<X86Subtarget>().is64Bit())
1461      // It's not always legal to reference the low 8-bit of the larger
1462      // register in 32-bit mode.
1463      return false;
1464  case X86::MOVSX32rr16:
1465  case X86::MOVZX32rr16:
1466  case X86::MOVSX64rr16:
1467  case X86::MOVSX64rr32: {
1468    if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1469      // Be conservative.
1470      return false;
1471    SrcReg = MI.getOperand(1).getReg();
1472    DstReg = MI.getOperand(0).getReg();
1473    switch (MI.getOpcode()) {
1474    default: llvm_unreachable("Unreachable!");
1475    case X86::MOVSX16rr8:
1476    case X86::MOVZX16rr8:
1477    case X86::MOVSX32rr8:
1478    case X86::MOVZX32rr8:
1479    case X86::MOVSX64rr8:
1480      SubIdx = X86::sub_8bit;
1481      break;
1482    case X86::MOVSX32rr16:
1483    case X86::MOVZX32rr16:
1484    case X86::MOVSX64rr16:
1485      SubIdx = X86::sub_16bit;
1486      break;
1487    case X86::MOVSX64rr32:
1488      SubIdx = X86::sub_32bit;
1489      break;
1490    }
1491    return true;
1492  }
1493  }
1494  return false;
1495}
1496
1497/// isFrameOperand - Return true and the FrameIndex if the specified
1498/// operand and follow operands form a reference to the stack frame.
1499bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1500                                  int &FrameIndex) const {
1501  if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
1502      MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
1503      MI->getOperand(Op+1).getImm() == 1 &&
1504      MI->getOperand(Op+2).getReg() == 0 &&
1505      MI->getOperand(Op+3).getImm() == 0) {
1506    FrameIndex = MI->getOperand(Op).getIndex();
1507    return true;
1508  }
1509  return false;
1510}
1511
1512static bool isFrameLoadOpcode(int Opcode) {
1513  switch (Opcode) {
1514  default:
1515    return false;
1516  case X86::MOV8rm:
1517  case X86::MOV16rm:
1518  case X86::MOV32rm:
1519  case X86::MOV64rm:
1520  case X86::LD_Fp64m:
1521  case X86::MOVSSrm:
1522  case X86::MOVSDrm:
1523  case X86::MOVAPSrm:
1524  case X86::MOVAPDrm:
1525  case X86::MOVDQArm:
1526  case X86::VMOVSSrm:
1527  case X86::VMOVSDrm:
1528  case X86::VMOVAPSrm:
1529  case X86::VMOVAPDrm:
1530  case X86::VMOVDQArm:
1531  case X86::VMOVAPSYrm:
1532  case X86::VMOVAPDYrm:
1533  case X86::VMOVDQAYrm:
1534  case X86::MMX_MOVD64rm:
1535  case X86::MMX_MOVQ64rm:
1536  case X86::VMOVDQA32rm:
1537  case X86::VMOVDQA64rm:
1538    return true;
1539  }
1540}
1541
1542static bool isFrameStoreOpcode(int Opcode) {
1543  switch (Opcode) {
1544  default: break;
1545  case X86::MOV8mr:
1546  case X86::MOV16mr:
1547  case X86::MOV32mr:
1548  case X86::MOV64mr:
1549  case X86::ST_FpP64m:
1550  case X86::MOVSSmr:
1551  case X86::MOVSDmr:
1552  case X86::MOVAPSmr:
1553  case X86::MOVAPDmr:
1554  case X86::MOVDQAmr:
1555  case X86::VMOVSSmr:
1556  case X86::VMOVSDmr:
1557  case X86::VMOVAPSmr:
1558  case X86::VMOVAPDmr:
1559  case X86::VMOVDQAmr:
1560  case X86::VMOVAPSYmr:
1561  case X86::VMOVAPDYmr:
1562  case X86::VMOVDQAYmr:
1563  case X86::MMX_MOVD64mr:
1564  case X86::MMX_MOVQ64mr:
1565  case X86::MMX_MOVNTQmr:
1566    return true;
1567  }
1568  return false;
1569}
1570
1571unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1572                                           int &FrameIndex) const {
1573  if (isFrameLoadOpcode(MI->getOpcode()))
1574    if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1575      return MI->getOperand(0).getReg();
1576  return 0;
1577}
1578
1579unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1580                                                 int &FrameIndex) const {
1581  if (isFrameLoadOpcode(MI->getOpcode())) {
1582    unsigned Reg;
1583    if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1584      return Reg;
1585    // Check for post-frame index elimination operations
1586    const MachineMemOperand *Dummy;
1587    return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1588  }
1589  return 0;
1590}
1591
1592unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1593                                          int &FrameIndex) const {
1594  if (isFrameStoreOpcode(MI->getOpcode()))
1595    if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1596        isFrameOperand(MI, 0, FrameIndex))
1597      return MI->getOperand(X86::AddrNumOperands).getReg();
1598  return 0;
1599}
1600
1601unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1602                                                int &FrameIndex) const {
1603  if (isFrameStoreOpcode(MI->getOpcode())) {
1604    unsigned Reg;
1605    if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1606      return Reg;
1607    // Check for post-frame index elimination operations
1608    const MachineMemOperand *Dummy;
1609    return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1610  }
1611  return 0;
1612}
1613
1614/// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1615/// X86::MOVPC32r.
1616static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1617  // Don't waste compile time scanning use-def chains of physregs.
1618  if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
1619    return false;
1620  bool isPICBase = false;
1621  for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1622         E = MRI.def_end(); I != E; ++I) {
1623    MachineInstr *DefMI = I.getOperand().getParent();
1624    if (DefMI->getOpcode() != X86::MOVPC32r)
1625      return false;
1626    assert(!isPICBase && "More than one PIC base?");
1627    isPICBase = true;
1628  }
1629  return isPICBase;
1630}
1631
1632bool
1633X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1634                                                AliasAnalysis *AA) const {
1635  switch (MI->getOpcode()) {
1636  default: break;
1637  case X86::MOV8rm:
1638  case X86::MOV16rm:
1639  case X86::MOV32rm:
1640  case X86::MOV64rm:
1641  case X86::LD_Fp64m:
1642  case X86::MOVSSrm:
1643  case X86::MOVSDrm:
1644  case X86::MOVAPSrm:
1645  case X86::MOVUPSrm:
1646  case X86::MOVAPDrm:
1647  case X86::MOVDQArm:
1648  case X86::MOVDQUrm:
1649  case X86::VMOVSSrm:
1650  case X86::VMOVSDrm:
1651  case X86::VMOVAPSrm:
1652  case X86::VMOVUPSrm:
1653  case X86::VMOVAPDrm:
1654  case X86::VMOVDQArm:
1655  case X86::VMOVDQUrm:
1656  case X86::VMOVAPSYrm:
1657  case X86::VMOVUPSYrm:
1658  case X86::VMOVAPDYrm:
1659  case X86::VMOVDQAYrm:
1660  case X86::VMOVDQUYrm:
1661  case X86::MMX_MOVD64rm:
1662  case X86::MMX_MOVQ64rm:
1663  case X86::FsVMOVAPSrm:
1664  case X86::FsVMOVAPDrm:
1665  case X86::FsMOVAPSrm:
1666  case X86::FsMOVAPDrm: {
1667    // Loads from constant pools are trivially rematerializable.
1668    if (MI->getOperand(1).isReg() &&
1669        MI->getOperand(2).isImm() &&
1670        MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1671        MI->isInvariantLoad(AA)) {
1672      unsigned BaseReg = MI->getOperand(1).getReg();
1673      if (BaseReg == 0 || BaseReg == X86::RIP)
1674        return true;
1675      // Allow re-materialization of PIC load.
1676      if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
1677        return false;
1678      const MachineFunction &MF = *MI->getParent()->getParent();
1679      const MachineRegisterInfo &MRI = MF.getRegInfo();
1680      return regIsPICBase(BaseReg, MRI);
1681    }
1682    return false;
1683  }
1684
1685  case X86::LEA32r:
1686  case X86::LEA64r: {
1687    if (MI->getOperand(2).isImm() &&
1688        MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1689        !MI->getOperand(4).isReg()) {
1690      // lea fi#, lea GV, etc. are all rematerializable.
1691      if (!MI->getOperand(1).isReg())
1692        return true;
1693      unsigned BaseReg = MI->getOperand(1).getReg();
1694      if (BaseReg == 0)
1695        return true;
1696      // Allow re-materialization of lea PICBase + x.
1697      const MachineFunction &MF = *MI->getParent()->getParent();
1698      const MachineRegisterInfo &MRI = MF.getRegInfo();
1699      return regIsPICBase(BaseReg, MRI);
1700    }
1701    return false;
1702  }
1703  }
1704
1705  // All other instructions marked M_REMATERIALIZABLE are always trivially
1706  // rematerializable.
1707  return true;
1708}
1709
1710/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
1711/// would clobber the EFLAGS condition register. Note the result may be
1712/// conservative. If it cannot definitely determine the safety after visiting
1713/// a few instructions in each direction it assumes it's not safe.
1714static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1715                                  MachineBasicBlock::iterator I) {
1716  MachineBasicBlock::iterator E = MBB.end();
1717
1718  // For compile time consideration, if we are not able to determine the
1719  // safety after visiting 4 instructions in each direction, we will assume
1720  // it's not safe.
1721  MachineBasicBlock::iterator Iter = I;
1722  for (unsigned i = 0; Iter != E && i < 4; ++i) {
1723    bool SeenDef = false;
1724    for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1725      MachineOperand &MO = Iter->getOperand(j);
1726      if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1727        SeenDef = true;
1728      if (!MO.isReg())
1729        continue;
1730      if (MO.getReg() == X86::EFLAGS) {
1731        if (MO.isUse())
1732          return false;
1733        SeenDef = true;
1734      }
1735    }
1736
1737    if (SeenDef)
1738      // This instruction defines EFLAGS, no need to look any further.
1739      return true;
1740    ++Iter;
1741    // Skip over DBG_VALUE.
1742    while (Iter != E && Iter->isDebugValue())
1743      ++Iter;
1744  }
1745
1746  // It is safe to clobber EFLAGS at the end of a block of no successor has it
1747  // live in.
1748  if (Iter == E) {
1749    for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1750           SE = MBB.succ_end(); SI != SE; ++SI)
1751      if ((*SI)->isLiveIn(X86::EFLAGS))
1752        return false;
1753    return true;
1754  }
1755
1756  MachineBasicBlock::iterator B = MBB.begin();
1757  Iter = I;
1758  for (unsigned i = 0; i < 4; ++i) {
1759    // If we make it to the beginning of the block, it's safe to clobber
1760    // EFLAGS iff EFLAGS is not live-in.
1761    if (Iter == B)
1762      return !MBB.isLiveIn(X86::EFLAGS);
1763
1764    --Iter;
1765    // Skip over DBG_VALUE.
1766    while (Iter != B && Iter->isDebugValue())
1767      --Iter;
1768
1769    bool SawKill = false;
1770    for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1771      MachineOperand &MO = Iter->getOperand(j);
1772      // A register mask may clobber EFLAGS, but we should still look for a
1773      // live EFLAGS def.
1774      if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1775        SawKill = true;
1776      if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1777        if (MO.isDef()) return MO.isDead();
1778        if (MO.isKill()) SawKill = true;
1779      }
1780    }
1781
1782    if (SawKill)
1783      // This instruction kills EFLAGS and doesn't redefine it, so
1784      // there's no need to look further.
1785      return true;
1786  }
1787
1788  // Conservative answer.
1789  return false;
1790}
1791
1792void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1793                                 MachineBasicBlock::iterator I,
1794                                 unsigned DestReg, unsigned SubIdx,
1795                                 const MachineInstr *Orig,
1796                                 const TargetRegisterInfo &TRI) const {
1797  // MOV32r0 is implemented with a xor which clobbers condition code.
1798  // Re-materialize it as movri instructions to avoid side effects.
1799  unsigned Opc = Orig->getOpcode();
1800  if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
1801    DebugLoc DL = Orig->getDebugLoc();
1802    BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
1803      .addImm(0);
1804  } else {
1805    MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1806    MBB.insert(I, MI);
1807  }
1808
1809  MachineInstr *NewMI = prior(I);
1810  NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1811}
1812
1813/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1814/// is not marked dead.
1815static bool hasLiveCondCodeDef(MachineInstr *MI) {
1816  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1817    MachineOperand &MO = MI->getOperand(i);
1818    if (MO.isReg() && MO.isDef() &&
1819        MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1820      return true;
1821    }
1822  }
1823  return false;
1824}
1825
1826/// getTruncatedShiftCount - check whether the shift count for a machine operand
1827/// is non-zero.
1828inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
1829                                              unsigned ShiftAmtOperandIdx) {
1830  // The shift count is six bits with the REX.W prefix and five bits without.
1831  unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
1832  unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
1833  return Imm & ShiftCountMask;
1834}
1835
1836/// isTruncatedShiftCountForLEA - check whether the given shift count is appropriate
1837/// can be represented by a LEA instruction.
1838inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
1839  // Left shift instructions can be transformed into load-effective-address
1840  // instructions if we can encode them appropriately.
1841  // A LEA instruction utilizes a SIB byte to encode it's scale factor.
1842  // The SIB.scale field is two bits wide which means that we can encode any
1843  // shift amount less than 4.
1844  return ShAmt < 4 && ShAmt > 0;
1845}
1846
1847bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
1848                                  unsigned Opc, bool AllowSP,
1849                                  unsigned &NewSrc, bool &isKill, bool &isUndef,
1850                                  MachineOperand &ImplicitOp) const {
1851  MachineFunction &MF = *MI->getParent()->getParent();
1852  const TargetRegisterClass *RC;
1853  if (AllowSP) {
1854    RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1855  } else {
1856    RC = Opc != X86::LEA32r ?
1857      &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1858  }
1859  unsigned SrcReg = Src.getReg();
1860
1861  // For both LEA64 and LEA32 the register already has essentially the right
1862  // type (32-bit or 64-bit) we may just need to forbid SP.
1863  if (Opc != X86::LEA64_32r) {
1864    NewSrc = SrcReg;
1865    isKill = Src.isKill();
1866    isUndef = Src.isUndef();
1867
1868    if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
1869        !MF.getRegInfo().constrainRegClass(NewSrc, RC))
1870      return false;
1871
1872    return true;
1873  }
1874
1875  // This is for an LEA64_32r and incoming registers are 32-bit. One way or
1876  // another we need to add 64-bit registers to the final MI.
1877  if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
1878    ImplicitOp = Src;
1879    ImplicitOp.setImplicit();
1880
1881    NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
1882    MachineBasicBlock::LivenessQueryResult LQR =
1883      MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
1884
1885    switch (LQR) {
1886    case MachineBasicBlock::LQR_Unknown:
1887      // We can't give sane liveness flags to the instruction, abandon LEA
1888      // formation.
1889      return false;
1890    case MachineBasicBlock::LQR_Live:
1891      isKill = MI->killsRegister(SrcReg);
1892      isUndef = false;
1893      break;
1894    default:
1895      // The physreg itself is dead, so we have to use it as an <undef>.
1896      isKill = false;
1897      isUndef = true;
1898      break;
1899    }
1900  } else {
1901    // Virtual register of the wrong class, we have to create a temporary 64-bit
1902    // vreg to feed into the LEA.
1903    NewSrc = MF.getRegInfo().createVirtualRegister(RC);
1904    BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1905            get(TargetOpcode::COPY))
1906      .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1907        .addOperand(Src);
1908
1909    // Which is obviously going to be dead after we're done with it.
1910    isKill = true;
1911    isUndef = false;
1912  }
1913
1914  // We've set all the parameters without issue.
1915  return true;
1916}
1917
1918/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1919/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1920/// to a 32-bit superregister and then truncating back down to a 16-bit
1921/// subregister.
1922MachineInstr *
1923X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1924                                           MachineFunction::iterator &MFI,
1925                                           MachineBasicBlock::iterator &MBBI,
1926                                           LiveVariables *LV) const {
1927  MachineInstr *MI = MBBI;
1928  unsigned Dest = MI->getOperand(0).getReg();
1929  unsigned Src = MI->getOperand(1).getReg();
1930  bool isDead = MI->getOperand(0).isDead();
1931  bool isKill = MI->getOperand(1).isKill();
1932
1933  MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1934  unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1935  unsigned Opc, leaInReg;
1936  if (TM.getSubtarget<X86Subtarget>().is64Bit()) {
1937    Opc = X86::LEA64_32r;
1938    leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1939  } else {
1940    Opc = X86::LEA32r;
1941    leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1942  }
1943
1944  // Build and insert into an implicit UNDEF value. This is OK because
1945  // well be shifting and then extracting the lower 16-bits.
1946  // This has the potential to cause partial register stall. e.g.
1947  //   movw    (%rbp,%rcx,2), %dx
1948  //   leal    -65(%rdx), %esi
1949  // But testing has shown this *does* help performance in 64-bit mode (at
1950  // least on modern x86 machines).
1951  BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1952  MachineInstr *InsMI =
1953    BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1954    .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1955    .addReg(Src, getKillRegState(isKill));
1956
1957  MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1958                                    get(Opc), leaOutReg);
1959  switch (MIOpc) {
1960  default: llvm_unreachable("Unreachable!");
1961  case X86::SHL16ri: {
1962    unsigned ShAmt = MI->getOperand(2).getImm();
1963    MIB.addReg(0).addImm(1 << ShAmt)
1964       .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
1965    break;
1966  }
1967  case X86::INC16r:
1968  case X86::INC64_16r:
1969    addRegOffset(MIB, leaInReg, true, 1);
1970    break;
1971  case X86::DEC16r:
1972  case X86::DEC64_16r:
1973    addRegOffset(MIB, leaInReg, true, -1);
1974    break;
1975  case X86::ADD16ri:
1976  case X86::ADD16ri8:
1977  case X86::ADD16ri_DB:
1978  case X86::ADD16ri8_DB:
1979    addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1980    break;
1981  case X86::ADD16rr:
1982  case X86::ADD16rr_DB: {
1983    unsigned Src2 = MI->getOperand(2).getReg();
1984    bool isKill2 = MI->getOperand(2).isKill();
1985    unsigned leaInReg2 = 0;
1986    MachineInstr *InsMI2 = 0;
1987    if (Src == Src2) {
1988      // ADD16rr %reg1028<kill>, %reg1028
1989      // just a single insert_subreg.
1990      addRegReg(MIB, leaInReg, true, leaInReg, false);
1991    } else {
1992      if (TM.getSubtarget<X86Subtarget>().is64Bit())
1993        leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1994      else
1995        leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1996      // Build and insert into an implicit UNDEF value. This is OK because
1997      // well be shifting and then extracting the lower 16-bits.
1998      BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
1999      InsMI2 =
2000        BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2001        .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2002        .addReg(Src2, getKillRegState(isKill2));
2003      addRegReg(MIB, leaInReg, true, leaInReg2, true);
2004    }
2005    if (LV && isKill2 && InsMI2)
2006      LV->replaceKillInstruction(Src2, MI, InsMI2);
2007    break;
2008  }
2009  }
2010
2011  MachineInstr *NewMI = MIB;
2012  MachineInstr *ExtMI =
2013    BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2014    .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2015    .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2016
2017  if (LV) {
2018    // Update live variables
2019    LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2020    LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2021    if (isKill)
2022      LV->replaceKillInstruction(Src, MI, InsMI);
2023    if (isDead)
2024      LV->replaceKillInstruction(Dest, MI, ExtMI);
2025  }
2026
2027  return ExtMI;
2028}
2029
2030/// convertToThreeAddress - This method must be implemented by targets that
2031/// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
2032/// may be able to convert a two-address instruction into a true
2033/// three-address instruction on demand.  This allows the X86 target (for
2034/// example) to convert ADD and SHL instructions into LEA instructions if they
2035/// would require register copies due to two-addressness.
2036///
2037/// This method returns a null pointer if the transformation cannot be
2038/// performed, otherwise it returns the new instruction.
2039///
2040MachineInstr *
2041X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2042                                    MachineBasicBlock::iterator &MBBI,
2043                                    LiveVariables *LV) const {
2044  MachineInstr *MI = MBBI;
2045
2046  // The following opcodes also sets the condition code register(s). Only
2047  // convert them to equivalent lea if the condition code register def's
2048  // are dead!
2049  if (hasLiveCondCodeDef(MI))
2050    return 0;
2051
2052  MachineFunction &MF = *MI->getParent()->getParent();
2053  // All instructions input are two-addr instructions.  Get the known operands.
2054  const MachineOperand &Dest = MI->getOperand(0);
2055  const MachineOperand &Src = MI->getOperand(1);
2056
2057  MachineInstr *NewMI = NULL;
2058  // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
2059  // we have better subtarget support, enable the 16-bit LEA generation here.
2060  // 16-bit LEA is also slow on Core2.
2061  bool DisableLEA16 = true;
2062  bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2063
2064  unsigned MIOpc = MI->getOpcode();
2065  switch (MIOpc) {
2066  case X86::SHUFPSrri: {
2067    assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
2068    if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
2069
2070    unsigned B = MI->getOperand(1).getReg();
2071    unsigned C = MI->getOperand(2).getReg();
2072    if (B != C) return 0;
2073    unsigned M = MI->getOperand(3).getImm();
2074    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
2075      .addOperand(Dest).addOperand(Src).addImm(M);
2076    break;
2077  }
2078  case X86::SHUFPDrri: {
2079    assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!");
2080    if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
2081
2082    unsigned B = MI->getOperand(1).getReg();
2083    unsigned C = MI->getOperand(2).getReg();
2084    if (B != C) return 0;
2085    unsigned M = MI->getOperand(3).getImm();
2086
2087    // Convert to PSHUFD mask.
2088    M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44;
2089
2090    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
2091      .addOperand(Dest).addOperand(Src).addImm(M);
2092    break;
2093  }
2094  case X86::SHL64ri: {
2095    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2096    unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2097    if (!isTruncatedShiftCountForLEA(ShAmt)) return 0;
2098
2099    // LEA can't handle RSP.
2100    if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2101        !MF.getRegInfo().constrainRegClass(Src.getReg(),
2102                                           &X86::GR64_NOSPRegClass))
2103      return 0;
2104
2105    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2106      .addOperand(Dest)
2107      .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2108    break;
2109  }
2110  case X86::SHL32ri: {
2111    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2112    unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2113    if (!isTruncatedShiftCountForLEA(ShAmt)) return 0;
2114
2115    unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2116
2117    // LEA can't handle ESP.
2118    bool isKill, isUndef;
2119    unsigned SrcReg;
2120    MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2121    if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2122                        SrcReg, isKill, isUndef, ImplicitOp))
2123      return 0;
2124
2125    MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2126      .addOperand(Dest)
2127      .addReg(0).addImm(1 << ShAmt)
2128      .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2129      .addImm(0).addReg(0);
2130    if (ImplicitOp.getReg() != 0)
2131      MIB.addOperand(ImplicitOp);
2132    NewMI = MIB;
2133
2134    break;
2135  }
2136  case X86::SHL16ri: {
2137    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2138    unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2139    if (!isTruncatedShiftCountForLEA(ShAmt)) return 0;
2140
2141    if (DisableLEA16)
2142      return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2143    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2144      .addOperand(Dest)
2145      .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2146    break;
2147  }
2148  default: {
2149
2150    switch (MIOpc) {
2151    default: return 0;
2152    case X86::INC64r:
2153    case X86::INC32r:
2154    case X86::INC64_32r: {
2155      assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2156      unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2157        : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2158      bool isKill, isUndef;
2159      unsigned SrcReg;
2160      MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2161      if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2162                          SrcReg, isKill, isUndef, ImplicitOp))
2163        return 0;
2164
2165      MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2166          .addOperand(Dest)
2167          .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2168      if (ImplicitOp.getReg() != 0)
2169        MIB.addOperand(ImplicitOp);
2170
2171      NewMI = addOffset(MIB, 1);
2172      break;
2173    }
2174    case X86::INC16r:
2175    case X86::INC64_16r:
2176      if (DisableLEA16)
2177        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2178      assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2179      NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2180                        .addOperand(Dest).addOperand(Src), 1);
2181      break;
2182    case X86::DEC64r:
2183    case X86::DEC32r:
2184    case X86::DEC64_32r: {
2185      assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2186      unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2187        : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2188
2189      bool isKill, isUndef;
2190      unsigned SrcReg;
2191      MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2192      if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2193                          SrcReg, isKill, isUndef, ImplicitOp))
2194        return 0;
2195
2196      MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2197          .addOperand(Dest)
2198          .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2199      if (ImplicitOp.getReg() != 0)
2200        MIB.addOperand(ImplicitOp);
2201
2202      NewMI = addOffset(MIB, -1);
2203
2204      break;
2205    }
2206    case X86::DEC16r:
2207    case X86::DEC64_16r:
2208      if (DisableLEA16)
2209        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2210      assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2211      NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2212                        .addOperand(Dest).addOperand(Src), -1);
2213      break;
2214    case X86::ADD64rr:
2215    case X86::ADD64rr_DB:
2216    case X86::ADD32rr:
2217    case X86::ADD32rr_DB: {
2218      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2219      unsigned Opc;
2220      if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2221        Opc = X86::LEA64r;
2222      else
2223        Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2224
2225      bool isKill, isUndef;
2226      unsigned SrcReg;
2227      MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2228      if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2229                          SrcReg, isKill, isUndef, ImplicitOp))
2230        return 0;
2231
2232      const MachineOperand &Src2 = MI->getOperand(2);
2233      bool isKill2, isUndef2;
2234      unsigned SrcReg2;
2235      MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2236      if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2237                          SrcReg2, isKill2, isUndef2, ImplicitOp2))
2238        return 0;
2239
2240      MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2241        .addOperand(Dest);
2242      if (ImplicitOp.getReg() != 0)
2243        MIB.addOperand(ImplicitOp);
2244      if (ImplicitOp2.getReg() != 0)
2245        MIB.addOperand(ImplicitOp2);
2246
2247      NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2248
2249      // Preserve undefness of the operands.
2250      NewMI->getOperand(1).setIsUndef(isUndef);
2251      NewMI->getOperand(3).setIsUndef(isUndef2);
2252
2253      if (LV && Src2.isKill())
2254        LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2255      break;
2256    }
2257    case X86::ADD16rr:
2258    case X86::ADD16rr_DB: {
2259      if (DisableLEA16)
2260        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2261      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2262      unsigned Src2 = MI->getOperand(2).getReg();
2263      bool isKill2 = MI->getOperand(2).isKill();
2264      NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2265                        .addOperand(Dest),
2266                        Src.getReg(), Src.isKill(), Src2, isKill2);
2267
2268      // Preserve undefness of the operands.
2269      bool isUndef = MI->getOperand(1).isUndef();
2270      bool isUndef2 = MI->getOperand(2).isUndef();
2271      NewMI->getOperand(1).setIsUndef(isUndef);
2272      NewMI->getOperand(3).setIsUndef(isUndef2);
2273
2274      if (LV && isKill2)
2275        LV->replaceKillInstruction(Src2, MI, NewMI);
2276      break;
2277    }
2278    case X86::ADD64ri32:
2279    case X86::ADD64ri8:
2280    case X86::ADD64ri32_DB:
2281    case X86::ADD64ri8_DB:
2282      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2283      NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2284                        .addOperand(Dest).addOperand(Src),
2285                        MI->getOperand(2).getImm());
2286      break;
2287    case X86::ADD32ri:
2288    case X86::ADD32ri8:
2289    case X86::ADD32ri_DB:
2290    case X86::ADD32ri8_DB: {
2291      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2292      unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2293
2294      bool isKill, isUndef;
2295      unsigned SrcReg;
2296      MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2297      if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2298                          SrcReg, isKill, isUndef, ImplicitOp))
2299        return 0;
2300
2301      MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2302          .addOperand(Dest)
2303          .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2304      if (ImplicitOp.getReg() != 0)
2305        MIB.addOperand(ImplicitOp);
2306
2307      NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2308      break;
2309    }
2310    case X86::ADD16ri:
2311    case X86::ADD16ri8:
2312    case X86::ADD16ri_DB:
2313    case X86::ADD16ri8_DB:
2314      if (DisableLEA16)
2315        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2316      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2317      NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2318                        .addOperand(Dest).addOperand(Src),
2319                        MI->getOperand(2).getImm());
2320      break;
2321    }
2322  }
2323  }
2324
2325  if (!NewMI) return 0;
2326
2327  if (LV) {  // Update live variables
2328    if (Src.isKill())
2329      LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2330    if (Dest.isDead())
2331      LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2332  }
2333
2334  MFI->insert(MBBI, NewMI);          // Insert the new inst
2335  return NewMI;
2336}
2337
2338/// commuteInstruction - We have a few instructions that must be hacked on to
2339/// commute them.
2340///
2341MachineInstr *
2342X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
2343  switch (MI->getOpcode()) {
2344  case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2345  case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2346  case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2347  case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2348  case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2349  case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2350    unsigned Opc;
2351    unsigned Size;
2352    switch (MI->getOpcode()) {
2353    default: llvm_unreachable("Unreachable!");
2354    case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2355    case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2356    case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2357    case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2358    case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2359    case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2360    }
2361    unsigned Amt = MI->getOperand(3).getImm();
2362    if (NewMI) {
2363      MachineFunction &MF = *MI->getParent()->getParent();
2364      MI = MF.CloneMachineInstr(MI);
2365      NewMI = false;
2366    }
2367    MI->setDesc(get(Opc));
2368    MI->getOperand(3).setImm(Size-Amt);
2369    return TargetInstrInfo::commuteInstruction(MI, NewMI);
2370  }
2371  case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
2372  case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2373  case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
2374  case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2375  case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2376  case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
2377  case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
2378  case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2379  case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2380  case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
2381  case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
2382  case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2383  case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
2384  case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2385  case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
2386  case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2387    unsigned Opc;
2388    switch (MI->getOpcode()) {
2389    default: llvm_unreachable("Unreachable!");
2390    case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
2391    case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
2392    case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
2393    case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2394    case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2395    case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2396    case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
2397    case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
2398    case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
2399    case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2400    case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2401    case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
2402    case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2403    case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2404    case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2405    case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
2406    case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
2407    case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
2408    case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
2409    case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
2410    case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
2411    case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2412    case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2413    case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2414    case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2415    case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2416    case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2417    case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
2418    case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
2419    case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
2420    case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
2421    case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
2422    case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
2423    case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2424    case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2425    case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2426    case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
2427    case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
2428    case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
2429    case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2430    case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2431    case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
2432    case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
2433    case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
2434    case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
2435    case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2436    case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2437    case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
2438    }
2439    if (NewMI) {
2440      MachineFunction &MF = *MI->getParent()->getParent();
2441      MI = MF.CloneMachineInstr(MI);
2442      NewMI = false;
2443    }
2444    MI->setDesc(get(Opc));
2445    // Fallthrough intended.
2446  }
2447  default:
2448    return TargetInstrInfo::commuteInstruction(MI, NewMI);
2449  }
2450}
2451
2452static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
2453  switch (BrOpc) {
2454  default: return X86::COND_INVALID;
2455  case X86::JE_4:  return X86::COND_E;
2456  case X86::JNE_4: return X86::COND_NE;
2457  case X86::JL_4:  return X86::COND_L;
2458  case X86::JLE_4: return X86::COND_LE;
2459  case X86::JG_4:  return X86::COND_G;
2460  case X86::JGE_4: return X86::COND_GE;
2461  case X86::JB_4:  return X86::COND_B;
2462  case X86::JBE_4: return X86::COND_BE;
2463  case X86::JA_4:  return X86::COND_A;
2464  case X86::JAE_4: return X86::COND_AE;
2465  case X86::JS_4:  return X86::COND_S;
2466  case X86::JNS_4: return X86::COND_NS;
2467  case X86::JP_4:  return X86::COND_P;
2468  case X86::JNP_4: return X86::COND_NP;
2469  case X86::JO_4:  return X86::COND_O;
2470  case X86::JNO_4: return X86::COND_NO;
2471  }
2472}
2473
2474/// getCondFromSETOpc - return condition code of a SET opcode.
2475static X86::CondCode getCondFromSETOpc(unsigned Opc) {
2476  switch (Opc) {
2477  default: return X86::COND_INVALID;
2478  case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
2479  case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2480  case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
2481  case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2482  case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
2483  case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
2484  case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2485  case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
2486  case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2487  case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2488  case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2489  case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2490  case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2491  case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
2492  case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
2493  case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
2494  }
2495}
2496
2497/// getCondFromCmovOpc - return condition code of a CMov opcode.
2498X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
2499  switch (Opc) {
2500  default: return X86::COND_INVALID;
2501  case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
2502  case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
2503    return X86::COND_A;
2504  case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2505  case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2506    return X86::COND_AE;
2507  case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
2508  case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
2509    return X86::COND_B;
2510  case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2511  case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2512    return X86::COND_BE;
2513  case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
2514  case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
2515    return X86::COND_E;
2516  case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
2517  case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
2518    return X86::COND_G;
2519  case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2520  case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2521    return X86::COND_GE;
2522  case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
2523  case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
2524    return X86::COND_L;
2525  case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2526  case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2527    return X86::COND_LE;
2528  case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2529  case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2530    return X86::COND_NE;
2531  case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2532  case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2533    return X86::COND_NO;
2534  case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2535  case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2536    return X86::COND_NP;
2537  case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2538  case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2539    return X86::COND_NS;
2540  case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
2541  case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
2542    return X86::COND_O;
2543  case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
2544  case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
2545    return X86::COND_P;
2546  case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
2547  case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
2548    return X86::COND_S;
2549  }
2550}
2551
2552unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2553  switch (CC) {
2554  default: llvm_unreachable("Illegal condition code!");
2555  case X86::COND_E:  return X86::JE_4;
2556  case X86::COND_NE: return X86::JNE_4;
2557  case X86::COND_L:  return X86::JL_4;
2558  case X86::COND_LE: return X86::JLE_4;
2559  case X86::COND_G:  return X86::JG_4;
2560  case X86::COND_GE: return X86::JGE_4;
2561  case X86::COND_B:  return X86::JB_4;
2562  case X86::COND_BE: return X86::JBE_4;
2563  case X86::COND_A:  return X86::JA_4;
2564  case X86::COND_AE: return X86::JAE_4;
2565  case X86::COND_S:  return X86::JS_4;
2566  case X86::COND_NS: return X86::JNS_4;
2567  case X86::COND_P:  return X86::JP_4;
2568  case X86::COND_NP: return X86::JNP_4;
2569  case X86::COND_O:  return X86::JO_4;
2570  case X86::COND_NO: return X86::JNO_4;
2571  }
2572}
2573
2574/// GetOppositeBranchCondition - Return the inverse of the specified condition,
2575/// e.g. turning COND_E to COND_NE.
2576X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2577  switch (CC) {
2578  default: llvm_unreachable("Illegal condition code!");
2579  case X86::COND_E:  return X86::COND_NE;
2580  case X86::COND_NE: return X86::COND_E;
2581  case X86::COND_L:  return X86::COND_GE;
2582  case X86::COND_LE: return X86::COND_G;
2583  case X86::COND_G:  return X86::COND_LE;
2584  case X86::COND_GE: return X86::COND_L;
2585  case X86::COND_B:  return X86::COND_AE;
2586  case X86::COND_BE: return X86::COND_A;
2587  case X86::COND_A:  return X86::COND_BE;
2588  case X86::COND_AE: return X86::COND_B;
2589  case X86::COND_S:  return X86::COND_NS;
2590  case X86::COND_NS: return X86::COND_S;
2591  case X86::COND_P:  return X86::COND_NP;
2592  case X86::COND_NP: return X86::COND_P;
2593  case X86::COND_O:  return X86::COND_NO;
2594  case X86::COND_NO: return X86::COND_O;
2595  }
2596}
2597
2598/// getSwappedCondition - assume the flags are set by MI(a,b), return
2599/// the condition code if we modify the instructions such that flags are
2600/// set by MI(b,a).
2601static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2602  switch (CC) {
2603  default: return X86::COND_INVALID;
2604  case X86::COND_E:  return X86::COND_E;
2605  case X86::COND_NE: return X86::COND_NE;
2606  case X86::COND_L:  return X86::COND_G;
2607  case X86::COND_LE: return X86::COND_GE;
2608  case X86::COND_G:  return X86::COND_L;
2609  case X86::COND_GE: return X86::COND_LE;
2610  case X86::COND_B:  return X86::COND_A;
2611  case X86::COND_BE: return X86::COND_AE;
2612  case X86::COND_A:  return X86::COND_B;
2613  case X86::COND_AE: return X86::COND_BE;
2614  }
2615}
2616
2617/// getSETFromCond - Return a set opcode for the given condition and
2618/// whether it has memory operand.
2619static unsigned getSETFromCond(X86::CondCode CC,
2620                               bool HasMemoryOperand) {
2621  static const uint16_t Opc[16][2] = {
2622    { X86::SETAr,  X86::SETAm  },
2623    { X86::SETAEr, X86::SETAEm },
2624    { X86::SETBr,  X86::SETBm  },
2625    { X86::SETBEr, X86::SETBEm },
2626    { X86::SETEr,  X86::SETEm  },
2627    { X86::SETGr,  X86::SETGm  },
2628    { X86::SETGEr, X86::SETGEm },
2629    { X86::SETLr,  X86::SETLm  },
2630    { X86::SETLEr, X86::SETLEm },
2631    { X86::SETNEr, X86::SETNEm },
2632    { X86::SETNOr, X86::SETNOm },
2633    { X86::SETNPr, X86::SETNPm },
2634    { X86::SETNSr, X86::SETNSm },
2635    { X86::SETOr,  X86::SETOm  },
2636    { X86::SETPr,  X86::SETPm  },
2637    { X86::SETSr,  X86::SETSm  }
2638  };
2639
2640  assert(CC < 16 && "Can only handle standard cond codes");
2641  return Opc[CC][HasMemoryOperand ? 1 : 0];
2642}
2643
2644/// getCMovFromCond - Return a cmov opcode for the given condition,
2645/// register size in bytes, and operand type.
2646static unsigned getCMovFromCond(X86::CondCode CC, unsigned RegBytes,
2647                                bool HasMemoryOperand) {
2648  static const uint16_t Opc[32][3] = {
2649    { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
2650    { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
2651    { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
2652    { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
2653    { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
2654    { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
2655    { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
2656    { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
2657    { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
2658    { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
2659    { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
2660    { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
2661    { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
2662    { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
2663    { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
2664    { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
2665    { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
2666    { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
2667    { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
2668    { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
2669    { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
2670    { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
2671    { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
2672    { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
2673    { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
2674    { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
2675    { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
2676    { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
2677    { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
2678    { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
2679    { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
2680    { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
2681  };
2682
2683  assert(CC < 16 && "Can only handle standard cond codes");
2684  unsigned Idx = HasMemoryOperand ? 16+CC : CC;
2685  switch(RegBytes) {
2686  default: llvm_unreachable("Illegal register size!");
2687  case 2: return Opc[Idx][0];
2688  case 4: return Opc[Idx][1];
2689  case 8: return Opc[Idx][2];
2690  }
2691}
2692
2693bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
2694  if (!MI->isTerminator()) return false;
2695
2696  // Conditional branch is a special case.
2697  if (MI->isBranch() && !MI->isBarrier())
2698    return true;
2699  if (!MI->isPredicable())
2700    return true;
2701  return !isPredicated(MI);
2702}
2703
2704bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
2705                                 MachineBasicBlock *&TBB,
2706                                 MachineBasicBlock *&FBB,
2707                                 SmallVectorImpl<MachineOperand> &Cond,
2708                                 bool AllowModify) const {
2709  // Start from the bottom of the block and work up, examining the
2710  // terminator instructions.
2711  MachineBasicBlock::iterator I = MBB.end();
2712  MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2713  while (I != MBB.begin()) {
2714    --I;
2715    if (I->isDebugValue())
2716      continue;
2717
2718    // Working from the bottom, when we see a non-terminator instruction, we're
2719    // done.
2720    if (!isUnpredicatedTerminator(I))
2721      break;
2722
2723    // A terminator that isn't a branch can't easily be handled by this
2724    // analysis.
2725    if (!I->isBranch())
2726      return true;
2727
2728    // Handle unconditional branches.
2729    if (I->getOpcode() == X86::JMP_4) {
2730      UnCondBrIter = I;
2731
2732      if (!AllowModify) {
2733        TBB = I->getOperand(0).getMBB();
2734        continue;
2735      }
2736
2737      // If the block has any instructions after a JMP, delete them.
2738      while (llvm::next(I) != MBB.end())
2739        llvm::next(I)->eraseFromParent();
2740
2741      Cond.clear();
2742      FBB = 0;
2743
2744      // Delete the JMP if it's equivalent to a fall-through.
2745      if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2746        TBB = 0;
2747        I->eraseFromParent();
2748        I = MBB.end();
2749        UnCondBrIter = MBB.end();
2750        continue;
2751      }
2752
2753      // TBB is used to indicate the unconditional destination.
2754      TBB = I->getOperand(0).getMBB();
2755      continue;
2756    }
2757
2758    // Handle conditional branches.
2759    X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
2760    if (BranchCode == X86::COND_INVALID)
2761      return true;  // Can't handle indirect branch.
2762
2763    // Working from the bottom, handle the first conditional branch.
2764    if (Cond.empty()) {
2765      MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2766      if (AllowModify && UnCondBrIter != MBB.end() &&
2767          MBB.isLayoutSuccessor(TargetBB)) {
2768        // If we can modify the code and it ends in something like:
2769        //
2770        //     jCC L1
2771        //     jmp L2
2772        //   L1:
2773        //     ...
2774        //   L2:
2775        //
2776        // Then we can change this to:
2777        //
2778        //     jnCC L2
2779        //   L1:
2780        //     ...
2781        //   L2:
2782        //
2783        // Which is a bit more efficient.
2784        // We conditionally jump to the fall-through block.
2785        BranchCode = GetOppositeBranchCondition(BranchCode);
2786        unsigned JNCC = GetCondBranchFromCond(BranchCode);
2787        MachineBasicBlock::iterator OldInst = I;
2788
2789        BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2790          .addMBB(UnCondBrIter->getOperand(0).getMBB());
2791        BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2792          .addMBB(TargetBB);
2793
2794        OldInst->eraseFromParent();
2795        UnCondBrIter->eraseFromParent();
2796
2797        // Restart the analysis.
2798        UnCondBrIter = MBB.end();
2799        I = MBB.end();
2800        continue;
2801      }
2802
2803      FBB = TBB;
2804      TBB = I->getOperand(0).getMBB();
2805      Cond.push_back(MachineOperand::CreateImm(BranchCode));
2806      continue;
2807    }
2808
2809    // Handle subsequent conditional branches. Only handle the case where all
2810    // conditional branches branch to the same destination and their condition
2811    // opcodes fit one of the special multi-branch idioms.
2812    assert(Cond.size() == 1);
2813    assert(TBB);
2814
2815    // Only handle the case where all conditional branches branch to the same
2816    // destination.
2817    if (TBB != I->getOperand(0).getMBB())
2818      return true;
2819
2820    // If the conditions are the same, we can leave them alone.
2821    X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2822    if (OldBranchCode == BranchCode)
2823      continue;
2824
2825    // If they differ, see if they fit one of the known patterns. Theoretically,
2826    // we could handle more patterns here, but we shouldn't expect to see them
2827    // if instruction selection has done a reasonable job.
2828    if ((OldBranchCode == X86::COND_NP &&
2829         BranchCode == X86::COND_E) ||
2830        (OldBranchCode == X86::COND_E &&
2831         BranchCode == X86::COND_NP))
2832      BranchCode = X86::COND_NP_OR_E;
2833    else if ((OldBranchCode == X86::COND_P &&
2834              BranchCode == X86::COND_NE) ||
2835             (OldBranchCode == X86::COND_NE &&
2836              BranchCode == X86::COND_P))
2837      BranchCode = X86::COND_NE_OR_P;
2838    else
2839      return true;
2840
2841    // Update the MachineOperand.
2842    Cond[0].setImm(BranchCode);
2843  }
2844
2845  return false;
2846}
2847
2848unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
2849  MachineBasicBlock::iterator I = MBB.end();
2850  unsigned Count = 0;
2851
2852  while (I != MBB.begin()) {
2853    --I;
2854    if (I->isDebugValue())
2855      continue;
2856    if (I->getOpcode() != X86::JMP_4 &&
2857        getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2858      break;
2859    // Remove the branch.
2860    I->eraseFromParent();
2861    I = MBB.end();
2862    ++Count;
2863  }
2864
2865  return Count;
2866}
2867
2868unsigned
2869X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
2870                           MachineBasicBlock *FBB,
2871                           const SmallVectorImpl<MachineOperand> &Cond,
2872                           DebugLoc DL) const {
2873  // Shouldn't be a fall through.
2874  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
2875  assert((Cond.size() == 1 || Cond.size() == 0) &&
2876         "X86 branch conditions have one component!");
2877
2878  if (Cond.empty()) {
2879    // Unconditional branch?
2880    assert(!FBB && "Unconditional branch with multiple successors!");
2881    BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
2882    return 1;
2883  }
2884
2885  // Conditional branch.
2886  unsigned Count = 0;
2887  X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2888  switch (CC) {
2889  case X86::COND_NP_OR_E:
2890    // Synthesize NP_OR_E with two branches.
2891    BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
2892    ++Count;
2893    BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
2894    ++Count;
2895    break;
2896  case X86::COND_NE_OR_P:
2897    // Synthesize NE_OR_P with two branches.
2898    BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
2899    ++Count;
2900    BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
2901    ++Count;
2902    break;
2903  default: {
2904    unsigned Opc = GetCondBranchFromCond(CC);
2905    BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2906    ++Count;
2907  }
2908  }
2909  if (FBB) {
2910    // Two-way Conditional branch. Insert the second branch.
2911    BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
2912    ++Count;
2913  }
2914  return Count;
2915}
2916
2917bool X86InstrInfo::
2918canInsertSelect(const MachineBasicBlock &MBB,
2919                const SmallVectorImpl<MachineOperand> &Cond,
2920                unsigned TrueReg, unsigned FalseReg,
2921                int &CondCycles, int &TrueCycles, int &FalseCycles) const {
2922  // Not all subtargets have cmov instructions.
2923  if (!TM.getSubtarget<X86Subtarget>().hasCMov())
2924    return false;
2925  if (Cond.size() != 1)
2926    return false;
2927  // We cannot do the composite conditions, at least not in SSA form.
2928  if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
2929    return false;
2930
2931  // Check register classes.
2932  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2933  const TargetRegisterClass *RC =
2934    RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2935  if (!RC)
2936    return false;
2937
2938  // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
2939  if (X86::GR16RegClass.hasSubClassEq(RC) ||
2940      X86::GR32RegClass.hasSubClassEq(RC) ||
2941      X86::GR64RegClass.hasSubClassEq(RC)) {
2942    // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
2943    // Bridge. Probably Ivy Bridge as well.
2944    CondCycles = 2;
2945    TrueCycles = 2;
2946    FalseCycles = 2;
2947    return true;
2948  }
2949
2950  // Can't do vectors.
2951  return false;
2952}
2953
2954void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
2955                                MachineBasicBlock::iterator I, DebugLoc DL,
2956                                unsigned DstReg,
2957                                const SmallVectorImpl<MachineOperand> &Cond,
2958                                unsigned TrueReg, unsigned FalseReg) const {
2959   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2960   assert(Cond.size() == 1 && "Invalid Cond array");
2961   unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
2962                                  MRI.getRegClass(DstReg)->getSize(),
2963                                  false/*HasMemoryOperand*/);
2964   BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
2965}
2966
2967/// isHReg - Test if the given register is a physical h register.
2968static bool isHReg(unsigned Reg) {
2969  return X86::GR8_ABCD_HRegClass.contains(Reg);
2970}
2971
2972// Try and copy between VR128/VR64 and GR64 registers.
2973static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2974                                        const X86Subtarget& Subtarget) {
2975
2976
2977  // SrcReg(VR128) -> DestReg(GR64)
2978  // SrcReg(VR64)  -> DestReg(GR64)
2979  // SrcReg(GR64)  -> DestReg(VR128)
2980  // SrcReg(GR64)  -> DestReg(VR64)
2981
2982  bool HasAVX = Subtarget.hasAVX();
2983  bool HasAVX512 = Subtarget.hasAVX512();
2984  if (X86::GR64RegClass.contains(DestReg)) {
2985    if (X86::VR128XRegClass.contains(SrcReg))
2986      // Copy from a VR128 register to a GR64 register.
2987      return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
2988                                               X86::MOVPQIto64rr);
2989    if (X86::VR64RegClass.contains(SrcReg))
2990      // Copy from a VR64 register to a GR64 register.
2991      return X86::MOVSDto64rr;
2992  } else if (X86::GR64RegClass.contains(SrcReg)) {
2993    // Copy from a GR64 register to a VR128 register.
2994    if (X86::VR128XRegClass.contains(DestReg))
2995      return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
2996                                               X86::MOV64toPQIrr);
2997    // Copy from a GR64 register to a VR64 register.
2998    if (X86::VR64RegClass.contains(DestReg))
2999      return X86::MOV64toSDrr;
3000  }
3001
3002  // SrcReg(FR32) -> DestReg(GR32)
3003  // SrcReg(GR32) -> DestReg(FR32)
3004
3005  if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
3006    // Copy from a FR32 register to a GR32 register.
3007    return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
3008
3009  if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
3010    // Copy from a GR32 register to a FR32 register.
3011    return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
3012  return 0;
3013}
3014
3015static
3016unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
3017  if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
3018      X86::VR256XRegClass.contains(DestReg, SrcReg) ||
3019      X86::VR512RegClass.contains(DestReg, SrcReg)) {
3020     DestReg = get512BitSuperRegister(DestReg);
3021     SrcReg = get512BitSuperRegister(SrcReg);
3022     return X86::VMOVAPSZrr;
3023  }
3024  if ((X86::VK8RegClass.contains(DestReg) ||
3025       X86::VK16RegClass.contains(DestReg)) &&
3026      (X86::VK8RegClass.contains(SrcReg) ||
3027       X86::VK16RegClass.contains(SrcReg)))
3028    return X86::KMOVWkk;
3029  return 0;
3030}
3031
3032void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3033                               MachineBasicBlock::iterator MI, DebugLoc DL,
3034                               unsigned DestReg, unsigned SrcReg,
3035                               bool KillSrc) const {
3036  // First deal with the normal symmetric copies.
3037  bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3038  bool HasAVX512 = TM.getSubtarget<X86Subtarget>().hasAVX512();
3039  unsigned Opc = 0;
3040  if (X86::GR64RegClass.contains(DestReg, SrcReg))
3041    Opc = X86::MOV64rr;
3042  else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3043    Opc = X86::MOV32rr;
3044  else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3045    Opc = X86::MOV16rr;
3046  else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3047    // Copying to or from a physical H register on x86-64 requires a NOREX
3048    // move.  Otherwise use a normal move.
3049    if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3050        TM.getSubtarget<X86Subtarget>().is64Bit()) {
3051      Opc = X86::MOV8rr_NOREX;
3052      // Both operands must be encodable without an REX prefix.
3053      assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3054             "8-bit H register can not be copied outside GR8_NOREX");
3055    } else
3056      Opc = X86::MOV8rr;
3057  }
3058  else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3059    Opc = X86::MMX_MOVQ64rr;
3060  else if (HasAVX512)
3061    Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
3062  else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3063    Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3064  else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3065    Opc = X86::VMOVAPSYrr;
3066  if (!Opc)
3067    Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, TM.getSubtarget<X86Subtarget>());
3068
3069  if (Opc) {
3070    BuildMI(MBB, MI, DL, get(Opc), DestReg)
3071      .addReg(SrcReg, getKillRegState(KillSrc));
3072    return;
3073  }
3074
3075  // Moving EFLAGS to / from another register requires a push and a pop.
3076  // Notice that we have to adjust the stack if we don't want to clobber the
3077  // first frame index. See X86FrameLowering.cpp - colobbersTheStack.
3078  if (SrcReg == X86::EFLAGS) {
3079    if (X86::GR64RegClass.contains(DestReg)) {
3080      BuildMI(MBB, MI, DL, get(X86::PUSHF64));
3081      BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
3082      return;
3083    }
3084    if (X86::GR32RegClass.contains(DestReg)) {
3085      BuildMI(MBB, MI, DL, get(X86::PUSHF32));
3086      BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
3087      return;
3088    }
3089  }
3090  if (DestReg == X86::EFLAGS) {
3091    if (X86::GR64RegClass.contains(SrcReg)) {
3092      BuildMI(MBB, MI, DL, get(X86::PUSH64r))
3093        .addReg(SrcReg, getKillRegState(KillSrc));
3094      BuildMI(MBB, MI, DL, get(X86::POPF64));
3095      return;
3096    }
3097    if (X86::GR32RegClass.contains(SrcReg)) {
3098      BuildMI(MBB, MI, DL, get(X86::PUSH32r))
3099        .addReg(SrcReg, getKillRegState(KillSrc));
3100      BuildMI(MBB, MI, DL, get(X86::POPF32));
3101      return;
3102    }
3103  }
3104
3105  DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
3106               << " to " << RI.getName(DestReg) << '\n');
3107  llvm_unreachable("Cannot emit physreg copy instruction");
3108}
3109
3110static unsigned getLoadStoreRegOpcode(unsigned Reg,
3111                                      const TargetRegisterClass *RC,
3112                                      bool isStackAligned,
3113                                      const TargetMachine &TM,
3114                                      bool load) {
3115  if (TM.getSubtarget<X86Subtarget>().hasAVX512()) {
3116    if (X86::VK8RegClass.hasSubClassEq(RC)  ||
3117      X86::VK16RegClass.hasSubClassEq(RC))
3118      return load ? X86::KMOVWkm : X86::KMOVWmk;
3119    if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
3120      return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
3121    if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
3122      return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
3123    if (X86::VR512RegClass.hasSubClassEq(RC))
3124      return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3125  }
3126
3127  bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3128  switch (RC->getSize()) {
3129  default:
3130    llvm_unreachable("Unknown spill size");
3131  case 1:
3132    assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3133    if (TM.getSubtarget<X86Subtarget>().is64Bit())
3134      // Copying to or from a physical H register on x86-64 requires a NOREX
3135      // move.  Otherwise use a normal move.
3136      if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3137        return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3138    return load ? X86::MOV8rm : X86::MOV8mr;
3139  case 2:
3140    assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3141    return load ? X86::MOV16rm : X86::MOV16mr;
3142  case 4:
3143    if (X86::GR32RegClass.hasSubClassEq(RC))
3144      return load ? X86::MOV32rm : X86::MOV32mr;
3145    if (X86::FR32RegClass.hasSubClassEq(RC))
3146      return load ?
3147        (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3148        (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
3149    if (X86::RFP32RegClass.hasSubClassEq(RC))
3150      return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3151    llvm_unreachable("Unknown 4-byte regclass");
3152  case 8:
3153    if (X86::GR64RegClass.hasSubClassEq(RC))
3154      return load ? X86::MOV64rm : X86::MOV64mr;
3155    if (X86::FR64RegClass.hasSubClassEq(RC))
3156      return load ?
3157        (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3158        (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
3159    if (X86::VR64RegClass.hasSubClassEq(RC))
3160      return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3161    if (X86::RFP64RegClass.hasSubClassEq(RC))
3162      return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3163    llvm_unreachable("Unknown 8-byte regclass");
3164  case 10:
3165    assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3166    return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3167  case 16: {
3168    assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
3169    // If stack is realigned we can use aligned stores.
3170    if (isStackAligned)
3171      return load ?
3172        (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
3173        (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
3174    else
3175      return load ?
3176        (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
3177        (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
3178  }
3179  case 32:
3180    assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
3181    // If stack is realigned we can use aligned stores.
3182    if (isStackAligned)
3183      return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
3184    else
3185      return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
3186  case 64:
3187    assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3188    if (isStackAligned)
3189      return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3190    else
3191      return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3192  }
3193}
3194
3195static unsigned getStoreRegOpcode(unsigned SrcReg,
3196                                  const TargetRegisterClass *RC,
3197                                  bool isStackAligned,
3198                                  TargetMachine &TM) {
3199  return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
3200}
3201
3202
3203static unsigned getLoadRegOpcode(unsigned DestReg,
3204                                 const TargetRegisterClass *RC,
3205                                 bool isStackAligned,
3206                                 const TargetMachine &TM) {
3207  return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
3208}
3209
3210void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3211                                       MachineBasicBlock::iterator MI,
3212                                       unsigned SrcReg, bool isKill, int FrameIdx,
3213                                       const TargetRegisterClass *RC,
3214                                       const TargetRegisterInfo *TRI) const {
3215  const MachineFunction &MF = *MBB.getParent();
3216  assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
3217         "Stack slot too small for store");
3218  unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3219  bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
3220    RI.canRealignStack(MF);
3221  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
3222  DebugLoc DL = MBB.findDebugLoc(MI);
3223  addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
3224    .addReg(SrcReg, getKillRegState(isKill));
3225}
3226
3227void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
3228                                  bool isKill,
3229                                  SmallVectorImpl<MachineOperand> &Addr,
3230                                  const TargetRegisterClass *RC,
3231                                  MachineInstr::mmo_iterator MMOBegin,
3232                                  MachineInstr::mmo_iterator MMOEnd,
3233                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
3234  unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3235  bool isAligned = MMOBegin != MMOEnd &&
3236                   (*MMOBegin)->getAlignment() >= Alignment;
3237  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
3238  DebugLoc DL;
3239  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
3240  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3241    MIB.addOperand(Addr[i]);
3242  MIB.addReg(SrcReg, getKillRegState(isKill));
3243  (*MIB).setMemRefs(MMOBegin, MMOEnd);
3244  NewMIs.push_back(MIB);
3245}
3246
3247
3248void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3249                                        MachineBasicBlock::iterator MI,
3250                                        unsigned DestReg, int FrameIdx,
3251                                        const TargetRegisterClass *RC,
3252                                        const TargetRegisterInfo *TRI) const {
3253  const MachineFunction &MF = *MBB.getParent();
3254  unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3255  bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
3256    RI.canRealignStack(MF);
3257  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
3258  DebugLoc DL = MBB.findDebugLoc(MI);
3259  addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
3260}
3261
3262void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
3263                                 SmallVectorImpl<MachineOperand> &Addr,
3264                                 const TargetRegisterClass *RC,
3265                                 MachineInstr::mmo_iterator MMOBegin,
3266                                 MachineInstr::mmo_iterator MMOEnd,
3267                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
3268  unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3269  bool isAligned = MMOBegin != MMOEnd &&
3270                   (*MMOBegin)->getAlignment() >= Alignment;
3271  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
3272  DebugLoc DL;
3273  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
3274  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3275    MIB.addOperand(Addr[i]);
3276  (*MIB).setMemRefs(MMOBegin, MMOEnd);
3277  NewMIs.push_back(MIB);
3278}
3279
3280bool X86InstrInfo::
3281analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
3282               int &CmpMask, int &CmpValue) const {
3283  switch (MI->getOpcode()) {
3284  default: break;
3285  case X86::CMP64ri32:
3286  case X86::CMP64ri8:
3287  case X86::CMP32ri:
3288  case X86::CMP32ri8:
3289  case X86::CMP16ri:
3290  case X86::CMP16ri8:
3291  case X86::CMP8ri:
3292    SrcReg = MI->getOperand(0).getReg();
3293    SrcReg2 = 0;
3294    CmpMask = ~0;
3295    CmpValue = MI->getOperand(1).getImm();
3296    return true;
3297  // A SUB can be used to perform comparison.
3298  case X86::SUB64rm:
3299  case X86::SUB32rm:
3300  case X86::SUB16rm:
3301  case X86::SUB8rm:
3302    SrcReg = MI->getOperand(1).getReg();
3303    SrcReg2 = 0;
3304    CmpMask = ~0;
3305    CmpValue = 0;
3306    return true;
3307  case X86::SUB64rr:
3308  case X86::SUB32rr:
3309  case X86::SUB16rr:
3310  case X86::SUB8rr:
3311    SrcReg = MI->getOperand(1).getReg();
3312    SrcReg2 = MI->getOperand(2).getReg();
3313    CmpMask = ~0;
3314    CmpValue = 0;
3315    return true;
3316  case X86::SUB64ri32:
3317  case X86::SUB64ri8:
3318  case X86::SUB32ri:
3319  case X86::SUB32ri8:
3320  case X86::SUB16ri:
3321  case X86::SUB16ri8:
3322  case X86::SUB8ri:
3323    SrcReg = MI->getOperand(1).getReg();
3324    SrcReg2 = 0;
3325    CmpMask = ~0;
3326    CmpValue = MI->getOperand(2).getImm();
3327    return true;
3328  case X86::CMP64rr:
3329  case X86::CMP32rr:
3330  case X86::CMP16rr:
3331  case X86::CMP8rr:
3332    SrcReg = MI->getOperand(0).getReg();
3333    SrcReg2 = MI->getOperand(1).getReg();
3334    CmpMask = ~0;
3335    CmpValue = 0;
3336    return true;
3337  case X86::TEST8rr:
3338  case X86::TEST16rr:
3339  case X86::TEST32rr:
3340  case X86::TEST64rr:
3341    SrcReg = MI->getOperand(0).getReg();
3342    if (MI->getOperand(1).getReg() != SrcReg) return false;
3343    // Compare against zero.
3344    SrcReg2 = 0;
3345    CmpMask = ~0;
3346    CmpValue = 0;
3347    return true;
3348  }
3349  return false;
3350}
3351
3352/// isRedundantFlagInstr - check whether the first instruction, whose only
3353/// purpose is to update flags, can be made redundant.
3354/// CMPrr can be made redundant by SUBrr if the operands are the same.
3355/// This function can be extended later on.
3356/// SrcReg, SrcRegs: register operands for FlagI.
3357/// ImmValue: immediate for FlagI if it takes an immediate.
3358inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
3359                                        unsigned SrcReg2, int ImmValue,
3360                                        MachineInstr *OI) {
3361  if (((FlagI->getOpcode() == X86::CMP64rr &&
3362        OI->getOpcode() == X86::SUB64rr) ||
3363       (FlagI->getOpcode() == X86::CMP32rr &&
3364        OI->getOpcode() == X86::SUB32rr)||
3365       (FlagI->getOpcode() == X86::CMP16rr &&
3366        OI->getOpcode() == X86::SUB16rr)||
3367       (FlagI->getOpcode() == X86::CMP8rr &&
3368        OI->getOpcode() == X86::SUB8rr)) &&
3369      ((OI->getOperand(1).getReg() == SrcReg &&
3370        OI->getOperand(2).getReg() == SrcReg2) ||
3371       (OI->getOperand(1).getReg() == SrcReg2 &&
3372        OI->getOperand(2).getReg() == SrcReg)))
3373    return true;
3374
3375  if (((FlagI->getOpcode() == X86::CMP64ri32 &&
3376        OI->getOpcode() == X86::SUB64ri32) ||
3377       (FlagI->getOpcode() == X86::CMP64ri8 &&
3378        OI->getOpcode() == X86::SUB64ri8) ||
3379       (FlagI->getOpcode() == X86::CMP32ri &&
3380        OI->getOpcode() == X86::SUB32ri) ||
3381       (FlagI->getOpcode() == X86::CMP32ri8 &&
3382        OI->getOpcode() == X86::SUB32ri8) ||
3383       (FlagI->getOpcode() == X86::CMP16ri &&
3384        OI->getOpcode() == X86::SUB16ri) ||
3385       (FlagI->getOpcode() == X86::CMP16ri8 &&
3386        OI->getOpcode() == X86::SUB16ri8) ||
3387       (FlagI->getOpcode() == X86::CMP8ri &&
3388        OI->getOpcode() == X86::SUB8ri)) &&
3389      OI->getOperand(1).getReg() == SrcReg &&
3390      OI->getOperand(2).getImm() == ImmValue)
3391    return true;
3392  return false;
3393}
3394
3395/// isDefConvertible - check whether the definition can be converted
3396/// to remove a comparison against zero.
3397inline static bool isDefConvertible(MachineInstr *MI) {
3398  switch (MI->getOpcode()) {
3399  default: return false;
3400
3401  // The shift instructions only modify ZF if their shift count is non-zero.
3402  // N.B.: The processor truncates the shift count depending on the encoding.
3403  case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
3404  case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
3405     return getTruncatedShiftCount(MI, 2) != 0;
3406
3407  // Some left shift instructions can be turned into LEA instructions but only
3408  // if their flags aren't used. Avoid transforming such instructions.
3409  case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
3410    unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3411    if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3412    return ShAmt != 0;
3413  }
3414
3415  case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3416  case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3417     return getTruncatedShiftCount(MI, 3) != 0;
3418
3419  case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3420  case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
3421  case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
3422  case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
3423  case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
3424  case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
3425  case X86::DEC64_32r: case X86::DEC64_16r:
3426  case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3427  case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
3428  case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
3429  case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
3430  case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
3431  case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
3432  case X86::INC64_32r: case X86::INC64_16r:
3433  case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3434  case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
3435  case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
3436  case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
3437  case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
3438  case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3439  case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
3440  case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
3441  case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
3442  case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
3443  case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
3444  case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
3445  case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
3446  case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
3447  case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
3448  case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
3449  case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
3450  case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
3451  case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
3452  case X86::ADC32ri:   case X86::ADC32ri8:
3453  case X86::ADC32rr:   case X86::ADC64ri32:
3454  case X86::ADC64ri8:  case X86::ADC64rr:
3455  case X86::SBB32ri:   case X86::SBB32ri8:
3456  case X86::SBB32rr:   case X86::SBB64ri32:
3457  case X86::SBB64ri8:  case X86::SBB64rr:
3458  case X86::ANDN32rr:  case X86::ANDN32rm:
3459  case X86::ANDN64rr:  case X86::ANDN64rm:
3460  case X86::BEXTR32rr: case X86::BEXTR64rr:
3461  case X86::BEXTR32rm: case X86::BEXTR64rm:
3462  case X86::BLSI32rr:  case X86::BLSI32rm:
3463  case X86::BLSI64rr:  case X86::BLSI64rm:
3464  case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3465  case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3466  case X86::BLSR32rr:  case X86::BLSR32rm:
3467  case X86::BLSR64rr:  case X86::BLSR64rm:
3468  case X86::BZHI32rr:  case X86::BZHI32rm:
3469  case X86::BZHI64rr:  case X86::BZHI64rm:
3470  case X86::LZCNT16rr: case X86::LZCNT16rm:
3471  case X86::LZCNT32rr: case X86::LZCNT32rm:
3472  case X86::LZCNT64rr: case X86::LZCNT64rm:
3473  case X86::POPCNT16rr:case X86::POPCNT16rm:
3474  case X86::POPCNT32rr:case X86::POPCNT32rm:
3475  case X86::POPCNT64rr:case X86::POPCNT64rm:
3476  case X86::TZCNT16rr: case X86::TZCNT16rm:
3477  case X86::TZCNT32rr: case X86::TZCNT32rm:
3478  case X86::TZCNT64rr: case X86::TZCNT64rm:
3479    return true;
3480  }
3481}
3482
3483/// optimizeCompareInstr - Check if there exists an earlier instruction that
3484/// operates on the same source operands and sets flags in the same way as
3485/// Compare; remove Compare if possible.
3486bool X86InstrInfo::
3487optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
3488                     int CmpMask, int CmpValue,
3489                     const MachineRegisterInfo *MRI) const {
3490  // Check whether we can replace SUB with CMP.
3491  unsigned NewOpcode = 0;
3492  switch (CmpInstr->getOpcode()) {
3493  default: break;
3494  case X86::SUB64ri32:
3495  case X86::SUB64ri8:
3496  case X86::SUB32ri:
3497  case X86::SUB32ri8:
3498  case X86::SUB16ri:
3499  case X86::SUB16ri8:
3500  case X86::SUB8ri:
3501  case X86::SUB64rm:
3502  case X86::SUB32rm:
3503  case X86::SUB16rm:
3504  case X86::SUB8rm:
3505  case X86::SUB64rr:
3506  case X86::SUB32rr:
3507  case X86::SUB16rr:
3508  case X86::SUB8rr: {
3509    if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
3510      return false;
3511    // There is no use of the destination register, we can replace SUB with CMP.
3512    switch (CmpInstr->getOpcode()) {
3513    default: llvm_unreachable("Unreachable!");
3514    case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
3515    case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
3516    case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
3517    case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
3518    case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
3519    case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
3520    case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
3521    case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
3522    case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3523    case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
3524    case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
3525    case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
3526    case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
3527    case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
3528    case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
3529    }
3530    CmpInstr->setDesc(get(NewOpcode));
3531    CmpInstr->RemoveOperand(0);
3532    // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3533    if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3534        NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3535      return false;
3536  }
3537  }
3538
3539  // Get the unique definition of SrcReg.
3540  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3541  if (!MI) return false;
3542
3543  // CmpInstr is the first instruction of the BB.
3544  MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3545
3546  // If we are comparing against zero, check whether we can use MI to update
3547  // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3548  bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
3549  if (IsCmpZero && (MI->getParent() != CmpInstr->getParent() ||
3550      !isDefConvertible(MI)))
3551    return false;
3552
3553  // We are searching for an earlier instruction that can make CmpInstr
3554  // redundant and that instruction will be saved in Sub.
3555  MachineInstr *Sub = NULL;
3556  const TargetRegisterInfo *TRI = &getRegisterInfo();
3557
3558  // We iterate backward, starting from the instruction before CmpInstr and
3559  // stop when reaching the definition of a source register or done with the BB.
3560  // RI points to the instruction before CmpInstr.
3561  // If the definition is in this basic block, RE points to the definition;
3562  // otherwise, RE is the rend of the basic block.
3563  MachineBasicBlock::reverse_iterator
3564      RI = MachineBasicBlock::reverse_iterator(I),
3565      RE = CmpInstr->getParent() == MI->getParent() ?
3566           MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
3567           CmpInstr->getParent()->rend();
3568  MachineInstr *Movr0Inst = 0;
3569  for (; RI != RE; ++RI) {
3570    MachineInstr *Instr = &*RI;
3571    // Check whether CmpInstr can be made redundant by the current instruction.
3572    if (!IsCmpZero &&
3573        isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
3574      Sub = Instr;
3575      break;
3576    }
3577
3578    if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
3579        Instr->readsRegister(X86::EFLAGS, TRI)) {
3580      // This instruction modifies or uses EFLAGS.
3581
3582      // MOV32r0 etc. are implemented with xor which clobbers condition code.
3583      // They are safe to move up, if the definition to EFLAGS is dead and
3584      // earlier instructions do not read or write EFLAGS.
3585      if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
3586          Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
3587        Movr0Inst = Instr;
3588        continue;
3589      }
3590
3591      // We can't remove CmpInstr.
3592      return false;
3593    }
3594  }
3595
3596  // Return false if no candidates exist.
3597  if (!IsCmpZero && !Sub)
3598    return false;
3599
3600  bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
3601                    Sub->getOperand(2).getReg() == SrcReg);
3602
3603  // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
3604  // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3605  // If we are done with the basic block, we need to check whether EFLAGS is
3606  // live-out.
3607  bool IsSafe = false;
3608  SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
3609  MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
3610  for (++I; I != E; ++I) {
3611    const MachineInstr &Instr = *I;
3612    bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3613    bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3614    // We should check the usage if this instruction uses and updates EFLAGS.
3615    if (!UseEFLAGS && ModifyEFLAGS) {
3616      // It is safe to remove CmpInstr if EFLAGS is updated again.
3617      IsSafe = true;
3618      break;
3619    }
3620    if (!UseEFLAGS && !ModifyEFLAGS)
3621      continue;
3622
3623    // EFLAGS is used by this instruction.
3624    X86::CondCode OldCC;
3625    bool OpcIsSET = false;
3626    if (IsCmpZero || IsSwapped) {
3627      // We decode the condition code from opcode.
3628      if (Instr.isBranch())
3629        OldCC = getCondFromBranchOpc(Instr.getOpcode());
3630      else {
3631        OldCC = getCondFromSETOpc(Instr.getOpcode());
3632        if (OldCC != X86::COND_INVALID)
3633          OpcIsSET = true;
3634        else
3635          OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
3636      }
3637      if (OldCC == X86::COND_INVALID) return false;
3638    }
3639    if (IsCmpZero) {
3640      switch (OldCC) {
3641      default: break;
3642      case X86::COND_A: case X86::COND_AE:
3643      case X86::COND_B: case X86::COND_BE:
3644      case X86::COND_G: case X86::COND_GE:
3645      case X86::COND_L: case X86::COND_LE:
3646      case X86::COND_O: case X86::COND_NO:
3647        // CF and OF are used, we can't perform this optimization.
3648        return false;
3649      }
3650    } else if (IsSwapped) {
3651      // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3652      // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3653      // We swap the condition code and synthesize the new opcode.
3654      X86::CondCode NewCC = getSwappedCondition(OldCC);
3655      if (NewCC == X86::COND_INVALID) return false;
3656
3657      // Synthesize the new opcode.
3658      bool HasMemoryOperand = Instr.hasOneMemOperand();
3659      unsigned NewOpc;
3660      if (Instr.isBranch())
3661        NewOpc = GetCondBranchFromCond(NewCC);
3662      else if(OpcIsSET)
3663        NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
3664      else {
3665        unsigned DstReg = Instr.getOperand(0).getReg();
3666        NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
3667                                 HasMemoryOperand);
3668      }
3669
3670      // Push the MachineInstr to OpsToUpdate.
3671      // If it is safe to remove CmpInstr, the condition code of these
3672      // instructions will be modified.
3673      OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
3674    }
3675    if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3676      // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
3677      IsSafe = true;
3678      break;
3679    }
3680  }
3681
3682  // If EFLAGS is not killed nor re-defined, we should check whether it is
3683  // live-out. If it is live-out, do not optimize.
3684  if ((IsCmpZero || IsSwapped) && !IsSafe) {
3685    MachineBasicBlock *MBB = CmpInstr->getParent();
3686    for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
3687             SE = MBB->succ_end(); SI != SE; ++SI)
3688      if ((*SI)->isLiveIn(X86::EFLAGS))
3689        return false;
3690  }
3691
3692  // The instruction to be updated is either Sub or MI.
3693  Sub = IsCmpZero ? MI : Sub;
3694  // Move Movr0Inst to the appropriate place before Sub.
3695  if (Movr0Inst) {
3696    // Look backwards until we find a def that doesn't use the current EFLAGS.
3697    Def = Sub;
3698    MachineBasicBlock::reverse_iterator
3699      InsertI = MachineBasicBlock::reverse_iterator(++Def),
3700                InsertE = Sub->getParent()->rend();
3701    for (; InsertI != InsertE; ++InsertI) {
3702      MachineInstr *Instr = &*InsertI;
3703      if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
3704          Instr->modifiesRegister(X86::EFLAGS, TRI)) {
3705        Sub->getParent()->remove(Movr0Inst);
3706        Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
3707                                   Movr0Inst);
3708        break;
3709      }
3710    }
3711    if (InsertI == InsertE)
3712      return false;
3713  }
3714
3715  // Make sure Sub instruction defines EFLAGS and mark the def live.
3716  unsigned i = 0, e = Sub->getNumOperands();
3717  for (; i != e; ++i) {
3718    MachineOperand &MO = Sub->getOperand(i);
3719    if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
3720      MO.setIsDead(false);
3721      break;
3722    }
3723  }
3724  assert(i != e && "Unable to locate a def EFLAGS operand");
3725
3726  CmpInstr->eraseFromParent();
3727
3728  // Modify the condition code of instructions in OpsToUpdate.
3729  for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
3730    OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
3731  return true;
3732}
3733
3734/// optimizeLoadInstr - Try to remove the load by folding it to a register
3735/// operand at the use. We fold the load instructions if load defines a virtual
3736/// register, the virtual register is used once in the same BB, and the
3737/// instructions in-between do not load or store, and have no side effects.
3738MachineInstr* X86InstrInfo::
3739optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI,
3740                  unsigned &FoldAsLoadDefReg,
3741                  MachineInstr *&DefMI) const {
3742  if (FoldAsLoadDefReg == 0)
3743    return 0;
3744  // To be conservative, if there exists another load, clear the load candidate.
3745  if (MI->mayLoad()) {
3746    FoldAsLoadDefReg = 0;
3747    return 0;
3748  }
3749
3750  // Check whether we can move DefMI here.
3751  DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
3752  assert(DefMI);
3753  bool SawStore = false;
3754  if (!DefMI->isSafeToMove(this, 0, SawStore))
3755    return 0;
3756
3757  // We try to commute MI if possible.
3758  unsigned IdxEnd = (MI->isCommutable()) ? 2 : 1;
3759  for (unsigned Idx = 0; Idx < IdxEnd; Idx++) {
3760    // Collect information about virtual register operands of MI.
3761    unsigned SrcOperandId = 0;
3762    bool FoundSrcOperand = false;
3763    for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
3764      MachineOperand &MO = MI->getOperand(i);
3765      if (!MO.isReg())
3766        continue;
3767      unsigned Reg = MO.getReg();
3768      if (Reg != FoldAsLoadDefReg)
3769        continue;
3770      // Do not fold if we have a subreg use or a def or multiple uses.
3771      if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
3772        return 0;
3773
3774      SrcOperandId = i;
3775      FoundSrcOperand = true;
3776    }
3777    if (!FoundSrcOperand) return 0;
3778
3779    // Check whether we can fold the def into SrcOperandId.
3780    SmallVector<unsigned, 8> Ops;
3781    Ops.push_back(SrcOperandId);
3782    MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
3783    if (FoldMI) {
3784      FoldAsLoadDefReg = 0;
3785      return FoldMI;
3786    }
3787
3788    if (Idx == 1) {
3789      // MI was changed but it didn't help, commute it back!
3790      commuteInstruction(MI, false);
3791      return 0;
3792    }
3793
3794    // Check whether we can commute MI and enable folding.
3795    if (MI->isCommutable()) {
3796      MachineInstr *NewMI = commuteInstruction(MI, false);
3797      // Unable to commute.
3798      if (!NewMI) return 0;
3799      if (NewMI != MI) {
3800        // New instruction. It doesn't need to be kept.
3801        NewMI->eraseFromParent();
3802        return 0;
3803      }
3804    }
3805  }
3806  return 0;
3807}
3808
3809/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
3810/// instruction with two undef reads of the register being defined.  This is
3811/// used for mapping:
3812///   %xmm4 = V_SET0
3813/// to:
3814///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
3815///
3816static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
3817                             const MCInstrDesc &Desc) {
3818  assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3819  unsigned Reg = MIB->getOperand(0).getReg();
3820  MIB->setDesc(Desc);
3821
3822  // MachineInstr::addOperand() will insert explicit operands before any
3823  // implicit operands.
3824  MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3825  // But we don't trust that.
3826  assert(MIB->getOperand(1).getReg() == Reg &&
3827         MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
3828  return true;
3829}
3830
3831bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
3832  bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3833  MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
3834  switch (MI->getOpcode()) {
3835  case X86::SETB_C8r:
3836    return Expand2AddrUndef(MIB, get(X86::SBB8rr));
3837  case X86::SETB_C16r:
3838    return Expand2AddrUndef(MIB, get(X86::SBB16rr));
3839  case X86::SETB_C32r:
3840    return Expand2AddrUndef(MIB, get(X86::SBB32rr));
3841  case X86::SETB_C64r:
3842    return Expand2AddrUndef(MIB, get(X86::SBB64rr));
3843  case X86::V_SET0:
3844  case X86::FsFLD0SS:
3845  case X86::FsFLD0SD:
3846    return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
3847  case X86::AVX_SET0:
3848    assert(HasAVX && "AVX not supported");
3849    return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
3850  case X86::AVX512_512_SET0:
3851    return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
3852  case X86::V_SETALLONES:
3853    return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
3854  case X86::AVX2_SETALLONES:
3855    return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
3856  case X86::TEST8ri_NOREX:
3857    MI->setDesc(get(X86::TEST8ri));
3858    return true;
3859  case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
3860  case X86::KSET1B:
3861  case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
3862  }
3863  return false;
3864}
3865
3866static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
3867                                     const SmallVectorImpl<MachineOperand> &MOs,
3868                                     MachineInstr *MI,
3869                                     const TargetInstrInfo &TII) {
3870  // Create the base instruction with the memory operand as the first part.
3871  // Omit the implicit operands, something BuildMI can't do.
3872  MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
3873                                              MI->getDebugLoc(), true);
3874  MachineInstrBuilder MIB(MF, NewMI);
3875  unsigned NumAddrOps = MOs.size();
3876  for (unsigned i = 0; i != NumAddrOps; ++i)
3877    MIB.addOperand(MOs[i]);
3878  if (NumAddrOps < 4)  // FrameIndex only
3879    addOffset(MIB, 0);
3880
3881  // Loop over the rest of the ri operands, converting them over.
3882  unsigned NumOps = MI->getDesc().getNumOperands()-2;
3883  for (unsigned i = 0; i != NumOps; ++i) {
3884    MachineOperand &MO = MI->getOperand(i+2);
3885    MIB.addOperand(MO);
3886  }
3887  for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
3888    MachineOperand &MO = MI->getOperand(i);
3889    MIB.addOperand(MO);
3890  }
3891  return MIB;
3892}
3893
3894static MachineInstr *FuseInst(MachineFunction &MF,
3895                              unsigned Opcode, unsigned OpNo,
3896                              const SmallVectorImpl<MachineOperand> &MOs,
3897                              MachineInstr *MI, const TargetInstrInfo &TII) {
3898  // Omit the implicit operands, something BuildMI can't do.
3899  MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
3900                                              MI->getDebugLoc(), true);
3901  MachineInstrBuilder MIB(MF, NewMI);
3902
3903  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
3904    MachineOperand &MO = MI->getOperand(i);
3905    if (i == OpNo) {
3906      assert(MO.isReg() && "Expected to fold into reg operand!");
3907      unsigned NumAddrOps = MOs.size();
3908      for (unsigned i = 0; i != NumAddrOps; ++i)
3909        MIB.addOperand(MOs[i]);
3910      if (NumAddrOps < 4)  // FrameIndex only
3911        addOffset(MIB, 0);
3912    } else {
3913      MIB.addOperand(MO);
3914    }
3915  }
3916  return MIB;
3917}
3918
3919static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
3920                                const SmallVectorImpl<MachineOperand> &MOs,
3921                                MachineInstr *MI) {
3922  MachineFunction &MF = *MI->getParent()->getParent();
3923  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
3924
3925  unsigned NumAddrOps = MOs.size();
3926  for (unsigned i = 0; i != NumAddrOps; ++i)
3927    MIB.addOperand(MOs[i]);
3928  if (NumAddrOps < 4)  // FrameIndex only
3929    addOffset(MIB, 0);
3930  return MIB.addImm(0);
3931}
3932
3933MachineInstr*
3934X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
3935                                    MachineInstr *MI, unsigned i,
3936                                    const SmallVectorImpl<MachineOperand> &MOs,
3937                                    unsigned Size, unsigned Align) const {
3938  const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
3939  bool isCallRegIndirect = TM.getSubtarget<X86Subtarget>().callRegIndirect();
3940  bool isTwoAddrFold = false;
3941
3942  // Atom favors register form of call. So, we do not fold loads into calls
3943  // when X86Subtarget is Atom.
3944  if (isCallRegIndirect &&
3945    (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r)) {
3946    return NULL;
3947  }
3948
3949  unsigned NumOps = MI->getDesc().getNumOperands();
3950  bool isTwoAddr = NumOps > 1 &&
3951    MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
3952
3953  // FIXME: AsmPrinter doesn't know how to handle
3954  // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
3955  if (MI->getOpcode() == X86::ADD32ri &&
3956      MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
3957    return NULL;
3958
3959  MachineInstr *NewMI = NULL;
3960  // Folding a memory location into the two-address part of a two-address
3961  // instruction is different than folding it other places.  It requires
3962  // replacing the *two* registers with the memory location.
3963  if (isTwoAddr && NumOps >= 2 && i < 2 &&
3964      MI->getOperand(0).isReg() &&
3965      MI->getOperand(1).isReg() &&
3966      MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
3967    OpcodeTablePtr = &RegOp2MemOpTable2Addr;
3968    isTwoAddrFold = true;
3969  } else if (i == 0) { // If operand 0
3970    if (MI->getOpcode() == X86::MOV32r0) {
3971      NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
3972      if (NewMI)
3973        return NewMI;
3974    }
3975
3976    OpcodeTablePtr = &RegOp2MemOpTable0;
3977  } else if (i == 1) {
3978    OpcodeTablePtr = &RegOp2MemOpTable1;
3979  } else if (i == 2) {
3980    OpcodeTablePtr = &RegOp2MemOpTable2;
3981  } else if (i == 3) {
3982    OpcodeTablePtr = &RegOp2MemOpTable3;
3983  }
3984
3985  // If table selected...
3986  if (OpcodeTablePtr) {
3987    // Find the Opcode to fuse
3988    DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3989      OpcodeTablePtr->find(MI->getOpcode());
3990    if (I != OpcodeTablePtr->end()) {
3991      unsigned Opcode = I->second.first;
3992      unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
3993      if (Align < MinAlign)
3994        return NULL;
3995      bool NarrowToMOV32rm = false;
3996      if (Size) {
3997        unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
3998        if (Size < RCSize) {
3999          // Check if it's safe to fold the load. If the size of the object is
4000          // narrower than the load width, then it's not.
4001          if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4002            return NULL;
4003          // If this is a 64-bit load, but the spill slot is 32, then we can do
4004          // a 32-bit load which is implicitly zero-extended. This likely is due
4005          // to liveintervalanalysis remat'ing a load from stack slot.
4006          if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
4007            return NULL;
4008          Opcode = X86::MOV32rm;
4009          NarrowToMOV32rm = true;
4010        }
4011      }
4012
4013      if (isTwoAddrFold)
4014        NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
4015      else
4016        NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
4017
4018      if (NarrowToMOV32rm) {
4019        // If this is the special case where we use a MOV32rm to load a 32-bit
4020        // value and zero-extend the top bits. Change the destination register
4021        // to a 32-bit one.
4022        unsigned DstReg = NewMI->getOperand(0).getReg();
4023        if (TargetRegisterInfo::isPhysicalRegister(DstReg))
4024          NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
4025                                                   X86::sub_32bit));
4026        else
4027          NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4028      }
4029      return NewMI;
4030    }
4031  }
4032
4033  // No fusion
4034  if (PrintFailedFusing && !MI->isCopy())
4035    dbgs() << "We failed to fuse operand " << i << " in " << *MI;
4036  return NULL;
4037}
4038
4039/// hasPartialRegUpdate - Return true for all instructions that only update
4040/// the first 32 or 64-bits of the destination register and leave the rest
4041/// unmodified. This can be used to avoid folding loads if the instructions
4042/// only update part of the destination register, and the non-updated part is
4043/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4044/// instructions breaks the partial register dependency and it can improve
4045/// performance. e.g.:
4046///
4047///   movss (%rdi), %xmm0
4048///   cvtss2sd %xmm0, %xmm0
4049///
4050/// Instead of
4051///   cvtss2sd (%rdi), %xmm0
4052///
4053/// FIXME: This should be turned into a TSFlags.
4054///
4055static bool hasPartialRegUpdate(unsigned Opcode) {
4056  switch (Opcode) {
4057  case X86::CVTSI2SSrr:
4058  case X86::CVTSI2SS64rr:
4059  case X86::CVTSI2SDrr:
4060  case X86::CVTSI2SD64rr:
4061  case X86::CVTSD2SSrr:
4062  case X86::Int_CVTSD2SSrr:
4063  case X86::CVTSS2SDrr:
4064  case X86::Int_CVTSS2SDrr:
4065  case X86::RCPSSr:
4066  case X86::RCPSSr_Int:
4067  case X86::ROUNDSDr:
4068  case X86::ROUNDSDr_Int:
4069  case X86::ROUNDSSr:
4070  case X86::ROUNDSSr_Int:
4071  case X86::RSQRTSSr:
4072  case X86::RSQRTSSr_Int:
4073  case X86::SQRTSSr:
4074  case X86::SQRTSSr_Int:
4075    return true;
4076  }
4077
4078  return false;
4079}
4080
4081/// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
4082/// instructions we would like before a partial register update.
4083unsigned X86InstrInfo::
4084getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
4085                             const TargetRegisterInfo *TRI) const {
4086  if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
4087    return 0;
4088
4089  // If MI is marked as reading Reg, the partial register update is wanted.
4090  const MachineOperand &MO = MI->getOperand(0);
4091  unsigned Reg = MO.getReg();
4092  if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4093    if (MO.readsReg() || MI->readsVirtualRegister(Reg))
4094      return 0;
4095  } else {
4096    if (MI->readsRegister(Reg, TRI))
4097      return 0;
4098  }
4099
4100  // If any of the preceding 16 instructions are reading Reg, insert a
4101  // dependency breaking instruction.  The magic number is based on a few
4102  // Nehalem experiments.
4103  return 16;
4104}
4105
4106// Return true for any instruction the copies the high bits of the first source
4107// operand into the unused high bits of the destination operand.
4108static bool hasUndefRegUpdate(unsigned Opcode) {
4109  switch (Opcode) {
4110  case X86::VCVTSI2SSrr:
4111  case X86::Int_VCVTSI2SSrr:
4112  case X86::VCVTSI2SS64rr:
4113  case X86::Int_VCVTSI2SS64rr:
4114  case X86::VCVTSI2SDrr:
4115  case X86::Int_VCVTSI2SDrr:
4116  case X86::VCVTSI2SD64rr:
4117  case X86::Int_VCVTSI2SD64rr:
4118  case X86::VCVTSD2SSrr:
4119  case X86::Int_VCVTSD2SSrr:
4120  case X86::VCVTSS2SDrr:
4121  case X86::Int_VCVTSS2SDrr:
4122  case X86::VRCPSSr:
4123  case X86::VROUNDSDr:
4124  case X86::VROUNDSDr_Int:
4125  case X86::VROUNDSSr:
4126  case X86::VROUNDSSr_Int:
4127  case X86::VRSQRTSSr:
4128  case X86::VSQRTSSr:
4129
4130  // AVX-512
4131  case X86::VCVTSD2SSZrr:
4132  case X86::VCVTSS2SDZrr:
4133    return true;
4134  }
4135
4136  return false;
4137}
4138
4139/// Inform the ExeDepsFix pass how many idle instructions we would like before
4140/// certain undef register reads.
4141///
4142/// This catches the VCVTSI2SD family of instructions:
4143///
4144/// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
4145///
4146/// We should to be careful *not* to catch VXOR idioms which are presumably
4147/// handled specially in the pipeline:
4148///
4149/// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
4150///
4151/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4152/// high bits that are passed-through are not live.
4153unsigned X86InstrInfo::
4154getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
4155                     const TargetRegisterInfo *TRI) const {
4156  if (!hasUndefRegUpdate(MI->getOpcode()))
4157    return 0;
4158
4159  // Set the OpNum parameter to the first source operand.
4160  OpNum = 1;
4161
4162  const MachineOperand &MO = MI->getOperand(OpNum);
4163  if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
4164    // Use the same magic number as getPartialRegUpdateClearance.
4165    return 16;
4166  }
4167  return 0;
4168}
4169
4170void X86InstrInfo::
4171breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
4172                          const TargetRegisterInfo *TRI) const {
4173  unsigned Reg = MI->getOperand(OpNum).getReg();
4174  // If MI kills this register, the false dependence is already broken.
4175  if (MI->killsRegister(Reg, TRI))
4176    return;
4177  if (X86::VR128RegClass.contains(Reg)) {
4178    // These instructions are all floating point domain, so xorps is the best
4179    // choice.
4180    bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
4181    unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
4182    BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
4183      .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4184  } else if (X86::VR256RegClass.contains(Reg)) {
4185    // Use vxorps to clear the full ymm register.
4186    // It wants to read and write the xmm sub-register.
4187    unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4188    BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
4189      .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
4190      .addReg(Reg, RegState::ImplicitDefine);
4191  } else
4192    return;
4193  MI->addRegisterKilled(Reg, TRI, true);
4194}
4195
4196static MachineInstr* foldPatchpoint(MachineFunction &MF,
4197                                    MachineInstr *MI,
4198                                    const SmallVectorImpl<unsigned> &Ops,
4199                                    int FrameIndex,
4200                                    const TargetInstrInfo &TII) {
4201  bool hasDef = MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
4202                !MI->getOperand(0).isImplicit();
4203  unsigned StartIdx = hasDef ? 1 : 0;
4204
4205  MachineInstr *NewMI =
4206    MF.CreateMachineInstr(TII.get(MI->getOpcode()), MI->getDebugLoc(), true);
4207  MachineInstrBuilder MIB(MF, NewMI);
4208
4209  switch (MI->getOpcode()) {
4210  case TargetOpcode::STACKMAP:
4211    StartIdx += 2; // Skip ID, nShadowBytes.
4212    break;
4213  case TargetOpcode::PATCHPOINT:
4214    // Skip ID, numBytes, Target, numArgs.
4215    // For PatchPoint, the call args are not foldable.
4216    StartIdx += MI->getOperand(StartIdx+3).getImm() + 4;
4217    break;
4218  default:
4219    llvm_unreachable("unexpected stackmap opcode");
4220  }
4221
4222  // Return false if any operands requested for folding are not foldable (not
4223  // part of the stackmap's live values).
4224  for (SmallVectorImpl<unsigned>::const_iterator I = Ops.begin(), E = Ops.end();
4225       I != E; ++I) {
4226    if (*I < StartIdx)
4227      return 0;
4228  }
4229  // No need to fold return, the meta data, and function arguments
4230  for (unsigned i = 0; i < StartIdx; ++i)
4231    MIB.addOperand(MI->getOperand(i));
4232
4233  for (unsigned i = StartIdx; i < MI->getNumOperands(); ++i) {
4234    MachineOperand &MO = MI->getOperand(i);
4235    if (std::find(Ops.begin(), Ops.end(), i) != Ops.end()) {
4236      MIB.addOperand(MachineOperand::CreateImm(StackMaps::IndirectMemRefOp));
4237      MIB.addOperand(MachineOperand::CreateFI(FrameIndex));
4238      addOffset(MIB, 0);
4239    }
4240    else
4241      MIB.addOperand(MO);
4242  }
4243  return NewMI;
4244}
4245
4246MachineInstr*
4247X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
4248                                    const SmallVectorImpl<unsigned> &Ops,
4249                                    int FrameIndex) const {
4250  // Special case stack map and patch point intrinsics.
4251  if (MI->getOpcode() == TargetOpcode::STACKMAP
4252      || MI->getOpcode() == TargetOpcode::PATCHPOINT) {
4253    return foldPatchpoint(MF, MI, Ops, FrameIndex, *this);
4254  }
4255  // Check switch flag
4256  if (NoFusing) return NULL;
4257
4258  // Unless optimizing for size, don't fold to avoid partial
4259  // register update stalls
4260  if (!MF.getFunction()->getAttributes().
4261        hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
4262      hasPartialRegUpdate(MI->getOpcode()))
4263    return 0;
4264
4265  const MachineFrameInfo *MFI = MF.getFrameInfo();
4266  unsigned Size = MFI->getObjectSize(FrameIndex);
4267  unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
4268  // If the function stack isn't realigned we don't want to fold instructions
4269  // that need increased alignment.
4270  if (!RI.needsStackRealignment(MF))
4271    Alignment = std::min(Alignment, TM.getFrameLowering()->getStackAlignment());
4272  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4273    unsigned NewOpc = 0;
4274    unsigned RCSize = 0;
4275    switch (MI->getOpcode()) {
4276    default: return NULL;
4277    case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
4278    case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
4279    case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
4280    case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
4281    }
4282    // Check if it's safe to fold the load. If the size of the object is
4283    // narrower than the load width, then it's not.
4284    if (Size < RCSize)
4285      return NULL;
4286    // Change to CMPXXri r, 0 first.
4287    MI->setDesc(get(NewOpc));
4288    MI->getOperand(1).ChangeToImmediate(0);
4289  } else if (Ops.size() != 1)
4290    return NULL;
4291
4292  SmallVector<MachineOperand,4> MOs;
4293  MOs.push_back(MachineOperand::CreateFI(FrameIndex));
4294  return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
4295}
4296
4297MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4298                                                  MachineInstr *MI,
4299                                           const SmallVectorImpl<unsigned> &Ops,
4300                                                  MachineInstr *LoadMI) const {
4301  // If loading from a FrameIndex, fold directly from the FrameIndex.
4302  unsigned NumOps = LoadMI->getDesc().getNumOperands();
4303  int FrameIndex;
4304  if (isLoadFromStackSlot(LoadMI, FrameIndex))
4305    return foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
4306
4307  // Check switch flag
4308  if (NoFusing) return NULL;
4309
4310  // Unless optimizing for size, don't fold to avoid partial
4311  // register update stalls
4312  if (!MF.getFunction()->getAttributes().
4313        hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
4314      hasPartialRegUpdate(MI->getOpcode()))
4315    return 0;
4316
4317  // Determine the alignment of the load.
4318  unsigned Alignment = 0;
4319  if (LoadMI->hasOneMemOperand())
4320    Alignment = (*LoadMI->memoperands_begin())->getAlignment();
4321  else
4322    switch (LoadMI->getOpcode()) {
4323    case X86::AVX2_SETALLONES:
4324    case X86::AVX_SET0:
4325      Alignment = 32;
4326      break;
4327    case X86::V_SET0:
4328    case X86::V_SETALLONES:
4329      Alignment = 16;
4330      break;
4331    case X86::FsFLD0SD:
4332      Alignment = 8;
4333      break;
4334    case X86::FsFLD0SS:
4335      Alignment = 4;
4336      break;
4337    default:
4338      return 0;
4339    }
4340  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4341    unsigned NewOpc = 0;
4342    switch (MI->getOpcode()) {
4343    default: return NULL;
4344    case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
4345    case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
4346    case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
4347    case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
4348    }
4349    // Change to CMPXXri r, 0 first.
4350    MI->setDesc(get(NewOpc));
4351    MI->getOperand(1).ChangeToImmediate(0);
4352  } else if (Ops.size() != 1)
4353    return NULL;
4354
4355  // Make sure the subregisters match.
4356  // Otherwise we risk changing the size of the load.
4357  if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
4358    return NULL;
4359
4360  SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
4361  switch (LoadMI->getOpcode()) {
4362  case X86::V_SET0:
4363  case X86::V_SETALLONES:
4364  case X86::AVX2_SETALLONES:
4365  case X86::AVX_SET0:
4366  case X86::FsFLD0SD:
4367  case X86::FsFLD0SS: {
4368    // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
4369    // Create a constant-pool entry and operands to load from it.
4370
4371    // Medium and large mode can't fold loads this way.
4372    if (TM.getCodeModel() != CodeModel::Small &&
4373        TM.getCodeModel() != CodeModel::Kernel)
4374      return NULL;
4375
4376    // x86-32 PIC requires a PIC base register for constant pools.
4377    unsigned PICBase = 0;
4378    if (TM.getRelocationModel() == Reloc::PIC_) {
4379      if (TM.getSubtarget<X86Subtarget>().is64Bit())
4380        PICBase = X86::RIP;
4381      else
4382        // FIXME: PICBase = getGlobalBaseReg(&MF);
4383        // This doesn't work for several reasons.
4384        // 1. GlobalBaseReg may have been spilled.
4385        // 2. It may not be live at MI.
4386        return NULL;
4387    }
4388
4389    // Create a constant-pool entry.
4390    MachineConstantPool &MCP = *MF.getConstantPool();
4391    Type *Ty;
4392    unsigned Opc = LoadMI->getOpcode();
4393    if (Opc == X86::FsFLD0SS)
4394      Ty = Type::getFloatTy(MF.getFunction()->getContext());
4395    else if (Opc == X86::FsFLD0SD)
4396      Ty = Type::getDoubleTy(MF.getFunction()->getContext());
4397    else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
4398      Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
4399    else
4400      Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
4401
4402    bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
4403    const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
4404                                    Constant::getNullValue(Ty);
4405    unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
4406
4407    // Create operands to load from the constant pool entry.
4408    MOs.push_back(MachineOperand::CreateReg(PICBase, false));
4409    MOs.push_back(MachineOperand::CreateImm(1));
4410    MOs.push_back(MachineOperand::CreateReg(0, false));
4411    MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
4412    MOs.push_back(MachineOperand::CreateReg(0, false));
4413    break;
4414  }
4415  default: {
4416    if ((LoadMI->getOpcode() == X86::MOVSSrm ||
4417         LoadMI->getOpcode() == X86::VMOVSSrm) &&
4418        MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
4419          > 4)
4420      // These instructions only load 32 bits, we can't fold them if the
4421      // destination register is wider than 32 bits (4 bytes).
4422      return NULL;
4423    if ((LoadMI->getOpcode() == X86::MOVSDrm ||
4424         LoadMI->getOpcode() == X86::VMOVSDrm) &&
4425        MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
4426          > 8)
4427      // These instructions only load 64 bits, we can't fold them if the
4428      // destination register is wider than 64 bits (8 bytes).
4429      return NULL;
4430
4431    // Folding a normal load. Just copy the load's address operands.
4432    for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
4433      MOs.push_back(LoadMI->getOperand(i));
4434    break;
4435  }
4436  }
4437  return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
4438}
4439
4440
4441bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
4442                                  const SmallVectorImpl<unsigned> &Ops) const {
4443  // Check switch flag
4444  if (NoFusing) return 0;
4445
4446  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4447    switch (MI->getOpcode()) {
4448    default: return false;
4449    case X86::TEST8rr:
4450    case X86::TEST16rr:
4451    case X86::TEST32rr:
4452    case X86::TEST64rr:
4453      return true;
4454    case X86::ADD32ri:
4455      // FIXME: AsmPrinter doesn't know how to handle
4456      // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4457      if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4458        return false;
4459      break;
4460    }
4461  }
4462
4463  if (Ops.size() != 1)
4464    return false;
4465
4466  unsigned OpNum = Ops[0];
4467  unsigned Opc = MI->getOpcode();
4468  unsigned NumOps = MI->getDesc().getNumOperands();
4469  bool isTwoAddr = NumOps > 1 &&
4470    MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4471
4472  // Folding a memory location into the two-address part of a two-address
4473  // instruction is different than folding it other places.  It requires
4474  // replacing the *two* registers with the memory location.
4475  const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
4476  if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
4477    OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4478  } else if (OpNum == 0) { // If operand 0
4479    if (Opc == X86::MOV32r0)
4480      return true;
4481
4482    OpcodeTablePtr = &RegOp2MemOpTable0;
4483  } else if (OpNum == 1) {
4484    OpcodeTablePtr = &RegOp2MemOpTable1;
4485  } else if (OpNum == 2) {
4486    OpcodeTablePtr = &RegOp2MemOpTable2;
4487  } else if (OpNum == 3) {
4488    OpcodeTablePtr = &RegOp2MemOpTable3;
4489  }
4490
4491  if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
4492    return true;
4493  return TargetInstrInfo::canFoldMemoryOperand(MI, Ops);
4494}
4495
4496bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
4497                                unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
4498                                SmallVectorImpl<MachineInstr*> &NewMIs) const {
4499  DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4500    MemOp2RegOpTable.find(MI->getOpcode());
4501  if (I == MemOp2RegOpTable.end())
4502    return false;
4503  unsigned Opc = I->second.first;
4504  unsigned Index = I->second.second & TB_INDEX_MASK;
4505  bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4506  bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4507  if (UnfoldLoad && !FoldedLoad)
4508    return false;
4509  UnfoldLoad &= FoldedLoad;
4510  if (UnfoldStore && !FoldedStore)
4511    return false;
4512  UnfoldStore &= FoldedStore;
4513
4514  const MCInstrDesc &MCID = get(Opc);
4515  const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
4516  if (!MI->hasOneMemOperand() &&
4517      RC == &X86::VR128RegClass &&
4518      !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
4519    // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
4520    // conservatively assume the address is unaligned. That's bad for
4521    // performance.
4522    return false;
4523  SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
4524  SmallVector<MachineOperand,2> BeforeOps;
4525  SmallVector<MachineOperand,2> AfterOps;
4526  SmallVector<MachineOperand,4> ImpOps;
4527  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4528    MachineOperand &Op = MI->getOperand(i);
4529    if (i >= Index && i < Index + X86::AddrNumOperands)
4530      AddrOps.push_back(Op);
4531    else if (Op.isReg() && Op.isImplicit())
4532      ImpOps.push_back(Op);
4533    else if (i < Index)
4534      BeforeOps.push_back(Op);
4535    else if (i > Index)
4536      AfterOps.push_back(Op);
4537  }
4538
4539  // Emit the load instruction.
4540  if (UnfoldLoad) {
4541    std::pair<MachineInstr::mmo_iterator,
4542              MachineInstr::mmo_iterator> MMOs =
4543      MF.extractLoadMemRefs(MI->memoperands_begin(),
4544                            MI->memoperands_end());
4545    loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
4546    if (UnfoldStore) {
4547      // Address operands cannot be marked isKill.
4548      for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
4549        MachineOperand &MO = NewMIs[0]->getOperand(i);
4550        if (MO.isReg())
4551          MO.setIsKill(false);
4552      }
4553    }
4554  }
4555
4556  // Emit the data processing instruction.
4557  MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
4558  MachineInstrBuilder MIB(MF, DataMI);
4559
4560  if (FoldedStore)
4561    MIB.addReg(Reg, RegState::Define);
4562  for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
4563    MIB.addOperand(BeforeOps[i]);
4564  if (FoldedLoad)
4565    MIB.addReg(Reg);
4566  for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
4567    MIB.addOperand(AfterOps[i]);
4568  for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
4569    MachineOperand &MO = ImpOps[i];
4570    MIB.addReg(MO.getReg(),
4571               getDefRegState(MO.isDef()) |
4572               RegState::Implicit |
4573               getKillRegState(MO.isKill()) |
4574               getDeadRegState(MO.isDead()) |
4575               getUndefRegState(MO.isUndef()));
4576  }
4577  // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
4578  switch (DataMI->getOpcode()) {
4579  default: break;
4580  case X86::CMP64ri32:
4581  case X86::CMP64ri8:
4582  case X86::CMP32ri:
4583  case X86::CMP32ri8:
4584  case X86::CMP16ri:
4585  case X86::CMP16ri8:
4586  case X86::CMP8ri: {
4587    MachineOperand &MO0 = DataMI->getOperand(0);
4588    MachineOperand &MO1 = DataMI->getOperand(1);
4589    if (MO1.getImm() == 0) {
4590      unsigned NewOpc;
4591      switch (DataMI->getOpcode()) {
4592      default: llvm_unreachable("Unreachable!");
4593      case X86::CMP64ri8:
4594      case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
4595      case X86::CMP32ri8:
4596      case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
4597      case X86::CMP16ri8:
4598      case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
4599      case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
4600      }
4601      DataMI->setDesc(get(NewOpc));
4602      MO1.ChangeToRegister(MO0.getReg(), false);
4603    }
4604  }
4605  }
4606  NewMIs.push_back(DataMI);
4607
4608  // Emit the store instruction.
4609  if (UnfoldStore) {
4610    const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
4611    std::pair<MachineInstr::mmo_iterator,
4612              MachineInstr::mmo_iterator> MMOs =
4613      MF.extractStoreMemRefs(MI->memoperands_begin(),
4614                             MI->memoperands_end());
4615    storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
4616  }
4617
4618  return true;
4619}
4620
4621bool
4622X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
4623                                  SmallVectorImpl<SDNode*> &NewNodes) const {
4624  if (!N->isMachineOpcode())
4625    return false;
4626
4627  DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4628    MemOp2RegOpTable.find(N->getMachineOpcode());
4629  if (I == MemOp2RegOpTable.end())
4630    return false;
4631  unsigned Opc = I->second.first;
4632  unsigned Index = I->second.second & TB_INDEX_MASK;
4633  bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4634  bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4635  const MCInstrDesc &MCID = get(Opc);
4636  MachineFunction &MF = DAG.getMachineFunction();
4637  const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
4638  unsigned NumDefs = MCID.NumDefs;
4639  std::vector<SDValue> AddrOps;
4640  std::vector<SDValue> BeforeOps;
4641  std::vector<SDValue> AfterOps;
4642  SDLoc dl(N);
4643  unsigned NumOps = N->getNumOperands();
4644  for (unsigned i = 0; i != NumOps-1; ++i) {
4645    SDValue Op = N->getOperand(i);
4646    if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
4647      AddrOps.push_back(Op);
4648    else if (i < Index-NumDefs)
4649      BeforeOps.push_back(Op);
4650    else if (i > Index-NumDefs)
4651      AfterOps.push_back(Op);
4652  }
4653  SDValue Chain = N->getOperand(NumOps-1);
4654  AddrOps.push_back(Chain);
4655
4656  // Emit the load instruction.
4657  SDNode *Load = 0;
4658  if (FoldedLoad) {
4659    EVT VT = *RC->vt_begin();
4660    std::pair<MachineInstr::mmo_iterator,
4661              MachineInstr::mmo_iterator> MMOs =
4662      MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4663                            cast<MachineSDNode>(N)->memoperands_end());
4664    if (!(*MMOs.first) &&
4665        RC == &X86::VR128RegClass &&
4666        !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
4667      // Do not introduce a slow unaligned load.
4668      return false;
4669    unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4670    bool isAligned = (*MMOs.first) &&
4671                     (*MMOs.first)->getAlignment() >= Alignment;
4672    Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
4673                              VT, MVT::Other, AddrOps);
4674    NewNodes.push_back(Load);
4675
4676    // Preserve memory reference information.
4677    cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
4678  }
4679
4680  // Emit the data processing instruction.
4681  std::vector<EVT> VTs;
4682  const TargetRegisterClass *DstRC = 0;
4683  if (MCID.getNumDefs() > 0) {
4684    DstRC = getRegClass(MCID, 0, &RI, MF);
4685    VTs.push_back(*DstRC->vt_begin());
4686  }
4687  for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
4688    EVT VT = N->getValueType(i);
4689    if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
4690      VTs.push_back(VT);
4691  }
4692  if (Load)
4693    BeforeOps.push_back(SDValue(Load, 0));
4694  std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
4695  SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
4696  NewNodes.push_back(NewNode);
4697
4698  // Emit the store instruction.
4699  if (FoldedStore) {
4700    AddrOps.pop_back();
4701    AddrOps.push_back(SDValue(NewNode, 0));
4702    AddrOps.push_back(Chain);
4703    std::pair<MachineInstr::mmo_iterator,
4704              MachineInstr::mmo_iterator> MMOs =
4705      MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4706                             cast<MachineSDNode>(N)->memoperands_end());
4707    if (!(*MMOs.first) &&
4708        RC == &X86::VR128RegClass &&
4709        !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
4710      // Do not introduce a slow unaligned store.
4711      return false;
4712    unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4713    bool isAligned = (*MMOs.first) &&
4714                     (*MMOs.first)->getAlignment() >= Alignment;
4715    SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
4716                                                         isAligned, TM),
4717                                       dl, MVT::Other, AddrOps);
4718    NewNodes.push_back(Store);
4719
4720    // Preserve memory reference information.
4721    cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
4722  }
4723
4724  return true;
4725}
4726
4727unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
4728                                      bool UnfoldLoad, bool UnfoldStore,
4729                                      unsigned *LoadRegIndex) const {
4730  DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4731    MemOp2RegOpTable.find(Opc);
4732  if (I == MemOp2RegOpTable.end())
4733    return 0;
4734  bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4735  bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4736  if (UnfoldLoad && !FoldedLoad)
4737    return 0;
4738  if (UnfoldStore && !FoldedStore)
4739    return 0;
4740  if (LoadRegIndex)
4741    *LoadRegIndex = I->second.second & TB_INDEX_MASK;
4742  return I->second.first;
4743}
4744
4745bool
4746X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
4747                                     int64_t &Offset1, int64_t &Offset2) const {
4748  if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
4749    return false;
4750  unsigned Opc1 = Load1->getMachineOpcode();
4751  unsigned Opc2 = Load2->getMachineOpcode();
4752  switch (Opc1) {
4753  default: return false;
4754  case X86::MOV8rm:
4755  case X86::MOV16rm:
4756  case X86::MOV32rm:
4757  case X86::MOV64rm:
4758  case X86::LD_Fp32m:
4759  case X86::LD_Fp64m:
4760  case X86::LD_Fp80m:
4761  case X86::MOVSSrm:
4762  case X86::MOVSDrm:
4763  case X86::MMX_MOVD64rm:
4764  case X86::MMX_MOVQ64rm:
4765  case X86::FsMOVAPSrm:
4766  case X86::FsMOVAPDrm:
4767  case X86::MOVAPSrm:
4768  case X86::MOVUPSrm:
4769  case X86::MOVAPDrm:
4770  case X86::MOVDQArm:
4771  case X86::MOVDQUrm:
4772  // AVX load instructions
4773  case X86::VMOVSSrm:
4774  case X86::VMOVSDrm:
4775  case X86::FsVMOVAPSrm:
4776  case X86::FsVMOVAPDrm:
4777  case X86::VMOVAPSrm:
4778  case X86::VMOVUPSrm:
4779  case X86::VMOVAPDrm:
4780  case X86::VMOVDQArm:
4781  case X86::VMOVDQUrm:
4782  case X86::VMOVAPSYrm:
4783  case X86::VMOVUPSYrm:
4784  case X86::VMOVAPDYrm:
4785  case X86::VMOVDQAYrm:
4786  case X86::VMOVDQUYrm:
4787    break;
4788  }
4789  switch (Opc2) {
4790  default: return false;
4791  case X86::MOV8rm:
4792  case X86::MOV16rm:
4793  case X86::MOV32rm:
4794  case X86::MOV64rm:
4795  case X86::LD_Fp32m:
4796  case X86::LD_Fp64m:
4797  case X86::LD_Fp80m:
4798  case X86::MOVSSrm:
4799  case X86::MOVSDrm:
4800  case X86::MMX_MOVD64rm:
4801  case X86::MMX_MOVQ64rm:
4802  case X86::FsMOVAPSrm:
4803  case X86::FsMOVAPDrm:
4804  case X86::MOVAPSrm:
4805  case X86::MOVUPSrm:
4806  case X86::MOVAPDrm:
4807  case X86::MOVDQArm:
4808  case X86::MOVDQUrm:
4809  // AVX load instructions
4810  case X86::VMOVSSrm:
4811  case X86::VMOVSDrm:
4812  case X86::FsVMOVAPSrm:
4813  case X86::FsVMOVAPDrm:
4814  case X86::VMOVAPSrm:
4815  case X86::VMOVUPSrm:
4816  case X86::VMOVAPDrm:
4817  case X86::VMOVDQArm:
4818  case X86::VMOVDQUrm:
4819  case X86::VMOVAPSYrm:
4820  case X86::VMOVUPSYrm:
4821  case X86::VMOVAPDYrm:
4822  case X86::VMOVDQAYrm:
4823  case X86::VMOVDQUYrm:
4824    break;
4825  }
4826
4827  // Check if chain operands and base addresses match.
4828  if (Load1->getOperand(0) != Load2->getOperand(0) ||
4829      Load1->getOperand(5) != Load2->getOperand(5))
4830    return false;
4831  // Segment operands should match as well.
4832  if (Load1->getOperand(4) != Load2->getOperand(4))
4833    return false;
4834  // Scale should be 1, Index should be Reg0.
4835  if (Load1->getOperand(1) == Load2->getOperand(1) &&
4836      Load1->getOperand(2) == Load2->getOperand(2)) {
4837    if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
4838      return false;
4839
4840    // Now let's examine the displacements.
4841    if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
4842        isa<ConstantSDNode>(Load2->getOperand(3))) {
4843      Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
4844      Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
4845      return true;
4846    }
4847  }
4848  return false;
4849}
4850
4851bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
4852                                           int64_t Offset1, int64_t Offset2,
4853                                           unsigned NumLoads) const {
4854  assert(Offset2 > Offset1);
4855  if ((Offset2 - Offset1) / 8 > 64)
4856    return false;
4857
4858  unsigned Opc1 = Load1->getMachineOpcode();
4859  unsigned Opc2 = Load2->getMachineOpcode();
4860  if (Opc1 != Opc2)
4861    return false;  // FIXME: overly conservative?
4862
4863  switch (Opc1) {
4864  default: break;
4865  case X86::LD_Fp32m:
4866  case X86::LD_Fp64m:
4867  case X86::LD_Fp80m:
4868  case X86::MMX_MOVD64rm:
4869  case X86::MMX_MOVQ64rm:
4870    return false;
4871  }
4872
4873  EVT VT = Load1->getValueType(0);
4874  switch (VT.getSimpleVT().SimpleTy) {
4875  default:
4876    // XMM registers. In 64-bit mode we can be a bit more aggressive since we
4877    // have 16 of them to play with.
4878    if (TM.getSubtargetImpl()->is64Bit()) {
4879      if (NumLoads >= 3)
4880        return false;
4881    } else if (NumLoads) {
4882      return false;
4883    }
4884    break;
4885  case MVT::i8:
4886  case MVT::i16:
4887  case MVT::i32:
4888  case MVT::i64:
4889  case MVT::f32:
4890  case MVT::f64:
4891    if (NumLoads)
4892      return false;
4893    break;
4894  }
4895
4896  return true;
4897}
4898
4899bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
4900                                          MachineInstr *Second) const {
4901  // Check if this processor supports macro-fusion. Since this is a minor
4902  // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
4903  // proxy for SandyBridge+.
4904  if (!TM.getSubtarget<X86Subtarget>().hasAVX())
4905    return false;
4906
4907  enum {
4908    FuseTest,
4909    FuseCmp,
4910    FuseInc
4911  } FuseKind;
4912
4913  switch(Second->getOpcode()) {
4914  default:
4915    return false;
4916  case X86::JE_4:
4917  case X86::JNE_4:
4918  case X86::JL_4:
4919  case X86::JLE_4:
4920  case X86::JG_4:
4921  case X86::JGE_4:
4922    FuseKind = FuseInc;
4923    break;
4924  case X86::JB_4:
4925  case X86::JBE_4:
4926  case X86::JA_4:
4927  case X86::JAE_4:
4928    FuseKind = FuseCmp;
4929    break;
4930  case X86::JS_4:
4931  case X86::JNS_4:
4932  case X86::JP_4:
4933  case X86::JNP_4:
4934  case X86::JO_4:
4935  case X86::JNO_4:
4936    FuseKind = FuseTest;
4937    break;
4938  }
4939  switch (First->getOpcode()) {
4940  default:
4941    return false;
4942  case X86::TEST8rr:
4943  case X86::TEST16rr:
4944  case X86::TEST32rr:
4945  case X86::TEST64rr:
4946  case X86::TEST8ri:
4947  case X86::TEST16ri:
4948  case X86::TEST32ri:
4949  case X86::TEST32i32:
4950  case X86::TEST64i32:
4951  case X86::TEST64ri32:
4952  case X86::TEST8rm:
4953  case X86::TEST16rm:
4954  case X86::TEST32rm:
4955  case X86::TEST64rm:
4956  case X86::AND16i16:
4957  case X86::AND16ri:
4958  case X86::AND16ri8:
4959  case X86::AND16rm:
4960  case X86::AND16rr:
4961  case X86::AND32i32:
4962  case X86::AND32ri:
4963  case X86::AND32ri8:
4964  case X86::AND32rm:
4965  case X86::AND32rr:
4966  case X86::AND64i32:
4967  case X86::AND64ri32:
4968  case X86::AND64ri8:
4969  case X86::AND64rm:
4970  case X86::AND64rr:
4971  case X86::AND8i8:
4972  case X86::AND8ri:
4973  case X86::AND8rm:
4974  case X86::AND8rr:
4975    return true;
4976  case X86::CMP16i16:
4977  case X86::CMP16ri:
4978  case X86::CMP16ri8:
4979  case X86::CMP16rm:
4980  case X86::CMP16rr:
4981  case X86::CMP32i32:
4982  case X86::CMP32ri:
4983  case X86::CMP32ri8:
4984  case X86::CMP32rm:
4985  case X86::CMP32rr:
4986  case X86::CMP64i32:
4987  case X86::CMP64ri32:
4988  case X86::CMP64ri8:
4989  case X86::CMP64rm:
4990  case X86::CMP64rr:
4991  case X86::CMP8i8:
4992  case X86::CMP8ri:
4993  case X86::CMP8rm:
4994  case X86::CMP8rr:
4995  case X86::ADD16i16:
4996  case X86::ADD16ri:
4997  case X86::ADD16ri8:
4998  case X86::ADD16ri8_DB:
4999  case X86::ADD16ri_DB:
5000  case X86::ADD16rm:
5001  case X86::ADD16rr:
5002  case X86::ADD16rr_DB:
5003  case X86::ADD32i32:
5004  case X86::ADD32ri:
5005  case X86::ADD32ri8:
5006  case X86::ADD32ri8_DB:
5007  case X86::ADD32ri_DB:
5008  case X86::ADD32rm:
5009  case X86::ADD32rr:
5010  case X86::ADD32rr_DB:
5011  case X86::ADD64i32:
5012  case X86::ADD64ri32:
5013  case X86::ADD64ri32_DB:
5014  case X86::ADD64ri8:
5015  case X86::ADD64ri8_DB:
5016  case X86::ADD64rm:
5017  case X86::ADD64rr:
5018  case X86::ADD64rr_DB:
5019  case X86::ADD8i8:
5020  case X86::ADD8mi:
5021  case X86::ADD8mr:
5022  case X86::ADD8ri:
5023  case X86::ADD8rm:
5024  case X86::ADD8rr:
5025  case X86::SUB16i16:
5026  case X86::SUB16ri:
5027  case X86::SUB16ri8:
5028  case X86::SUB16rm:
5029  case X86::SUB16rr:
5030  case X86::SUB32i32:
5031  case X86::SUB32ri:
5032  case X86::SUB32ri8:
5033  case X86::SUB32rm:
5034  case X86::SUB32rr:
5035  case X86::SUB64i32:
5036  case X86::SUB64ri32:
5037  case X86::SUB64ri8:
5038  case X86::SUB64rm:
5039  case X86::SUB64rr:
5040  case X86::SUB8i8:
5041  case X86::SUB8ri:
5042  case X86::SUB8rm:
5043  case X86::SUB8rr:
5044    return FuseKind == FuseCmp || FuseKind == FuseInc;
5045  case X86::INC16r:
5046  case X86::INC32r:
5047  case X86::INC64_16r:
5048  case X86::INC64_32r:
5049  case X86::INC64r:
5050  case X86::INC8r:
5051  case X86::DEC16r:
5052  case X86::DEC32r:
5053  case X86::DEC64_16r:
5054  case X86::DEC64_32r:
5055  case X86::DEC64r:
5056  case X86::DEC8r:
5057    return FuseKind == FuseInc;
5058  }
5059}
5060
5061bool X86InstrInfo::
5062ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
5063  assert(Cond.size() == 1 && "Invalid X86 branch condition!");
5064  X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
5065  if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
5066    return true;
5067  Cond[0].setImm(GetOppositeBranchCondition(CC));
5068  return false;
5069}
5070
5071bool X86InstrInfo::
5072isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5073  // FIXME: Return false for x87 stack register classes for now. We can't
5074  // allow any loads of these registers before FpGet_ST0_80.
5075  return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
5076           RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
5077}
5078
5079/// getGlobalBaseReg - Return a virtual register initialized with the
5080/// the global base register value. Output instructions required to
5081/// initialize the register in the function entry block, if necessary.
5082///
5083/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
5084///
5085unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
5086  assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
5087         "X86-64 PIC uses RIP relative addressing");
5088
5089  X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5090  unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5091  if (GlobalBaseReg != 0)
5092    return GlobalBaseReg;
5093
5094  // Create the register. The code to initialize it is inserted
5095  // later, by the CGBR pass (below).
5096  MachineRegisterInfo &RegInfo = MF->getRegInfo();
5097  GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
5098  X86FI->setGlobalBaseReg(GlobalBaseReg);
5099  return GlobalBaseReg;
5100}
5101
5102// These are the replaceable SSE instructions. Some of these have Int variants
5103// that we don't include here. We don't want to replace instructions selected
5104// by intrinsics.
5105static const uint16_t ReplaceableInstrs[][3] = {
5106  //PackedSingle     PackedDouble    PackedInt
5107  { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
5108  { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
5109  { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
5110  { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
5111  { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
5112  { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
5113  { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
5114  { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
5115  { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
5116  { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
5117  { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
5118  { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
5119  { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
5120  { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
5121  // AVX 128-bit support
5122  { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
5123  { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
5124  { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
5125  { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
5126  { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
5127  { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5128  { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
5129  { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
5130  { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
5131  { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
5132  { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
5133  { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
5134  { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
5135  { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
5136  // AVX 256-bit support
5137  { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
5138  { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
5139  { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
5140  { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
5141  { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
5142  { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
5143};
5144
5145static const uint16_t ReplaceableInstrsAVX2[][3] = {
5146  //PackedSingle       PackedDouble       PackedInt
5147  { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
5148  { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
5149  { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
5150  { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
5151  { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
5152  { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
5153  { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
5154  { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
5155  { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
5156  { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
5157  { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
5158  { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
5159  { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
5160  { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr }
5161};
5162
5163// FIXME: Some shuffle and unpack instructions have equivalents in different
5164// domains, but they require a bit more work than just switching opcodes.
5165
5166static const uint16_t *lookup(unsigned opcode, unsigned domain) {
5167  for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
5168    if (ReplaceableInstrs[i][domain-1] == opcode)
5169      return ReplaceableInstrs[i];
5170  return 0;
5171}
5172
5173static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
5174  for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
5175    if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
5176      return ReplaceableInstrsAVX2[i];
5177  return 0;
5178}
5179
5180std::pair<uint16_t, uint16_t>
5181X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
5182  uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5183  bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2();
5184  uint16_t validDomains = 0;
5185  if (domain && lookup(MI->getOpcode(), domain))
5186    validDomains = 0xe;
5187  else if (domain && lookupAVX2(MI->getOpcode(), domain))
5188    validDomains = hasAVX2 ? 0xe : 0x6;
5189  return std::make_pair(domain, validDomains);
5190}
5191
5192void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
5193  assert(Domain>0 && Domain<4 && "Invalid execution domain");
5194  uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5195  assert(dom && "Not an SSE instruction");
5196  const uint16_t *table = lookup(MI->getOpcode(), dom);
5197  if (!table) { // try the other table
5198    assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) &&
5199           "256-bit vector operations only available in AVX2");
5200    table = lookupAVX2(MI->getOpcode(), dom);
5201  }
5202  assert(table && "Cannot change domain");
5203  MI->setDesc(get(table[Domain-1]));
5204}
5205
5206/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
5207void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
5208  NopInst.setOpcode(X86::NOOP);
5209}
5210
5211bool X86InstrInfo::isHighLatencyDef(int opc) const {
5212  switch (opc) {
5213  default: return false;
5214  case X86::DIVSDrm:
5215  case X86::DIVSDrm_Int:
5216  case X86::DIVSDrr:
5217  case X86::DIVSDrr_Int:
5218  case X86::DIVSSrm:
5219  case X86::DIVSSrm_Int:
5220  case X86::DIVSSrr:
5221  case X86::DIVSSrr_Int:
5222  case X86::SQRTPDm:
5223  case X86::SQRTPDr:
5224  case X86::SQRTPSm:
5225  case X86::SQRTPSr:
5226  case X86::SQRTSDm:
5227  case X86::SQRTSDm_Int:
5228  case X86::SQRTSDr:
5229  case X86::SQRTSDr_Int:
5230  case X86::SQRTSSm:
5231  case X86::SQRTSSm_Int:
5232  case X86::SQRTSSr:
5233  case X86::SQRTSSr_Int:
5234  // AVX instructions with high latency
5235  case X86::VDIVSDrm:
5236  case X86::VDIVSDrm_Int:
5237  case X86::VDIVSDrr:
5238  case X86::VDIVSDrr_Int:
5239  case X86::VDIVSSrm:
5240  case X86::VDIVSSrm_Int:
5241  case X86::VDIVSSrr:
5242  case X86::VDIVSSrr_Int:
5243  case X86::VSQRTPDm:
5244  case X86::VSQRTPDr:
5245  case X86::VSQRTPSm:
5246  case X86::VSQRTPSr:
5247  case X86::VSQRTSDm:
5248  case X86::VSQRTSDm_Int:
5249  case X86::VSQRTSDr:
5250  case X86::VSQRTSSm:
5251  case X86::VSQRTSSm_Int:
5252  case X86::VSQRTSSr:
5253  case X86::VSQRTPDZrm:
5254  case X86::VSQRTPDZrr:
5255  case X86::VSQRTPSZrm:
5256  case X86::VSQRTPSZrr:
5257  case X86::VSQRTSDZm:
5258  case X86::VSQRTSDZm_Int:
5259  case X86::VSQRTSDZr:
5260  case X86::VSQRTSSZm_Int:
5261  case X86::VSQRTSSZr:
5262  case X86::VSQRTSSZm:
5263  case X86::VDIVSDZrm:
5264  case X86::VDIVSDZrr:
5265  case X86::VDIVSSZrm:
5266  case X86::VDIVSSZrr:
5267
5268  case X86::VGATHERQPSZrm:
5269  case X86::VGATHERQPDZrm:
5270  case X86::VGATHERDPDZrm:
5271  case X86::VGATHERDPSZrm:
5272  case X86::VPGATHERQDZrm:
5273  case X86::VPGATHERQQZrm:
5274  case X86::VPGATHERDDZrm:
5275  case X86::VPGATHERDQZrm:
5276  case X86::VSCATTERQPDZmr:
5277  case X86::VSCATTERQPSZmr:
5278  case X86::VSCATTERDPDZmr:
5279  case X86::VSCATTERDPSZmr:
5280  case X86::VPSCATTERQDZmr:
5281  case X86::VPSCATTERQQZmr:
5282  case X86::VPSCATTERDDZmr:
5283  case X86::VPSCATTERDQZmr:
5284    return true;
5285  }
5286}
5287
5288bool X86InstrInfo::
5289hasHighOperandLatency(const InstrItineraryData *ItinData,
5290                      const MachineRegisterInfo *MRI,
5291                      const MachineInstr *DefMI, unsigned DefIdx,
5292                      const MachineInstr *UseMI, unsigned UseIdx) const {
5293  return isHighLatencyDef(DefMI->getOpcode());
5294}
5295
5296namespace {
5297  /// CGBR - Create Global Base Reg pass. This initializes the PIC
5298  /// global base register for x86-32.
5299  struct CGBR : public MachineFunctionPass {
5300    static char ID;
5301    CGBR() : MachineFunctionPass(ID) {}
5302
5303    virtual bool runOnMachineFunction(MachineFunction &MF) {
5304      const X86TargetMachine *TM =
5305        static_cast<const X86TargetMachine *>(&MF.getTarget());
5306
5307      assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
5308             "X86-64 PIC uses RIP relative addressing");
5309
5310      // Only emit a global base reg in PIC mode.
5311      if (TM->getRelocationModel() != Reloc::PIC_)
5312        return false;
5313
5314      X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
5315      unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5316
5317      // If we didn't need a GlobalBaseReg, don't insert code.
5318      if (GlobalBaseReg == 0)
5319        return false;
5320
5321      // Insert the set of GlobalBaseReg into the first MBB of the function
5322      MachineBasicBlock &FirstMBB = MF.front();
5323      MachineBasicBlock::iterator MBBI = FirstMBB.begin();
5324      DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
5325      MachineRegisterInfo &RegInfo = MF.getRegInfo();
5326      const X86InstrInfo *TII = TM->getInstrInfo();
5327
5328      unsigned PC;
5329      if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
5330        PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
5331      else
5332        PC = GlobalBaseReg;
5333
5334      // Operand of MovePCtoStack is completely ignored by asm printer. It's
5335      // only used in JIT code emission as displacement to pc.
5336      BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
5337
5338      // If we're using vanilla 'GOT' PIC style, we should use relative addressing
5339      // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
5340      if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
5341        // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
5342        BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
5343          .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
5344                                        X86II::MO_GOT_ABSOLUTE_ADDRESS);
5345      }
5346
5347      return true;
5348    }
5349
5350    virtual const char *getPassName() const {
5351      return "X86 PIC Global Base Reg Initialization";
5352    }
5353
5354    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
5355      AU.setPreservesCFG();
5356      MachineFunctionPass::getAnalysisUsage(AU);
5357    }
5358  };
5359}
5360
5361char CGBR::ID = 0;
5362FunctionPass*
5363llvm::createGlobalBaseRegPass() { return new CGBR(); }
5364
5365namespace {
5366  struct LDTLSCleanup : public MachineFunctionPass {
5367    static char ID;
5368    LDTLSCleanup() : MachineFunctionPass(ID) {}
5369
5370    virtual bool runOnMachineFunction(MachineFunction &MF) {
5371      X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
5372      if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
5373        // No point folding accesses if there isn't at least two.
5374        return false;
5375      }
5376
5377      MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
5378      return VisitNode(DT->getRootNode(), 0);
5379    }
5380
5381    // Visit the dominator subtree rooted at Node in pre-order.
5382    // If TLSBaseAddrReg is non-null, then use that to replace any
5383    // TLS_base_addr instructions. Otherwise, create the register
5384    // when the first such instruction is seen, and then use it
5385    // as we encounter more instructions.
5386    bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
5387      MachineBasicBlock *BB = Node->getBlock();
5388      bool Changed = false;
5389
5390      // Traverse the current block.
5391      for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
5392           ++I) {
5393        switch (I->getOpcode()) {
5394          case X86::TLS_base_addr32:
5395          case X86::TLS_base_addr64:
5396            if (TLSBaseAddrReg)
5397              I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
5398            else
5399              I = SetRegister(I, &TLSBaseAddrReg);
5400            Changed = true;
5401            break;
5402          default:
5403            break;
5404        }
5405      }
5406
5407      // Visit the children of this block in the dominator tree.
5408      for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
5409           I != E; ++I) {
5410        Changed |= VisitNode(*I, TLSBaseAddrReg);
5411      }
5412
5413      return Changed;
5414    }
5415
5416    // Replace the TLS_base_addr instruction I with a copy from
5417    // TLSBaseAddrReg, returning the new instruction.
5418    MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
5419                                         unsigned TLSBaseAddrReg) {
5420      MachineFunction *MF = I->getParent()->getParent();
5421      const X86TargetMachine *TM =
5422          static_cast<const X86TargetMachine *>(&MF->getTarget());
5423      const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
5424      const X86InstrInfo *TII = TM->getInstrInfo();
5425
5426      // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
5427      MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
5428                                   TII->get(TargetOpcode::COPY),
5429                                   is64Bit ? X86::RAX : X86::EAX)
5430                                   .addReg(TLSBaseAddrReg);
5431
5432      // Erase the TLS_base_addr instruction.
5433      I->eraseFromParent();
5434
5435      return Copy;
5436    }
5437
5438    // Create a virtal register in *TLSBaseAddrReg, and populate it by
5439    // inserting a copy instruction after I. Returns the new instruction.
5440    MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
5441      MachineFunction *MF = I->getParent()->getParent();
5442      const X86TargetMachine *TM =
5443          static_cast<const X86TargetMachine *>(&MF->getTarget());
5444      const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
5445      const X86InstrInfo *TII = TM->getInstrInfo();
5446
5447      // Create a virtual register for the TLS base address.
5448      MachineRegisterInfo &RegInfo = MF->getRegInfo();
5449      *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
5450                                                      ? &X86::GR64RegClass
5451                                                      : &X86::GR32RegClass);
5452
5453      // Insert a copy from RAX/EAX to TLSBaseAddrReg.
5454      MachineInstr *Next = I->getNextNode();
5455      MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
5456                                   TII->get(TargetOpcode::COPY),
5457                                   *TLSBaseAddrReg)
5458                                   .addReg(is64Bit ? X86::RAX : X86::EAX);
5459
5460      return Copy;
5461    }
5462
5463    virtual const char *getPassName() const {
5464      return "Local Dynamic TLS Access Clean-up";
5465    }
5466
5467    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
5468      AU.setPreservesCFG();
5469      AU.addRequired<MachineDominatorTree>();
5470      MachineFunctionPass::getAnalysisUsage(AU);
5471    }
5472  };
5473}
5474
5475char LDTLSCleanup::ID = 0;
5476FunctionPass*
5477llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
5478