131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
20e0a7a45d3d0a8c865a078459d2e1c6d8967a100Misha Brukman//
3856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell//                     The LLVM Compiler Infrastructure
4856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell//
54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source
64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details.
70e0a7a45d3d0a8c865a078459d2e1c6d8967a100Misha Brukman//
8856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell//===----------------------------------------------------------------------===//
9726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner//
103501feab811c86c9659248a4875fc31a3165f84dChris Lattner// This file contains the X86 implementation of the TargetInstrInfo class.
11726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner//
12726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner//===----------------------------------------------------------------------===//
13726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner
14726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#ifndef X86INSTRUCTIONINFO_H
15726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#define X86INSTRUCTIONINFO_H
16726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner
1736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines#include "MCTargetDesc/X86BaseInfo.h"
18726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#include "X86RegisterInfo.h"
19d68a07650cdb2e18f18f362ba533459aa10e01b6Dan Gohman#include "llvm/ADT/DenseMap.h"
2079aa3417eb6f58d668aadfedf075240a41d35a26Craig Topper#include "llvm/Target/TargetInstrInfo.h"
21726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner
224db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng#define GET_INSTRINFO_HEADER
234db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng#include "X86GenInstrInfo.inc"
244db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng
25d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm {
2625ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng  class X86RegisterInfo;
27cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines  class X86Subtarget;
28d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke
297fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattnernamespace X86 {
307fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner  // X86 specific condition code. These correspond to X86_*_COND in
317fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner  // X86InstrInfo.td. They must be kept in synch.
327fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner  enum CondCode {
337fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner    COND_A  = 0,
347fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner    COND_AE = 1,
357fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner    COND_B  = 2,
367fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner    COND_BE = 3,
377fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner    COND_E  = 4,
387fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner    COND_G  = 5,
397fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner    COND_GE = 6,
407fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner    COND_L  = 7,
417fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner    COND_LE = 8,
427fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner    COND_NE = 9,
437fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner    COND_NO = 10,
447fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner    COND_NP = 11,
457fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner    COND_NS = 12,
46653456c351d9bf908ebd982f6ae9df3449c5f34bDan Gohman    COND_O  = 13,
47653456c351d9bf908ebd982f6ae9df3449c5f34bDan Gohman    COND_P  = 14,
48653456c351d9bf908ebd982f6ae9df3449c5f34bDan Gohman    COND_S  = 15,
49cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines    LAST_VALID_COND = COND_S,
50279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman
51279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman    // Artificial condition codes. These are used by AnalyzeBranch
52279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman    // to indicate a block terminated with two conditional branches to
53279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman    // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
54279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman    // which can't be represented on x86 with a single condition. These
55279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman    // are never used in MachineInstrs.
56279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman    COND_NE_OR_P,
57279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman    COND_NP_OR_E,
58279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman
597fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner    COND_INVALID
607fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner  };
618d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick
627fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner  // Turn condition code into conditional branch opcode.
637fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner  unsigned GetCondBranchFromCond(CondCode CC);
648d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick
65cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines  /// \brief Return a set opcode for the given condition and whether it has
66cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines  /// a memory operand.
67cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines  unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false);
68cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines
69cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines  /// \brief Return a cmov opcode for the given condition, register size in
70cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines  /// bytes, and operand type.
71cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines  unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
72cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines                           bool HasMemoryOperand = false);
73cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines
74b118a073d7434727a4ea5a5762f54e54e72bef4fMichael Liao  // Turn CMov opcode into condition code.
75b118a073d7434727a4ea5a5762f54e54e72bef4fMichael Liao  CondCode getCondFromCMovOpc(unsigned Opc);
76b118a073d7434727a4ea5a5762f54e54e72bef4fMichael Liao
779cd68759178f9fe25c72253d338e78e414f1d770Chris Lattner  /// GetOppositeBranchCondition - Return the inverse of the specified cond,
789cd68759178f9fe25c72253d338e78e414f1d770Chris Lattner  /// e.g. turning COND_E to COND_NE.
79cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines  CondCode GetOppositeBranchCondition(CondCode CC);
808c3fee59038d8fd98db2a01b6a309a8941a16a3fEvan Cheng}  // end namespace X86;
819cd68759178f9fe25c72253d338e78e414f1d770Chris Lattner
82281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner
833b6b36d6f54e780a2947cb1b9efe4eed7c40dc11Chris Lattner/// isGlobalStubReference - Return true if the specified TargetFlag operand is
84281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner/// a reference to a stub for a global, not the global itself.
853b6b36d6f54e780a2947cb1b9efe4eed7c40dc11Chris Lattnerinline static bool isGlobalStubReference(unsigned char TargetFlag) {
863b6b36d6f54e780a2947cb1b9efe4eed7c40dc11Chris Lattner  switch (TargetFlag) {
87281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner  case X86II::MO_DLLIMPORT: // dllimport stub.
88281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner  case X86II::MO_GOTPCREL:  // rip-relative GOT reference.
89281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner  case X86II::MO_GOT:       // normal GOT reference.
90281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner  case X86II::MO_DARWIN_NONLAZY_PIC_BASE:        // Normal $non_lazy_ptr ref.
91281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner  case X86II::MO_DARWIN_NONLAZY:                 // Normal $non_lazy_ptr ref.
92281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner  case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
93281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner    return true;
94281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner  default:
95281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner    return false;
96281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner  }
97281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner}
987478ab8502a52815413d8b388898f719484ab1a9Chris Lattner
997478ab8502a52815413d8b388898f719484ab1a9Chris Lattner/// isGlobalRelativeToPICBase - Return true if the specified global value
1007478ab8502a52815413d8b388898f719484ab1a9Chris Lattner/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg).  If this
1017478ab8502a52815413d8b388898f719484ab1a9Chris Lattner/// is true, the addressing mode has the PIC base register added in (e.g. EBX).
1027478ab8502a52815413d8b388898f719484ab1a9Chris Lattnerinline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
1037478ab8502a52815413d8b388898f719484ab1a9Chris Lattner  switch (TargetFlag) {
1047478ab8502a52815413d8b388898f719484ab1a9Chris Lattner  case X86II::MO_GOTOFF:                         // isPICStyleGOT: local global.
1057478ab8502a52815413d8b388898f719484ab1a9Chris Lattner  case X86II::MO_GOT:                            // isPICStyleGOT: other global.
1067478ab8502a52815413d8b388898f719484ab1a9Chris Lattner  case X86II::MO_PIC_BASE_OFFSET:                // Darwin local global.
1077478ab8502a52815413d8b388898f719484ab1a9Chris Lattner  case X86II::MO_DARWIN_NONLAZY_PIC_BASE:        // Darwin/32 external global.
1087478ab8502a52815413d8b388898f719484ab1a9Chris Lattner  case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
10930ef0e5658b0b8b04437f73f74162d5d72923f29Eric Christopher  case X86II::MO_TLVP:                           // ??? Pretty sure..
1107478ab8502a52815413d8b388898f719484ab1a9Chris Lattner    return true;
1117478ab8502a52815413d8b388898f719484ab1a9Chris Lattner  default:
1127478ab8502a52815413d8b388898f719484ab1a9Chris Lattner    return false;
1137478ab8502a52815413d8b388898f719484ab1a9Chris Lattner  }
1147478ab8502a52815413d8b388898f719484ab1a9Chris Lattner}
1158d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick
1161c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikovinline static bool isScale(const MachineOperand &MO) {
117d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman  return MO.isImm() &&
1181c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikov    (MO.getImm() == 1 || MO.getImm() == 2 ||
1191c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikov     MO.getImm() == 4 || MO.getImm() == 8);
1201c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikov}
1211c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikov
122094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindolainline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
123d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman  if (MI->getOperand(Op).isFI()) return true;
12436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  return Op+X86::AddrSegmentReg <= MI->getNumOperands() &&
12536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines    MI->getOperand(Op+X86::AddrBaseReg).isReg() &&
12636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines    isScale(MI->getOperand(Op+X86::AddrScaleAmt)) &&
12736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines    MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
12836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines    (MI->getOperand(Op+X86::AddrDisp).isImm() ||
12936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines     MI->getOperand(Op+X86::AddrDisp).isGlobal() ||
13036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines     MI->getOperand(Op+X86::AddrDisp).isCPI() ||
13136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines     MI->getOperand(Op+X86::AddrDisp).isJTI());
1321c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikov}
1331c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikov
134094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindolainline static bool isMem(const MachineInstr *MI, unsigned Op) {
135094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindola  if (MI->getOperand(Op).isFI()) return true;
13636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  return Op+X86::AddrNumOperands <= MI->getNumOperands() &&
13736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines    MI->getOperand(Op+X86::AddrSegmentReg).isReg() &&
138094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindola    isLeaMem(MI, Op);
139094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindola}
140094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindola
14136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hinesclass X86InstrInfo final : public X86GenInstrInfo {
142cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines  X86Subtarget &Subtarget;
143726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner  const X86RegisterInfo RI;
1448d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick
145241c15ffaa9fbe820d3aa55f17e0b569235691f3Craig Topper  /// RegOp2MemOpTable3Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
146241c15ffaa9fbe820d3aa55f17e0b569235691f3Craig Topper  /// RegOp2MemOpTable2, RegOp2MemOpTable3 - Load / store folding opcode maps.
14743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson  ///
148cbf479df8abe5e208f1438092a9632a145551cbcBruno Cardoso Lopes  typedef DenseMap<unsigned,
149cbf479df8abe5e208f1438092a9632a145551cbcBruno Cardoso Lopes                   std::pair<unsigned, unsigned> > RegOp2MemOpTableType;
150cbf479df8abe5e208f1438092a9632a145551cbcBruno Cardoso Lopes  RegOp2MemOpTableType RegOp2MemOpTable2Addr;
151cbf479df8abe5e208f1438092a9632a145551cbcBruno Cardoso Lopes  RegOp2MemOpTableType RegOp2MemOpTable0;
152cbf479df8abe5e208f1438092a9632a145551cbcBruno Cardoso Lopes  RegOp2MemOpTableType RegOp2MemOpTable1;
153cbf479df8abe5e208f1438092a9632a145551cbcBruno Cardoso Lopes  RegOp2MemOpTableType RegOp2MemOpTable2;
154177cf1e1a3685209ab805f82897902a8d2b61661Elena Demikhovsky  RegOp2MemOpTableType RegOp2MemOpTable3;
1558d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick
15643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson  /// MemOp2RegOpTable - Load / store unfolding opcode map.
15743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson  ///
158cbf479df8abe5e208f1438092a9632a145551cbcBruno Cardoso Lopes  typedef DenseMap<unsigned,
159cbf479df8abe5e208f1438092a9632a145551cbcBruno Cardoso Lopes                   std::pair<unsigned, unsigned> > MemOp2RegOpTableType;
160cbf479df8abe5e208f1438092a9632a145551cbcBruno Cardoso Lopes  MemOp2RegOpTableType MemOp2RegOpTable;
161cbf479df8abe5e208f1438092a9632a145551cbcBruno Cardoso Lopes
162f318457547ade1ca210386fb69da97f070423998Craig Topper  static void AddTableEntry(RegOp2MemOpTableType &R2MTable,
163f318457547ade1ca210386fb69da97f070423998Craig Topper                            MemOp2RegOpTableType &M2RTable,
164f318457547ade1ca210386fb69da97f070423998Craig Topper                            unsigned RegOp, unsigned MemOp, unsigned Flags);
165352aa503faee6c58e9cdb5054cc5ec1d90c696b4Jakob Stoklund Olesen
166354362524a72b3fa43a6c09380b7ae3b2380cbbaJuergen Ributzka  virtual void anchor();
167354362524a72b3fa43a6c09380b7ae3b2380cbbaJuergen Ributzka
168726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattnerpublic:
169cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines  explicit X86InstrInfo(X86Subtarget &STI);
170726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner
1713501feab811c86c9659248a4875fc31a3165f84dChris Lattner  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
172726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner  /// such, whenever a client has an instance of instruction info, it should
173726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner  /// always be able to get register info as well (through this method).
174726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner  ///
17536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  const X86RegisterInfo &getRegisterInfo() const { return RI; }
176726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner
1777da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng  /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
1787da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng  /// extension instruction. That is, it's like a copy where it's legal for the
1797da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng  /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
1807da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng  /// true, then it's expected the pre-extension value is available as a subreg
1817da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng  /// of the result register. This also returns the sub-register index in
1827da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng  /// SubIdx.
18336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  bool isCoalescableExtInstr(const MachineInstr &MI,
18436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                             unsigned &SrcReg, unsigned &DstReg,
18536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                             unsigned &SubIdx) const override;
186a5a81d70720a4ce6ac7538927c2a874b0dfa8bd2Evan Cheng
18736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  unsigned isLoadFromStackSlot(const MachineInstr *MI,
18836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                               int &FrameIndex) const override;
189dda3978d7877d2d60390833c73ed24857295e89cDavid Greene  /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
190dda3978d7877d2d60390833c73ed24857295e89cDavid Greene  /// stack locations as well.  This uses a heuristic so it isn't
191dda3978d7877d2d60390833c73ed24857295e89cDavid Greene  /// reliable for correctness.
192dda3978d7877d2d60390833c73ed24857295e89cDavid Greene  unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
19336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                                     int &FrameIndex) const override;
194b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene
19536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  unsigned isStoreToStackSlot(const MachineInstr *MI,
19636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                              int &FrameIndex) const override;
197dda3978d7877d2d60390833c73ed24857295e89cDavid Greene  /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
198dda3978d7877d2d60390833c73ed24857295e89cDavid Greene  /// stack locations as well.  This uses a heuristic so it isn't
199dda3978d7877d2d60390833c73ed24857295e89cDavid Greene  /// reliable for correctness.
200dda3978d7877d2d60390833c73ed24857295e89cDavid Greene  unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
20136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                                    int &FrameIndex) const override;
202ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng
2033731bc026cc6c4fb7deb7ac67e2c3be0c22498beDan Gohman  bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
20436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                                         AliasAnalysis *AA) const override;
205ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng  void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
206378445303b10b092a898a75131141a8259cff50bEvan Cheng                     unsigned DestReg, unsigned SubIdx,
207d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng                     const MachineInstr *Orig,
20836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                     const TargetRegisterInfo &TRI) const override;
209ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng
210e5609f37323b105c7720d5d423a9203d1e869c29Tim Northover  /// Given an operand within a MachineInstr, insert preceding code to put it
211e5609f37323b105c7720d5d423a9203d1e869c29Tim Northover  /// into the right format for a particular kind of LEA instruction. This may
212e5609f37323b105c7720d5d423a9203d1e869c29Tim Northover  /// involve using an appropriate super-register instead (with an implicit use
213e5609f37323b105c7720d5d423a9203d1e869c29Tim Northover  /// of the original) or creating a new virtual register and inserting COPY
214e5609f37323b105c7720d5d423a9203d1e869c29Tim Northover  /// instructions to get the data into the right class.
215e5609f37323b105c7720d5d423a9203d1e869c29Tim Northover  ///
216e5609f37323b105c7720d5d423a9203d1e869c29Tim Northover  /// Reference parameters are set to indicate how caller should add this
217e5609f37323b105c7720d5d423a9203d1e869c29Tim Northover  /// operand to the LEA instruction.
218e5609f37323b105c7720d5d423a9203d1e869c29Tim Northover  bool classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
219e5609f37323b105c7720d5d423a9203d1e869c29Tim Northover                      unsigned LEAOpcode, bool AllowSP,
220e5609f37323b105c7720d5d423a9203d1e869c29Tim Northover                      unsigned &NewSrc, bool &isKill,
221e5609f37323b105c7720d5d423a9203d1e869c29Tim Northover                      bool &isUndef, MachineOperand &ImplicitOp) const;
222e5609f37323b105c7720d5d423a9203d1e869c29Tim Northover
223bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner  /// convertToThreeAddress - This method must be implemented by targets that
224bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner  /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
225bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner  /// may be able to convert a two-address instruction into a true
226bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner  /// three-address instruction on demand.  This allows the X86 target (for
227bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner  /// example) to convert ADD and SHL instructions into LEA instructions if they
228bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner  /// would require register copies due to two-addressness.
229bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner  ///
230bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner  /// This method returns a null pointer if the transformation cannot be
231bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner  /// performed, otherwise it returns the new instruction.
232bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner  ///
23336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
23436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                                      MachineBasicBlock::iterator &MBBI,
23536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                                      LiveVariables *LV) const override;
236bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner
23741e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner  /// commuteInstruction - We have a few instructions that must be hacked on to
23841e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner  /// commute them.
23941e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner  ///
24036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const override;
24136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines
24236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
24336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                             unsigned &SrcOpIdx2) const override;
24441e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner
2457fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner  // Branch analysis.
24636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  bool isUnpredicatedTerminator(const MachineInstr* MI) const override;
24736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
24836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                     MachineBasicBlock *&FBB,
24936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                     SmallVectorImpl<MachineOperand> &Cond,
25036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                     bool AllowModify) const override;
25136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
25236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
25336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                        MachineBasicBlock *FBB,
25436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                        const SmallVectorImpl<MachineOperand> &Cond,
25536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                        DebugLoc DL) const override;
25636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  bool canInsertSelect(const MachineBasicBlock&,
25736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                       const SmallVectorImpl<MachineOperand> &Cond,
25836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                       unsigned, unsigned, int&, int&, int&) const override;
25936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  void insertSelect(MachineBasicBlock &MBB,
26036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                    MachineBasicBlock::iterator MI, DebugLoc DL,
26136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                    unsigned DstReg,
26236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                    const SmallVectorImpl<MachineOperand> &Cond,
26336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                    unsigned TrueReg, unsigned FalseReg) const override;
26436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  void copyPhysReg(MachineBasicBlock &MBB,
26536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                   MachineBasicBlock::iterator MI, DebugLoc DL,
26636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                   unsigned DestReg, unsigned SrcReg,
26736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                   bool KillSrc) const override;
26836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  void storeRegToStackSlot(MachineBasicBlock &MBB,
26936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                           MachineBasicBlock::iterator MI,
27036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                           unsigned SrcReg, bool isKill, int FrameIndex,
27136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                           const TargetRegisterClass *RC,
27236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                           const TargetRegisterInfo *TRI) const override;
27336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines
27436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
27536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                      SmallVectorImpl<MachineOperand> &Addr,
27636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                      const TargetRegisterClass *RC,
27736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                      MachineInstr::mmo_iterator MMOBegin,
27836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                      MachineInstr::mmo_iterator MMOEnd,
27936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                      SmallVectorImpl<MachineInstr*> &NewMIs) const;
28036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines
28136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  void loadRegFromStackSlot(MachineBasicBlock &MBB,
28236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                            MachineBasicBlock::iterator MI,
28336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                            unsigned DestReg, int FrameIndex,
28436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                            const TargetRegisterClass *RC,
28536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                            const TargetRegisterInfo *TRI) const override;
28636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines
28736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
28836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                       SmallVectorImpl<MachineOperand> &Addr,
28936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                       const TargetRegisterClass *RC,
29036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                       MachineInstr::mmo_iterator MMOBegin,
29136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                       MachineInstr::mmo_iterator MMOEnd,
29236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                       SmallVectorImpl<MachineInstr*> &NewMIs) const;
29336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines
29436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
29592fb79b7a611ab4c1043f04e8acd08f963d073adJakob Stoklund Olesen
29643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson  /// foldMemoryOperand - If this target supports it, fold a load or store of
29743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson  /// the specified stack slot into the specified machine instruction for the
29843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson  /// specified operand(s).  If this is possible, the target should perform the
29943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson  /// folding and return true, otherwise it should return false.  If it folds
30043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson  /// the instruction, it is likely that the MachineInstruction the iterator
30143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson  /// references has been changed.
30236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
30336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                                      MachineInstr* MI,
30436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                                      const SmallVectorImpl<unsigned> &Ops,
30536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                                      int FrameIndex) const override;
30643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson
30743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson  /// foldMemoryOperand - Same as the previous version except it allows folding
30843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson  /// of any load and store from / to any address, not just from a specific
30943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson  /// stack slot.
31036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
31136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                                      MachineInstr* MI,
31236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                                      const SmallVectorImpl<unsigned> &Ops,
31336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                                      MachineInstr* LoadMI) const override;
31443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson
31543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson  /// canFoldMemoryOperand - Returns true if the specified load / store is
31643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson  /// folding is possible.
31736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  bool canFoldMemoryOperand(const MachineInstr*,
31836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                            const SmallVectorImpl<unsigned> &) const override;
31943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson
32043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson  /// unfoldMemoryOperand - Separate a single instruction which folded a load or
32143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson  /// a store or a load and a store into two or more instruction. If this is
32243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson  /// possible, returns true as well as the new instructions by reference.
32336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
32436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                         unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
32536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                         SmallVectorImpl<MachineInstr*> &NewMIs) const override;
32643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson
32736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
32836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                           SmallVectorImpl<SDNode*> &NewNodes) const override;
32943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson
33043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson  /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
33143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson  /// instruction after load / store are unfolded from an instruction of the
33243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson  /// specified opcode. It returns zero if the specified unfolding is not
3330115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman  /// possible. If LoadRegIndex is non-null, it is filled in with the operand
3340115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman  /// index of the operand which will hold the register holding the loaded
3350115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman  /// value.
33636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
33736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                              bool UnfoldLoad, bool UnfoldStore,
338dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines                              unsigned *LoadRegIndex = nullptr) const override;
3398d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick
34096dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
34196dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng  /// to determine if two loads are loading from the same base address. It
34296dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng  /// should only return true if the base pointers are the same and the
34396dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng  /// only differences between the two addresses are the offset. It also returns
34496dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng  /// the offsets by reference.
34536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
34636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                               int64_t &Offset2) const override;
34796dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng
34896dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
3497a2bdde0a0eebcd2125055e0eacaca040f0b766cChris Lattner  /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
35096dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng  /// be scheduled togther. On some targets if two loads are loading from
35196dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng  /// addresses in the same cache line, it's better if they are scheduled
35296dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng  /// together. This function takes two integers that represent the load offsets
35396dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng  /// from the common base address. It returns true if it decides it's desirable
35496dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng  /// to schedule the two loads together. "NumLoads" is the number of loads that
35596dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng  /// have already been scheduled after Load1.
35636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
35736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                               int64_t Offset1, int64_t Offset2,
35836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                               unsigned NumLoads) const override;
35996dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng
36036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  bool shouldScheduleAdjacent(MachineInstr* First,
36136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                              MachineInstr *Second) const override;
3620f2eec65fb9e9e1dee3f672d38d03d047936a62aAndrew Trick
36336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  void getNoopForMachoTarget(MCInst &NopInst) const override;
364ee9eb411fffddbb8fe70418c05946a131889b487Chris Lattner
36536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  bool
36636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
36741e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner
3684350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng  /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
3694350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng  /// instruction that defines the specified register class.
37036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
37123066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng
372dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines  /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha
373dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines  /// would clobber the EFLAGS condition register. Note the result may be
374dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines  /// conservative. If it cannot definitely determine the safety after visiting
375dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines  /// a few instructions in each direction it assumes it's not safe.
376dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines  bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
377dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines                             MachineBasicBlock::iterator I) const;
378dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines
37939a612e6f9e63806af410a0ab0d81895391e4c79Chris Lattner  static bool isX86_64ExtendedReg(const MachineOperand &MO) {
38039a612e6f9e63806af410a0ab0d81895391e4c79Chris Lattner    if (!MO.isReg()) return false;
3818c3fee59038d8fd98db2a01b6a309a8941a16a3fEvan Cheng    return X86II::isX86_64ExtendedReg(MO.getReg());
38239a612e6f9e63806af410a0ab0d81895391e4c79Chris Lattner  }
38352e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray
38457c3dac0df7ac1b53ae7c0e5d2adc459fc7bd37cDan Gohman  /// getGlobalBaseReg - Return a virtual register initialized with the
38557c3dac0df7ac1b53ae7c0e5d2adc459fc7bd37cDan Gohman  /// the global base register value. Output instructions required to
38657c3dac0df7ac1b53ae7c0e5d2adc459fc7bd37cDan Gohman  /// initialize the register in the function entry block, if necessary.
3878b746969baee26237e4c52de9862d06795eabcdaDan Gohman  ///
38857c3dac0df7ac1b53ae7c0e5d2adc459fc7bd37cDan Gohman  unsigned getGlobalBaseReg(MachineFunction *MF) const;
3898b746969baee26237e4c52de9862d06795eabcdaDan Gohman
39098e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen  std::pair<uint16_t, uint16_t>
39136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  getExecutionDomain(const MachineInstr *MI) const override;
392e4b94b4efb9a4670f25a5a80dd3b97f9583de202Jakob Stoklund Olesen
39336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override;
394352aa503faee6c58e9cdb5054cc5ec1d90c696b4Jakob Stoklund Olesen
39536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  unsigned
39636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines    getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
39736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                                 const TargetRegisterInfo *TRI) const override;
398a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99Andrew Trick  unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
39936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                                const TargetRegisterInfo *TRI) const override;
400c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen  void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
40136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                                 const TargetRegisterInfo *TRI) const override;
402c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen
403beac75da3784929aee9f0357fc5cd76d49d6c3d7Chris Lattner  MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
404beac75da3784929aee9f0357fc5cd76d49d6c3d7Chris Lattner                                      MachineInstr* MI,
405beac75da3784929aee9f0357fc5cd76d49d6c3d7Chris Lattner                                      unsigned OpNum,
406beac75da3784929aee9f0357fc5cd76d49d6c3d7Chris Lattner                                      const SmallVectorImpl<MachineOperand> &MOs,
407beac75da3784929aee9f0357fc5cd76d49d6c3d7Chris Lattner                                      unsigned Size, unsigned Alignment) const;
4082312842de0c641107dd04d7e056d02491cc781caEvan Cheng
409cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines  void
410cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines  getUnconditionalBranch(MCInst &Branch,
411cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines                         const MCSymbolRefExpr *BranchTarget) const override;
412cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines
413cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines  void getTrap(MCInst &MI) const override;
414cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines
41536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  bool isHighLatencyDef(int opc) const override;
416e0ef509aeb47b396cf1bdc170ca4f468f799719fAndrew Trick
4172312842de0c641107dd04d7e056d02491cc781caEvan Cheng  bool hasHighOperandLatency(const InstrItineraryData *ItinData,
4182312842de0c641107dd04d7e056d02491cc781caEvan Cheng                             const MachineRegisterInfo *MRI,
4192312842de0c641107dd04d7e056d02491cc781caEvan Cheng                             const MachineInstr *DefMI, unsigned DefIdx,
42036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                             const MachineInstr *UseMI,
42136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                             unsigned UseIdx) const override;
4228d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick
4232af66dc51a7a0f3490c7e89c636e4015431195cdManman Ren  /// analyzeCompare - For a comparison instruction, return the source registers
4242af66dc51a7a0f3490c7e89c636e4015431195cdManman Ren  /// in SrcReg and SrcReg2 if having two register operands, and the value it
4252af66dc51a7a0f3490c7e89c636e4015431195cdManman Ren  /// compares against in CmpValue. Return true if the comparison instruction
4262af66dc51a7a0f3490c7e89c636e4015431195cdManman Ren  /// can be analyzed.
42736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
42836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                      unsigned &SrcReg2, int &CmpMask,
42936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                      int &CmpValue) const override;
4302af66dc51a7a0f3490c7e89c636e4015431195cdManman Ren
4312af66dc51a7a0f3490c7e89c636e4015431195cdManman Ren  /// optimizeCompareInstr - Check if there exists an earlier instruction that
4322af66dc51a7a0f3490c7e89c636e4015431195cdManman Ren  /// operates on the same source operands and sets flags in the same way as
4332af66dc51a7a0f3490c7e89c636e4015431195cdManman Ren  /// Compare; remove Compare if possible.
43436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
43536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                            unsigned SrcReg2, int CmpMask, int CmpValue,
43636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                            const MachineRegisterInfo *MRI) const override;
4372af66dc51a7a0f3490c7e89c636e4015431195cdManman Ren
438d7d003c2b7b7f657eed364e4ac06f4ab32fc8c2dManman Ren  /// optimizeLoadInstr - Try to remove the load by folding it to a register
439d7d003c2b7b7f657eed364e4ac06f4ab32fc8c2dManman Ren  /// operand at the use. We fold the load instructions if and only if the
440127eea87d666ccc9fe7025f41148c33af0f8c84bManman Ren  /// def and use are in the same BB. We only look at one load and see
441127eea87d666ccc9fe7025f41148c33af0f8c84bManman Ren  /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
442127eea87d666ccc9fe7025f41148c33af0f8c84bManman Ren  /// defined by the load we are trying to fold. DefMI returns the machine
443127eea87d666ccc9fe7025f41148c33af0f8c84bManman Ren  /// instruction that defines FoldAsLoadDefReg, and the function returns
444127eea87d666ccc9fe7025f41148c33af0f8c84bManman Ren  /// the machine instruction generated due to folding.
44536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines  MachineInstr* optimizeLoadInstr(MachineInstr *MI,
44636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                                  const MachineRegisterInfo *MRI,
44736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                                  unsigned &FoldAsLoadDefReg,
44836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines                                  MachineInstr *&DefMI) const override;
449d7d003c2b7b7f657eed364e4ac06f4ab32fc8c2dManman Ren
45043dbe05279b753aabda571d9c83eaeb36987001aOwen Andersonprivate:
451656e51454ac70f5d500565fd33c883f6dea549f2Evan Cheng  MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
452656e51454ac70f5d500565fd33c883f6dea549f2Evan Cheng                                              MachineFunction::iterator &MFI,
453656e51454ac70f5d500565fd33c883f6dea549f2Evan Cheng                                              MachineBasicBlock::iterator &MBBI,
454656e51454ac70f5d500565fd33c883f6dea549f2Evan Cheng                                              LiveVariables *LV) const;
455656e51454ac70f5d500565fd33c883f6dea549f2Evan Cheng
456b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene  /// isFrameOperand - Return true and the FrameIndex if the specified
457b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene  /// operand and follow operands form a reference to the stack frame.
458b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene  bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
459b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene                      int &FrameIndex) const;
460726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner};
461726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner
462d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace
463d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke
464726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#endif
465