X86InstrInfo.h revision 4ee451de366474b9c228b4e5fa573795a715216d
11e60a9165dc4d6ce5650dacc026f2942696af920Chris Lattner//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 20e0a7a45d3d0a8c865a078459d2e1c6d8967a100Misha Brukman// 3856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell// The LLVM Compiler Infrastructure 4856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 70e0a7a45d3d0a8c865a078459d2e1c6d8967a100Misha Brukman// 8856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell//===----------------------------------------------------------------------===// 9726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner// 103501feab811c86c9659248a4875fc31a3165f84dChris Lattner// This file contains the X86 implementation of the TargetInstrInfo class. 11726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner// 12726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner//===----------------------------------------------------------------------===// 13726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 14726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#ifndef X86INSTRUCTIONINFO_H 15726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#define X86INSTRUCTIONINFO_H 16726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 173501feab811c86c9659248a4875fc31a3165f84dChris Lattner#include "llvm/Target/TargetInstrInfo.h" 18726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#include "X86RegisterInfo.h" 19726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 20d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 2125ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng class X86RegisterInfo; 22aa3c1410b427909da350f2b5e8d4ec3db62a3618Evan Cheng class X86TargetMachine; 23d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 247fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattnernamespace X86 { 257fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner // X86 specific condition code. These correspond to X86_*_COND in 267fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner // X86InstrInfo.td. They must be kept in synch. 277fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner enum CondCode { 287fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_A = 0, 297fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_AE = 1, 307fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_B = 2, 317fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_BE = 3, 327fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_E = 4, 337fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_G = 5, 347fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_GE = 6, 357fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_L = 7, 367fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_LE = 8, 377fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_NE = 9, 387fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_NO = 10, 397fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_NP = 11, 407fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_NS = 12, 417fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_O = 13, 427fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_P = 14, 437fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_S = 15, 447fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_INVALID 457fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner }; 467fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner 477fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner // Turn condition code into conditional branch opcode. 487fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner unsigned GetCondBranchFromCond(CondCode CC); 499cd68759178f9fe25c72253d338e78e414f1d770Chris Lattner 509cd68759178f9fe25c72253d338e78e414f1d770Chris Lattner /// GetOppositeBranchCondition - Return the inverse of the specified cond, 519cd68759178f9fe25c72253d338e78e414f1d770Chris Lattner /// e.g. turning COND_E to COND_NE. 529cd68759178f9fe25c72253d338e78e414f1d770Chris Lattner CondCode GetOppositeBranchCondition(X86::CondCode CC); 539cd68759178f9fe25c72253d338e78e414f1d770Chris Lattner 547fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner} 557fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner 569d17740295838f94120646ef619b2e187f2d71bdChris Lattner/// X86II - This namespace holds all of the target specific flags that 579d17740295838f94120646ef619b2e187f2d71bdChris Lattner/// instruction info tracks. 589d17740295838f94120646ef619b2e187f2d71bdChris Lattner/// 599d17740295838f94120646ef619b2e187f2d71bdChris Lattnernamespace X86II { 609d17740295838f94120646ef619b2e187f2d71bdChris Lattner enum { 616aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner //===------------------------------------------------------------------===// 626aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner // Instruction types. These are the standard/most common forms for X86 636aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner // instructions. 646aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner // 656aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 664c299f5da1013cd36563a82f188c731b2758074dChris Lattner // PseudoFrm - This represents an instruction that is a pseudo instruction 674c299f5da1013cd36563a82f188c731b2758074dChris Lattner // or one that has not been implemented yet. It is illegal to code generate 684c299f5da1013cd36563a82f188c731b2758074dChris Lattner // it, but tolerated for intermediate implementation stages. 694c299f5da1013cd36563a82f188c731b2758074dChris Lattner Pseudo = 0, 704c299f5da1013cd36563a82f188c731b2758074dChris Lattner 716aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// Raw - This form is for instructions that don't have any operands, so 726aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// they are just a fixed opcode value, like 'leave'. 734c299f5da1013cd36563a82f188c731b2758074dChris Lattner RawFrm = 1, 740e0a7a45d3d0a8c865a078459d2e1c6d8967a100Misha Brukman 756aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// AddRegFrm - This form is used for instructions like 'push r32' that have 766aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// their one register operand added to their opcode. 774c299f5da1013cd36563a82f188c731b2758074dChris Lattner AddRegFrm = 2, 786aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 796aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 806aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// to specify a destination, which in this case is a register. 816aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// 824c299f5da1013cd36563a82f188c731b2758074dChris Lattner MRMDestReg = 3, 836aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 846aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 856aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// to specify a destination, which in this case is memory. 866aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// 874c299f5da1013cd36563a82f188c731b2758074dChris Lattner MRMDestMem = 4, 886aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 896aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 906aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// to specify a source, which in this case is a register. 916aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// 924c299f5da1013cd36563a82f188c731b2758074dChris Lattner MRMSrcReg = 5, 936aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 946aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 956aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// to specify a source, which in this case is memory. 966aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// 974c299f5da1013cd36563a82f188c731b2758074dChris Lattner MRMSrcMem = 6, 980e0a7a45d3d0a8c865a078459d2e1c6d8967a100Misha Brukman 99169584ed45f62f91599bed3d019640e168d815eaAlkis Evlogimenos /// MRM[0-7][rm] - These forms are used to represent instructions that use 10085b39f229f3146e57d059f1c774400e4bde23987Chris Lattner /// a Mod/RM byte, and use the middle field to hold extended opcode 10185b39f229f3146e57d059f1c774400e4bde23987Chris Lattner /// information. In the intel manual these are represented as /0, /1, ... 10285b39f229f3146e57d059f1c774400e4bde23987Chris Lattner /// 10385b39f229f3146e57d059f1c774400e4bde23987Chris Lattner 10485b39f229f3146e57d059f1c774400e4bde23987Chris Lattner // First, instructions that operate on a register r/m operand... 105169584ed45f62f91599bed3d019640e168d815eaAlkis Evlogimenos MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 106169584ed45f62f91599bed3d019640e168d815eaAlkis Evlogimenos MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 10785b39f229f3146e57d059f1c774400e4bde23987Chris Lattner 10885b39f229f3146e57d059f1c774400e4bde23987Chris Lattner // Next, instructions that operate on a memory r/m operand... 109169584ed45f62f91599bed3d019640e168d815eaAlkis Evlogimenos MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 110169584ed45f62f91599bed3d019640e168d815eaAlkis Evlogimenos MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 1116aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 1123c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng // MRMInitReg - This form is used for instructions whose source and 1133c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng // destinations are the same register. 1143c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng MRMInitReg = 32, 1153c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng 1163c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng FormMask = 63, 1176aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 1186aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner //===------------------------------------------------------------------===// 1196aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner // Actual flags... 1206aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 12111e53e3c384e9e25f53a0aec3acf0a725efafeabChris Lattner // OpSize - Set if this instruction requires an operand size prefix (0x66), 12211e53e3c384e9e25f53a0aec3acf0a725efafeabChris Lattner // which most often indicates that the instruction operates on 16 bit data 12311e53e3c384e9e25f53a0aec3acf0a725efafeabChris Lattner // instead of 32 bit data. 1243c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng OpSize = 1 << 6, 1254c299f5da1013cd36563a82f188c731b2758074dChris Lattner 12625ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // AsSize - Set if this instruction requires an operand size prefix (0x67), 12725ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // which most often indicates that the instruction address 16 bit address 12825ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // instead of 32 bit address (or 32 bit address in 64 bit mode). 12925ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng AdSize = 1 << 7, 13025ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng 13125ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng //===------------------------------------------------------------------===// 1324c299f5da1013cd36563a82f188c731b2758074dChris Lattner // Op0Mask - There are several prefix bytes that are used to form two byte 133915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 134915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner // used to obtain the setting of this field. If no bits in this field is 135915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner // set, there is no prefix byte for obtaining a multibyte opcode. 1364c299f5da1013cd36563a82f188c731b2758074dChris Lattner // 13725ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng Op0Shift = 8, 1382959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner Op0Mask = 0xF << Op0Shift, 1394c299f5da1013cd36563a82f188c731b2758074dChris Lattner 1404c299f5da1013cd36563a82f188c731b2758074dChris Lattner // TB - TwoByte - Set if this instruction has a two byte opcode, which 1414c299f5da1013cd36563a82f188c731b2758074dChris Lattner // starts with a 0x0F byte before the real opcode. 1422959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner TB = 1 << Op0Shift, 1434c299f5da1013cd36563a82f188c731b2758074dChris Lattner 144915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner // REP - The 0xF3 prefix byte indicating repetition of the following 145915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner // instruction. 146915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner REP = 2 << Op0Shift, 147915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner 1484c299f5da1013cd36563a82f188c731b2758074dChris Lattner // D8-DF - These escape opcodes are used by the floating point unit. These 1494c299f5da1013cd36563a82f188c731b2758074dChris Lattner // values must remain sequential. 150915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 151915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner DA = 5 << Op0Shift, DB = 6 << Op0Shift, 152915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner DC = 7 << Op0Shift, DD = 8 << Op0Shift, 153915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner DE = 9 << Op0Shift, DF = 10 << Op0Shift, 1549eb59ec548b861d6ede05b4e6dc22aabf645e665Jeff Cohen 155f63be7d3959939b2ffaf0bba5519b71216ec9ee6Nate Begeman // XS, XD - These prefix codes are for single and double precision scalar 156f63be7d3959939b2ffaf0bba5519b71216ec9ee6Nate Begeman // floating point operations performed in the SSE registers. 157bb1ee05253d965e0944351a21e9970c02b1aebfeBill Wendling XD = 11 << Op0Shift, XS = 12 << Op0Shift, 158bb1ee05253d965e0944351a21e9970c02b1aebfeBill Wendling 159bb1ee05253d965e0944351a21e9970c02b1aebfeBill Wendling // T8, TA - Prefix after the 0x0F prefix. 160bb1ee05253d965e0944351a21e9970c02b1aebfeBill Wendling T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 1614c299f5da1013cd36563a82f188c731b2758074dChris Lattner 1620c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner //===------------------------------------------------------------------===// 16325ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 16425ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // They are used to specify GPRs and SSE registers, 64-bit operand size, 16525ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // etc. We only cares about REX.W and REX.R bits and only the former is 16625ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // statically determined. 16725ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // 16825ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng REXShift = 12, 16925ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng REX_W = 1 << REXShift, 17025ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng 17125ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng //===------------------------------------------------------------------===// 17225ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // This three-bit field describes the size of an immediate operand. Zero is 1735ab29b504d49d3fa84d76f79e73704260f900682Alkis Evlogimenos // unused so that we can tell if we forgot to set a value. 17425ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng ImmShift = 13, 17525ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng ImmMask = 7 << ImmShift, 1765ab29b504d49d3fa84d76f79e73704260f900682Alkis Evlogimenos Imm8 = 1 << ImmShift, 1775ab29b504d49d3fa84d76f79e73704260f900682Alkis Evlogimenos Imm16 = 2 << ImmShift, 1785ab29b504d49d3fa84d76f79e73704260f900682Alkis Evlogimenos Imm32 = 3 << ImmShift, 17925ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng Imm64 = 4 << ImmShift, 1804c299f5da1013cd36563a82f188c731b2758074dChris Lattner 1810c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner //===------------------------------------------------------------------===// 1820c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // FP Instruction Classification... Zero is non-fp instruction. 1830c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 1842959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner // FPTypeMask - Mask for all of the FP types... 18525ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng FPTypeShift = 16, 1862959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner FPTypeMask = 7 << FPTypeShift, 1872959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner 18879b13735adcc034a6869f1fd5670051c6dd0a28aChris Lattner // NotFP - The default, set for instructions that do not use FP registers. 18979b13735adcc034a6869f1fd5670051c6dd0a28aChris Lattner NotFP = 0 << FPTypeShift, 19079b13735adcc034a6869f1fd5670051c6dd0a28aChris Lattner 1910c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 1922959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner ZeroArgFP = 1 << FPTypeShift, 1930c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 1940c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 1952959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner OneArgFP = 2 << FPTypeShift, 1960c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 1970c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 1980c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // result back to ST(0). For example, fcos, fsqrt, etc. 1990c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // 2002959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner OneArgFPRW = 3 << FPTypeShift, 2010c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 2020c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 2030c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // explicit argument, storing the result to either ST(0) or the implicit 2040c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // argument. For example: fadd, fsub, fmul, etc... 2052959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner TwoArgFP = 4 << FPTypeShift, 2060c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 207ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 208ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner // explicit argument, but have no destination. Example: fucom, fucomi, ... 209ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner CompareFP = 5 << FPTypeShift, 210ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner 2111c54a8544788156d6864430182a3a79b8839b7daChris Lattner // CondMovFP - "2 operand" floating point conditional move instructions. 212ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner CondMovFP = 6 << FPTypeShift, 2131c54a8544788156d6864430182a3a79b8839b7daChris Lattner 2140c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 215ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner SpecialFP = 7 << FPTypeShift, 2161c54a8544788156d6864430182a3a79b8839b7daChris Lattner 21725ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // Bits 19 -> 23 are unused 21825ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng OpcodeShift = 24, 219d74ea2bbd8bb630331f35ead42d385249bd42af8Chris Lattner OpcodeMask = 0xFF << OpcodeShift 2209d17740295838f94120646ef619b2e187f2d71bdChris Lattner }; 2219d17740295838f94120646ef619b2e187f2d71bdChris Lattner} 2229d17740295838f94120646ef619b2e187f2d71bdChris Lattner 2233501feab811c86c9659248a4875fc31a3165f84dChris Lattnerclass X86InstrInfo : public TargetInstrInfo { 224aa3c1410b427909da350f2b5e8d4ec3db62a3618Evan Cheng X86TargetMachine &TM; 225726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner const X86RegisterInfo RI; 226726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattnerpublic: 227aa3c1410b427909da350f2b5e8d4ec3db62a3618Evan Cheng X86InstrInfo(X86TargetMachine &tm); 228726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 2293501feab811c86c9659248a4875fc31a3165f84dChris Lattner /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 230726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner /// such, whenever a client has an instance of instruction info, it should 231726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner /// always be able to get register info as well (through this method). 232726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner /// 233726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner virtual const MRegisterInfo &getRegisterInfo() const { return RI; } 234726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 2355e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos // Return true if the instruction is a register to register move and 2365e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos // leave the source and dest operands in the passed parameters. 2375e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos // 238408396014742a05cad1c91949d2226169e3f9d80Chris Lattner bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, 239408396014742a05cad1c91949d2226169e3f9d80Chris Lattner unsigned& destReg) const; 240408396014742a05cad1c91949d2226169e3f9d80Chris Lattner unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; 241408396014742a05cad1c91949d2226169e3f9d80Chris Lattner unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; 242041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling bool isReallyTriviallyReMaterializable(MachineInstr *MI) const; 243627c00b663f881600b4af1ae135af6ee2cb19c1aBill Wendling bool isReallySideEffectFree(MachineInstr *MI) const; 244627c00b663f881600b4af1ae135af6ee2cb19c1aBill Wendling 245bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// convertToThreeAddress - This method must be implemented by targets that 246bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 247bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// may be able to convert a two-address instruction into a true 248bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// three-address instruction on demand. This allows the X86 target (for 249bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// example) to convert ADD and SHL instructions into LEA instructions if they 250bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// would require register copies due to two-addressness. 251bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// 252bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// This method returns a null pointer if the transformation cannot be 253bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// performed, otherwise it returns the new instruction. 254bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// 255ba59a1e453e110f7b84233f07613f9c5d9a39b87Evan Cheng virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 256ba59a1e453e110f7b84233f07613f9c5d9a39b87Evan Cheng MachineBasicBlock::iterator &MBBI, 257ba59a1e453e110f7b84233f07613f9c5d9a39b87Evan Cheng LiveVariables &LV) const; 258bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner 25941e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner /// commuteInstruction - We have a few instructions that must be hacked on to 26041e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner /// commute them. 26141e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner /// 26241e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 26341e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner 2647fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner // Branch analysis. 265318093b6f8d21ac8eab34573b0526984895fe941Dale Johannesen virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 2667fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 2677fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner MachineBasicBlock *&FBB, 2687fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner std::vector<MachineOperand> &Cond) const; 2696ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Cheng virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 2706ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Cheng virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 2716ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Cheng MachineBasicBlock *FBB, 2726ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Cheng const std::vector<MachineOperand> &Cond) const; 273c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; 2747fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const; 27541e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner 27625ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng const TargetRegisterClass *getPointerRegClass() const; 27725ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng 278f21dfcddcf199444440004bfa74bb222e2d3ce9eChris Lattner // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 279ee465749313579ccd91575ca8acf70b75c221a2cDuncan Sands // specified machine instruction. 280f21dfcddcf199444440004bfa74bb222e2d3ce9eChris Lattner // 28119f2ffce4598c4c70f32eed7c6740b43185200b1Evan Cheng unsigned char getBaseOpcodeFor(const TargetInstrDescriptor *TID) const { 28219f2ffce4598c4c70f32eed7c6740b43185200b1Evan Cheng return TID->TSFlags >> X86II::OpcodeShift; 2834d18d5ce1e62779e7736ca0811e2e1cb06e4ea36Chris Lattner } 284ee465749313579ccd91575ca8acf70b75c221a2cDuncan Sands unsigned char getBaseOpcodeFor(MachineOpCode Opcode) const { 285ee465749313579ccd91575ca8acf70b75c221a2cDuncan Sands return getBaseOpcodeFor(&get(Opcode)); 286ee465749313579ccd91575ca8acf70b75c221a2cDuncan Sands } 287726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner}; 288726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 289d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 290d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 291726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#endif 292