X86InstrInfo.h revision 79b13735adcc034a6869f1fd5670051c6dd0a28a
11e60a9165dc4d6ce5650dacc026f2942696af920Chris Lattner//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell// 3856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell// The LLVM Compiler Infrastructure 4856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell// 5856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell// This file was developed by the LLVM research group and is distributed under 6856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell// the University of Illinois Open Source License. See LICENSE.TXT for details. 7856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell// 8856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell//===----------------------------------------------------------------------===// 9726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner// 103501feab811c86c9659248a4875fc31a3165f84dChris Lattner// This file contains the X86 implementation of the TargetInstrInfo class. 11726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner// 12726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner//===----------------------------------------------------------------------===// 13726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 14726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#ifndef X86INSTRUCTIONINFO_H 15726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#define X86INSTRUCTIONINFO_H 16726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 173501feab811c86c9659248a4875fc31a3165f84dChris Lattner#include "llvm/Target/TargetInstrInfo.h" 18726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#include "X86RegisterInfo.h" 19726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 20d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 21d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 229d17740295838f94120646ef619b2e187f2d71bdChris Lattner/// X86II - This namespace holds all of the target specific flags that 239d17740295838f94120646ef619b2e187f2d71bdChris Lattner/// instruction info tracks. 249d17740295838f94120646ef619b2e187f2d71bdChris Lattner/// 259d17740295838f94120646ef619b2e187f2d71bdChris Lattnernamespace X86II { 269d17740295838f94120646ef619b2e187f2d71bdChris Lattner enum { 276aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner //===------------------------------------------------------------------===// 286aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner // Instruction types. These are the standard/most common forms for X86 296aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner // instructions. 306aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner // 316aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 324c299f5da1013cd36563a82f188c731b2758074dChris Lattner // PseudoFrm - This represents an instruction that is a pseudo instruction 334c299f5da1013cd36563a82f188c731b2758074dChris Lattner // or one that has not been implemented yet. It is illegal to code generate 344c299f5da1013cd36563a82f188c731b2758074dChris Lattner // it, but tolerated for intermediate implementation stages. 354c299f5da1013cd36563a82f188c731b2758074dChris Lattner Pseudo = 0, 364c299f5da1013cd36563a82f188c731b2758074dChris Lattner 376aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// Raw - This form is for instructions that don't have any operands, so 386aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// they are just a fixed opcode value, like 'leave'. 394c299f5da1013cd36563a82f188c731b2758074dChris Lattner RawFrm = 1, 406aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 416aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// AddRegFrm - This form is used for instructions like 'push r32' that have 426aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// their one register operand added to their opcode. 434c299f5da1013cd36563a82f188c731b2758074dChris Lattner AddRegFrm = 2, 446aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 456aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 466aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// to specify a destination, which in this case is a register. 476aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// 484c299f5da1013cd36563a82f188c731b2758074dChris Lattner MRMDestReg = 3, 496aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 506aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 516aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// to specify a destination, which in this case is memory. 526aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// 534c299f5da1013cd36563a82f188c731b2758074dChris Lattner MRMDestMem = 4, 546aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 556aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 566aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// to specify a source, which in this case is a register. 576aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// 584c299f5da1013cd36563a82f188c731b2758074dChris Lattner MRMSrcReg = 5, 596aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 606aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 616aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// to specify a source, which in this case is memory. 626aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// 634c299f5da1013cd36563a82f188c731b2758074dChris Lattner MRMSrcMem = 6, 646aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 6585b39f229f3146e57d059f1c774400e4bde23987Chris Lattner /// MRMS[0-7][rm] - These forms are used to represent instructions that use 6685b39f229f3146e57d059f1c774400e4bde23987Chris Lattner /// a Mod/RM byte, and use the middle field to hold extended opcode 6785b39f229f3146e57d059f1c774400e4bde23987Chris Lattner /// information. In the intel manual these are represented as /0, /1, ... 6885b39f229f3146e57d059f1c774400e4bde23987Chris Lattner /// 6985b39f229f3146e57d059f1c774400e4bde23987Chris Lattner 7085b39f229f3146e57d059f1c774400e4bde23987Chris Lattner // First, instructions that operate on a register r/m operand... 7185b39f229f3146e57d059f1c774400e4bde23987Chris Lattner MRMS0r = 16, MRMS1r = 17, MRMS2r = 18, MRMS3r = 19, // Format /0 /1 /2 /3 7285b39f229f3146e57d059f1c774400e4bde23987Chris Lattner MRMS4r = 20, MRMS5r = 21, MRMS6r = 22, MRMS7r = 23, // Format /4 /5 /6 /7 7385b39f229f3146e57d059f1c774400e4bde23987Chris Lattner 7485b39f229f3146e57d059f1c774400e4bde23987Chris Lattner // Next, instructions that operate on a memory r/m operand... 7585b39f229f3146e57d059f1c774400e4bde23987Chris Lattner MRMS0m = 24, MRMS1m = 25, MRMS2m = 26, MRMS3m = 27, // Format /0 /1 /2 /3 7685b39f229f3146e57d059f1c774400e4bde23987Chris Lattner MRMS4m = 28, MRMS5m = 29, MRMS6m = 30, MRMS7m = 31, // Format /4 /5 /6 /7 776aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 7885b39f229f3146e57d059f1c774400e4bde23987Chris Lattner FormMask = 31, 796aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 806aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner //===------------------------------------------------------------------===// 816aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner // Actual flags... 826aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 8311e53e3c384e9e25f53a0aec3acf0a725efafeabChris Lattner // OpSize - Set if this instruction requires an operand size prefix (0x66), 8411e53e3c384e9e25f53a0aec3acf0a725efafeabChris Lattner // which most often indicates that the instruction operates on 16 bit data 8511e53e3c384e9e25f53a0aec3acf0a725efafeabChris Lattner // instead of 32 bit data. 862959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner OpSize = 1 << 5, 874c299f5da1013cd36563a82f188c731b2758074dChris Lattner 884c299f5da1013cd36563a82f188c731b2758074dChris Lattner // Op0Mask - There are several prefix bytes that are used to form two byte 894c299f5da1013cd36563a82f188c731b2758074dChris Lattner // opcodes. These are currently 0x0F, and 0xD8-0xDF. This mask is used to 904c299f5da1013cd36563a82f188c731b2758074dChris Lattner // obtain the setting of this field. If no bits in this field is set, there 914c299f5da1013cd36563a82f188c731b2758074dChris Lattner // is no prefix byte for obtaining a multibyte opcode. 924c299f5da1013cd36563a82f188c731b2758074dChris Lattner // 932959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner Op0Shift = 6, 942959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner Op0Mask = 0xF << Op0Shift, 954c299f5da1013cd36563a82f188c731b2758074dChris Lattner 964c299f5da1013cd36563a82f188c731b2758074dChris Lattner // TB - TwoByte - Set if this instruction has a two byte opcode, which 974c299f5da1013cd36563a82f188c731b2758074dChris Lattner // starts with a 0x0F byte before the real opcode. 982959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner TB = 1 << Op0Shift, 994c299f5da1013cd36563a82f188c731b2758074dChris Lattner 1004c299f5da1013cd36563a82f188c731b2758074dChris Lattner // D8-DF - These escape opcodes are used by the floating point unit. These 1014c299f5da1013cd36563a82f188c731b2758074dChris Lattner // values must remain sequential. 1022959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner D8 = 2 << Op0Shift, D9 = 3 << Op0Shift, 1032959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner DA = 4 << Op0Shift, DB = 5 << Op0Shift, 1042959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner DC = 6 << Op0Shift, DD = 7 << Op0Shift, 1052959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner DE = 8 << Op0Shift, DF = 9 << Op0Shift, 1064c299f5da1013cd36563a82f188c731b2758074dChris Lattner 1070c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner //===------------------------------------------------------------------===// 1084c299f5da1013cd36563a82f188c731b2758074dChris Lattner // This three-bit field describes the size of a memory operand. Zero is 1094c299f5da1013cd36563a82f188c731b2758074dChris Lattner // unused so that we can tell if we forgot to set a value. 1102959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner ArgShift = 10, 1112959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner ArgMask = 7 << ArgShift, 1122959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner Arg8 = 1 << ArgShift, 1132959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner Arg16 = 2 << ArgShift, 1142959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner Arg32 = 3 << ArgShift, 1152959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner Arg64 = 4 << ArgShift, // 64 bit int argument for FILD64 1162959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner ArgF32 = 5 << ArgShift, 1172959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner ArgF64 = 6 << ArgShift, 1182959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner ArgF80 = 7 << ArgShift, 1194c299f5da1013cd36563a82f188c731b2758074dChris Lattner 1200c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner //===------------------------------------------------------------------===// 1210c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // FP Instruction Classification... Zero is non-fp instruction. 1220c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 1232959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner // FPTypeMask - Mask for all of the FP types... 1242959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner FPTypeShift = 13, 1252959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner FPTypeMask = 7 << FPTypeShift, 1262959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner 12779b13735adcc034a6869f1fd5670051c6dd0a28aChris Lattner // NotFP - The default, set for instructions that do not use FP registers. 12879b13735adcc034a6869f1fd5670051c6dd0a28aChris Lattner NotFP = 0 << FPTypeShift, 12979b13735adcc034a6869f1fd5670051c6dd0a28aChris Lattner 1300c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 1312959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner ZeroArgFP = 1 << FPTypeShift, 1320c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 1330c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 1342959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner OneArgFP = 2 << FPTypeShift, 1350c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 1360c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 1370c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // result back to ST(0). For example, fcos, fsqrt, etc. 1380c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // 1392959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner OneArgFPRW = 3 << FPTypeShift, 1400c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 1410c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 1420c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // explicit argument, storing the result to either ST(0) or the implicit 1430c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // argument. For example: fadd, fsub, fmul, etc... 1442959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner TwoArgFP = 4 << FPTypeShift, 1450c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 1460c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 1472959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner SpecialFP = 5 << FPTypeShift, 1480c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 149d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke // PrintImplUses - Print out implicit uses in the assembly output. 1502959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner PrintImplUses = 1 << 16, 151d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke 1522959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner OpcodeShift = 17, 1532959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner OpcodeMask = 0xFF << OpcodeShift, 1542959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner // Bits 25 -> 31 are unused 1559d17740295838f94120646ef619b2e187f2d71bdChris Lattner }; 1569d17740295838f94120646ef619b2e187f2d71bdChris Lattner} 1579d17740295838f94120646ef619b2e187f2d71bdChris Lattner 1583501feab811c86c9659248a4875fc31a3165f84dChris Lattnerclass X86InstrInfo : public TargetInstrInfo { 159726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner const X86RegisterInfo RI; 160726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattnerpublic: 161055c965bff7c8567e7fae90ffe1e10e109856064Chris Lattner X86InstrInfo(); 162726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 1633501feab811c86c9659248a4875fc31a3165f84dChris Lattner /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 164726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner /// such, whenever a client has an instance of instruction info, it should 165726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner /// always be able to get register info as well (through this method). 166726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner /// 167726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner virtual const MRegisterInfo &getRegisterInfo() const { return RI; } 168726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 169e9d883828ad92f3a1d06e3c9e98c4e3df937197dMisha Brukman /// createNOPinstr - returns the target's implementation of NOP, which is 170e9d883828ad92f3a1d06e3c9e98c4e3df937197dMisha Brukman /// usually a pseudo-instruction, implemented by a degenerate version of 171e9d883828ad92f3a1d06e3c9e98c4e3df937197dMisha Brukman /// another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0' 172e9d883828ad92f3a1d06e3c9e98c4e3df937197dMisha Brukman /// 173e9d883828ad92f3a1d06e3c9e98c4e3df937197dMisha Brukman MachineInstr* createNOPinstr() const; 174e9d883828ad92f3a1d06e3c9e98c4e3df937197dMisha Brukman 1755e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos // 1765e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos // Return true if the instruction is a register to register move and 1775e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos // leave the source and dest operands in the passed parameters. 1785e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos // 1795e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos virtual bool isMoveInstr(const MachineInstr& MI, 1805e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos unsigned& sourceReg, 1815e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos unsigned& destReg) const; 1825e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos 18312745c55e1d5a6e76d41684f1b507ea7c6b888acMisha Brukman /// isNOPinstr - not having a special NOP opcode, we need to know if a given 18412745c55e1d5a6e76d41684f1b507ea7c6b888acMisha Brukman /// instruction is interpreted as an `official' NOP instr, i.e., there may be 18512745c55e1d5a6e76d41684f1b507ea7c6b888acMisha Brukman /// more than one way to `do nothing' but only one canonical way to slack off. 186e9d883828ad92f3a1d06e3c9e98c4e3df937197dMisha Brukman /// 187e9d883828ad92f3a1d06e3c9e98c4e3df937197dMisha Brukman bool isNOPinstr(const MachineInstr &MI) const; 188e9d883828ad92f3a1d06e3c9e98c4e3df937197dMisha Brukman 189f21dfcddcf199444440004bfa74bb222e2d3ce9eChris Lattner // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 190f21dfcddcf199444440004bfa74bb222e2d3ce9eChris Lattner // specified opcode number. 191f21dfcddcf199444440004bfa74bb222e2d3ce9eChris Lattner // 1924d18d5ce1e62779e7736ca0811e2e1cb06e4ea36Chris Lattner unsigned char getBaseOpcodeFor(unsigned Opcode) const { 1934d18d5ce1e62779e7736ca0811e2e1cb06e4ea36Chris Lattner return get(Opcode).TSFlags >> X86II::OpcodeShift; 1944d18d5ce1e62779e7736ca0811e2e1cb06e4ea36Chris Lattner } 195726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner}; 196726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 197d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 198d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 199726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#endif 200