X86InstrInfo.h revision 7a2bdde0a0eebcd2125055e0eacaca040f0b766c
11e60a9165dc4d6ce5650dacc026f2942696af920Chris Lattner//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 20e0a7a45d3d0a8c865a078459d2e1c6d8967a100Misha Brukman// 3856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell// The LLVM Compiler Infrastructure 4856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 70e0a7a45d3d0a8c865a078459d2e1c6d8967a100Misha Brukman// 8856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell//===----------------------------------------------------------------------===// 9726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner// 103501feab811c86c9659248a4875fc31a3165f84dChris Lattner// This file contains the X86 implementation of the TargetInstrInfo class. 11726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner// 12726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner//===----------------------------------------------------------------------===// 13726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 14726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#ifndef X86INSTRUCTIONINFO_H 15726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#define X86INSTRUCTIONINFO_H 16726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 173501feab811c86c9659248a4875fc31a3165f84dChris Lattner#include "llvm/Target/TargetInstrInfo.h" 1852e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray#include "X86.h" 19726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#include "X86RegisterInfo.h" 20d68a07650cdb2e18f18f362ba533459aa10e01b6Dan Gohman#include "llvm/ADT/DenseMap.h" 21726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 22d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 2325ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng class X86RegisterInfo; 24aa3c1410b427909da350f2b5e8d4ec3db62a3618Evan Cheng class X86TargetMachine; 25d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 267fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattnernamespace X86 { 27ac0ed5dc082dff9ce359af5422f5b82047b4fe6bChris Lattner // Enums for memory operand decoding. Each memory operand is represented with 28ac0ed5dc082dff9ce359af5422f5b82047b4fe6bChris Lattner // a 5 operand sequence in the form: 29ac0ed5dc082dff9ce359af5422f5b82047b4fe6bChris Lattner // [BaseReg, ScaleAmt, IndexReg, Disp, Segment] 30ac0ed5dc082dff9ce359af5422f5b82047b4fe6bChris Lattner // These enums help decode this. 31ac0ed5dc082dff9ce359af5422f5b82047b4fe6bChris Lattner enum { 32ac0ed5dc082dff9ce359af5422f5b82047b4fe6bChris Lattner AddrBaseReg = 0, 33ac0ed5dc082dff9ce359af5422f5b82047b4fe6bChris Lattner AddrScaleAmt = 1, 34ac0ed5dc082dff9ce359af5422f5b82047b4fe6bChris Lattner AddrIndexReg = 2, 35ac0ed5dc082dff9ce359af5422f5b82047b4fe6bChris Lattner AddrDisp = 3, 368d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 37ac0ed5dc082dff9ce359af5422f5b82047b4fe6bChris Lattner /// AddrSegmentReg - The operand # of the segment in the memory operand. 38ac0ed5dc082dff9ce359af5422f5b82047b4fe6bChris Lattner AddrSegmentReg = 4, 39ac0ed5dc082dff9ce359af5422f5b82047b4fe6bChris Lattner 40ac0ed5dc082dff9ce359af5422f5b82047b4fe6bChris Lattner /// AddrNumOperands - Total number of operands in a memory reference. 41ac0ed5dc082dff9ce359af5422f5b82047b4fe6bChris Lattner AddrNumOperands = 5 42ac0ed5dc082dff9ce359af5422f5b82047b4fe6bChris Lattner }; 438d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 448d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 457fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner // X86 specific condition code. These correspond to X86_*_COND in 467fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner // X86InstrInfo.td. They must be kept in synch. 477fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner enum CondCode { 487fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_A = 0, 497fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_AE = 1, 507fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_B = 2, 517fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_BE = 3, 527fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_E = 4, 537fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_G = 5, 547fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_GE = 6, 557fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_L = 7, 567fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_LE = 8, 577fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_NE = 9, 587fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_NO = 10, 597fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_NP = 11, 607fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_NS = 12, 61653456c351d9bf908ebd982f6ae9df3449c5f34bDan Gohman COND_O = 13, 62653456c351d9bf908ebd982f6ae9df3449c5f34bDan Gohman COND_P = 14, 63653456c351d9bf908ebd982f6ae9df3449c5f34bDan Gohman COND_S = 15, 64279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman 65279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman // Artificial condition codes. These are used by AnalyzeBranch 66279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman // to indicate a block terminated with two conditional branches to 67279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 68279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman // which can't be represented on x86 with a single condition. These 69279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman // are never used in MachineInstrs. 70279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman COND_NE_OR_P, 71279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman COND_NP_OR_E, 72279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman 737fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_INVALID 747fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner }; 758d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 767fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner // Turn condition code into conditional branch opcode. 777fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner unsigned GetCondBranchFromCond(CondCode CC); 788d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 799cd68759178f9fe25c72253d338e78e414f1d770Chris Lattner /// GetOppositeBranchCondition - Return the inverse of the specified cond, 809cd68759178f9fe25c72253d338e78e414f1d770Chris Lattner /// e.g. turning COND_E to COND_NE. 819cd68759178f9fe25c72253d338e78e414f1d770Chris Lattner CondCode GetOppositeBranchCondition(X86::CondCode CC); 829cd68759178f9fe25c72253d338e78e414f1d770Chris Lattner 837fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner} 848d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 859d17740295838f94120646ef619b2e187f2d71bdChris Lattner/// X86II - This namespace holds all of the target specific flags that 869d17740295838f94120646ef619b2e187f2d71bdChris Lattner/// instruction info tracks. 879d17740295838f94120646ef619b2e187f2d71bdChris Lattner/// 889d17740295838f94120646ef619b2e187f2d71bdChris Lattnernamespace X86II { 893b6b36d6f54e780a2947cb1b9efe4eed7c40dc11Chris Lattner /// Target Operand Flag enum. 903b6b36d6f54e780a2947cb1b9efe4eed7c40dc11Chris Lattner enum TOF { 916aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner //===------------------------------------------------------------------===// 92ac5e887a6cf0a6182664d8c11beb0d2270272b02Chris Lattner // X86 Specific MachineOperand flags. 938d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 9401a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_NO_FLAG, 958d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 96ac5e887a6cf0a6182664d8c11beb0d2270272b02Chris Lattner /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 97ac5e887a6cf0a6182664d8c11beb0d2270272b02Chris Lattner /// relocation of: 9855e7c827301da0e5e03b26835bff259c320b3bf7Chris Lattner /// SYMBOL_LABEL + [. - PICBASELABEL] 9901a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_GOT_ABSOLUTE_ADDRESS, 1008d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 10155e7c827301da0e5e03b26835bff259c320b3bf7Chris Lattner /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 10255e7c827301da0e5e03b26835bff259c320b3bf7Chris Lattner /// immediate should get the value of the symbol minus the PIC base label: 10355e7c827301da0e5e03b26835bff259c320b3bf7Chris Lattner /// SYMBOL_LABEL - PICBASELABEL 10401a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_PIC_BASE_OFFSET, 10555e7c827301da0e5e03b26835bff259c320b3bf7Chris Lattner 106b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// MO_GOT - On a symbol operand this indicates that the immediate is the 107b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// offset to the GOT entry for the symbol name from the base of the GOT. 108b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// 1098d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick /// See the X86-64 ELF ABI supplement for more details. 110b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// SYMBOL_LABEL @GOT 11101a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_GOT, 1128d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 113b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 1148d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick /// the offset to the location of the symbol name from the base of the GOT. 115b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// 1168d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick /// See the X86-64 ELF ABI supplement for more details. 11755e7c827301da0e5e03b26835bff259c320b3bf7Chris Lattner /// SYMBOL_LABEL @GOTOFF 11801a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_GOTOFF, 1198d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 120b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 121b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// offset to the GOT entry for the symbol name from the current code 1228d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick /// location. 123b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// 1248d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick /// See the X86-64 ELF ABI supplement for more details. 125b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// SYMBOL_LABEL @GOTPCREL 12601a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_GOTPCREL, 1278d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 128b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// MO_PLT - On a symbol operand this indicates that the immediate is 1298d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick /// offset to the PLT entry of symbol name from the current code location. 130b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// 1318d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick /// See the X86-64 ELF ABI supplement for more details. 132b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// SYMBOL_LABEL @PLT 13301a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_PLT, 1348d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 135b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// MO_TLSGD - On a symbol operand this indicates that the immediate is 136b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// some TLS offset. 137b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// 1388d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick /// See 'ELF Handling for Thread-Local Storage' for more details. 139b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// SYMBOL_LABEL @TLSGD 14001a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_TLSGD, 1418d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 142b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 143b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// some TLS offset. 144b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// 1458d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick /// See 'ELF Handling for Thread-Local Storage' for more details. 146b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// SYMBOL_LABEL @GOTTPOFF 14701a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_GOTTPOFF, 1488d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 149b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 150b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// some TLS offset. 151b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// 1528d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick /// See 'ELF Handling for Thread-Local Storage' for more details. 153b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// SYMBOL_LABEL @INDNTPOFF 15401a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_INDNTPOFF, 1558d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 156b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// MO_TPOFF - On a symbol operand this indicates that the immediate is 157b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// some TLS offset. 158b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// 1598d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick /// See 'ELF Handling for Thread-Local Storage' for more details. 160b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// SYMBOL_LABEL @TPOFF 16101a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_TPOFF, 1628d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 163b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 164b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// some TLS offset. 165b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// 1668d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick /// See 'ELF Handling for Thread-Local Storage' for more details. 167b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// SYMBOL_LABEL @NTPOFF 16801a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_NTPOFF, 1698d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 1704aa21aa6d13b8ea00eb0817e53f24e5416ed3038Chris Lattner /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 1714aa21aa6d13b8ea00eb0817e53f24e5416ed3038Chris Lattner /// reference is actually to the "__imp_FOO" symbol. This is used for 1724aa21aa6d13b8ea00eb0817e53f24e5416ed3038Chris Lattner /// dllimport linkage on windows. 17301a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_DLLIMPORT, 1748d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 17574e726e3270c99169cc90fb3c676eeaae273f48cChris Lattner /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the 17674e726e3270c99169cc90fb3c676eeaae273f48cChris Lattner /// reference is actually to the "FOO$stub" symbol. This is used for calls 17721d272874b750201272ef3f00441b58932c3d769Chris Lattner /// and jumps to external functions on Tiger and earlier. 17801a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_DARWIN_STUB, 1798d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 18075cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 18175cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 18275cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 18301a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_DARWIN_NONLAZY, 18475cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner 18575cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 18675cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 18775cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 18801a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_DARWIN_NONLAZY_PIC_BASE, 1898d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 19075cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this 19175cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE", 19275cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner /// which is a PIC-base-relative reference to a hidden dyld lazy pointer 19375cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner /// stub. 19430ef0e5658b0b8b04437f73f74162d5d72923f29Eric Christopher MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, 1958d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 19630ef0e5658b0b8b04437f73f74162d5d72923f29Eric Christopher /// MO_TLVP - On a symbol operand this indicates that the immediate is 19730ef0e5658b0b8b04437f73f74162d5d72923f29Eric Christopher /// some TLS offset. 19830ef0e5658b0b8b04437f73f74162d5d72923f29Eric Christopher /// 19930ef0e5658b0b8b04437f73f74162d5d72923f29Eric Christopher /// This is the TLS offset for the Darwin TLS mechanism. 20030ef0e5658b0b8b04437f73f74162d5d72923f29Eric Christopher MO_TLVP, 2018d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 20230ef0e5658b0b8b04437f73f74162d5d72923f29Eric Christopher /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate 20330ef0e5658b0b8b04437f73f74162d5d72923f29Eric Christopher /// is some TLS offset from the picbase. 20430ef0e5658b0b8b04437f73f74162d5d72923f29Eric Christopher /// 20530ef0e5658b0b8b04437f73f74162d5d72923f29Eric Christopher /// This is the 32-bit TLS offset for Darwin TLS in PIC mode. 20630ef0e5658b0b8b04437f73f74162d5d72923f29Eric Christopher MO_TLVP_PIC_BASE 207281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner }; 208281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner} 209281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner 2103b6b36d6f54e780a2947cb1b9efe4eed7c40dc11Chris Lattner/// isGlobalStubReference - Return true if the specified TargetFlag operand is 211281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner/// a reference to a stub for a global, not the global itself. 2123b6b36d6f54e780a2947cb1b9efe4eed7c40dc11Chris Lattnerinline static bool isGlobalStubReference(unsigned char TargetFlag) { 2133b6b36d6f54e780a2947cb1b9efe4eed7c40dc11Chris Lattner switch (TargetFlag) { 214281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner case X86II::MO_DLLIMPORT: // dllimport stub. 215281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner case X86II::MO_GOTPCREL: // rip-relative GOT reference. 216281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner case X86II::MO_GOT: // normal GOT reference. 217281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. 218281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. 219281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref. 220281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner return true; 221281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner default: 222281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner return false; 223281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner } 224281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner} 2257478ab8502a52815413d8b388898f719484ab1a9Chris Lattner 2267478ab8502a52815413d8b388898f719484ab1a9Chris Lattner/// isGlobalRelativeToPICBase - Return true if the specified global value 2277478ab8502a52815413d8b388898f719484ab1a9Chris Lattner/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this 2287478ab8502a52815413d8b388898f719484ab1a9Chris Lattner/// is true, the addressing mode has the PIC base register added in (e.g. EBX). 2297478ab8502a52815413d8b388898f719484ab1a9Chris Lattnerinline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { 2307478ab8502a52815413d8b388898f719484ab1a9Chris Lattner switch (TargetFlag) { 2317478ab8502a52815413d8b388898f719484ab1a9Chris Lattner case X86II::MO_GOTOFF: // isPICStyleGOT: local global. 2327478ab8502a52815413d8b388898f719484ab1a9Chris Lattner case X86II::MO_GOT: // isPICStyleGOT: other global. 2337478ab8502a52815413d8b388898f719484ab1a9Chris Lattner case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. 2347478ab8502a52815413d8b388898f719484ab1a9Chris Lattner case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. 2357478ab8502a52815413d8b388898f719484ab1a9Chris Lattner case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global. 23630ef0e5658b0b8b04437f73f74162d5d72923f29Eric Christopher case X86II::MO_TLVP: // ??? Pretty sure.. 2377478ab8502a52815413d8b388898f719484ab1a9Chris Lattner return true; 2387478ab8502a52815413d8b388898f719484ab1a9Chris Lattner default: 2397478ab8502a52815413d8b388898f719484ab1a9Chris Lattner return false; 2407478ab8502a52815413d8b388898f719484ab1a9Chris Lattner } 2417478ab8502a52815413d8b388898f719484ab1a9Chris Lattner} 2428d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 243281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner/// X86II - This namespace holds all of the target specific flags that 244281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner/// instruction info tracks. 245281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner/// 246281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattnernamespace X86II { 247281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner enum { 248ac5e887a6cf0a6182664d8c11beb0d2270272b02Chris Lattner //===------------------------------------------------------------------===// 249ac5e887a6cf0a6182664d8c11beb0d2270272b02Chris Lattner // Instruction encodings. These are the standard/most common forms for X86 2506aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner // instructions. 2516aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner // 2526aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 2534c299f5da1013cd36563a82f188c731b2758074dChris Lattner // PseudoFrm - This represents an instruction that is a pseudo instruction 2544c299f5da1013cd36563a82f188c731b2758074dChris Lattner // or one that has not been implemented yet. It is illegal to code generate 2554c299f5da1013cd36563a82f188c731b2758074dChris Lattner // it, but tolerated for intermediate implementation stages. 2564c299f5da1013cd36563a82f188c731b2758074dChris Lattner Pseudo = 0, 2574c299f5da1013cd36563a82f188c731b2758074dChris Lattner 2586aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// Raw - This form is for instructions that don't have any operands, so 2596aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// they are just a fixed opcode value, like 'leave'. 2604c299f5da1013cd36563a82f188c731b2758074dChris Lattner RawFrm = 1, 2610e0a7a45d3d0a8c865a078459d2e1c6d8967a100Misha Brukman 2626aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// AddRegFrm - This form is used for instructions like 'push r32' that have 2636aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// their one register operand added to their opcode. 2644c299f5da1013cd36563a82f188c731b2758074dChris Lattner AddRegFrm = 2, 2656aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 2666aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 2676aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// to specify a destination, which in this case is a register. 2686aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// 2694c299f5da1013cd36563a82f188c731b2758074dChris Lattner MRMDestReg = 3, 2706aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 2716aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 2726aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// to specify a destination, which in this case is memory. 2736aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// 2744c299f5da1013cd36563a82f188c731b2758074dChris Lattner MRMDestMem = 4, 2756aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 2766aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 2776aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// to specify a source, which in this case is a register. 2786aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// 2794c299f5da1013cd36563a82f188c731b2758074dChris Lattner MRMSrcReg = 5, 2806aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 2816aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 2826aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// to specify a source, which in this case is memory. 2836aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// 2844c299f5da1013cd36563a82f188c731b2758074dChris Lattner MRMSrcMem = 6, 2850e0a7a45d3d0a8c865a078459d2e1c6d8967a100Misha Brukman 286169584ed45f62f91599bed3d019640e168d815eaAlkis Evlogimenos /// MRM[0-7][rm] - These forms are used to represent instructions that use 28785b39f229f3146e57d059f1c774400e4bde23987Chris Lattner /// a Mod/RM byte, and use the middle field to hold extended opcode 28885b39f229f3146e57d059f1c774400e4bde23987Chris Lattner /// information. In the intel manual these are represented as /0, /1, ... 28985b39f229f3146e57d059f1c774400e4bde23987Chris Lattner /// 29085b39f229f3146e57d059f1c774400e4bde23987Chris Lattner 29185b39f229f3146e57d059f1c774400e4bde23987Chris Lattner // First, instructions that operate on a register r/m operand... 292169584ed45f62f91599bed3d019640e168d815eaAlkis Evlogimenos MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 293169584ed45f62f91599bed3d019640e168d815eaAlkis Evlogimenos MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 29485b39f229f3146e57d059f1c774400e4bde23987Chris Lattner 29585b39f229f3146e57d059f1c774400e4bde23987Chris Lattner // Next, instructions that operate on a memory r/m operand... 296169584ed45f62f91599bed3d019640e168d815eaAlkis Evlogimenos MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 297169584ed45f62f91599bed3d019640e168d815eaAlkis Evlogimenos MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 2986aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 2993c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng // MRMInitReg - This form is used for instructions whose source and 3003c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng // destinations are the same register. 3013c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng MRMInitReg = 32, 3028d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 3030d8db8e0a8492ab2d4bef725ec61b519471b97ecChris Lattner //// MRM_C1 - A mod/rm byte of exactly 0xC1. 3040d8db8e0a8492ab2d4bef725ec61b519471b97ecChris Lattner MRM_C1 = 33, 305a599de241041eebc84867ac8e4cb76668cabd236Chris Lattner MRM_C2 = 34, 306a599de241041eebc84867ac8e4cb76668cabd236Chris Lattner MRM_C3 = 35, 307a599de241041eebc84867ac8e4cb76668cabd236Chris Lattner MRM_C4 = 36, 308a599de241041eebc84867ac8e4cb76668cabd236Chris Lattner MRM_C8 = 37, 309a599de241041eebc84867ac8e4cb76668cabd236Chris Lattner MRM_C9 = 38, 310a599de241041eebc84867ac8e4cb76668cabd236Chris Lattner MRM_E8 = 39, 311a599de241041eebc84867ac8e4cb76668cabd236Chris Lattner MRM_F0 = 40, 312a599de241041eebc84867ac8e4cb76668cabd236Chris Lattner MRM_F8 = 41, 313b779033a23c49c2e5e02b15a87bbae42973287b3Chris Lattner MRM_F9 = 42, 31487ca0e077d91b96a765b3b24cadfa8891026a33aRafael Espindola MRM_D0 = 45, 31587ca0e077d91b96a765b3b24cadfa8891026a33aRafael Espindola MRM_D1 = 46, 31640cc3f8783a4e426a0d439bb2b070b5c072b5947Chris Lattner 31740cc3f8783a4e426a0d439bb2b070b5c072b5947Chris Lattner /// RawFrmImm8 - This is used for the ENTER instruction, which has two 31840cc3f8783a4e426a0d439bb2b070b5c072b5947Chris Lattner /// immediates, the first of which is a 16-bit immediate (specified by 31940cc3f8783a4e426a0d439bb2b070b5c072b5947Chris Lattner /// the imm encoding) and the second is a 8-bit fixed value. 32040cc3f8783a4e426a0d439bb2b070b5c072b5947Chris Lattner RawFrmImm8 = 43, 3218d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 32259f8a6a66621f7c6f45b838e48fbf210af9d1fb5Chris Lattner /// RawFrmImm16 - This is used for CALL FAR instructions, which have two 32359f8a6a66621f7c6f45b838e48fbf210af9d1fb5Chris Lattner /// immediates, the first of which is a 16 or 32-bit immediate (specified by 32459f8a6a66621f7c6f45b838e48fbf210af9d1fb5Chris Lattner /// the imm encoding) and the second is a 16-bit fixed value. In the AMD 32559f8a6a66621f7c6f45b838e48fbf210af9d1fb5Chris Lattner /// manual, this operand is described as pntr16:32 and pntr16:16 32640cc3f8783a4e426a0d439bb2b070b5c072b5947Chris Lattner RawFrmImm16 = 44, 3273c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng 3283c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng FormMask = 63, 3296aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 3306aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner //===------------------------------------------------------------------===// 3316aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner // Actual flags... 3326aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 33311e53e3c384e9e25f53a0aec3acf0a725efafeabChris Lattner // OpSize - Set if this instruction requires an operand size prefix (0x66), 33411e53e3c384e9e25f53a0aec3acf0a725efafeabChris Lattner // which most often indicates that the instruction operates on 16 bit data 33511e53e3c384e9e25f53a0aec3acf0a725efafeabChris Lattner // instead of 32 bit data. 3363c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng OpSize = 1 << 6, 3374c299f5da1013cd36563a82f188c731b2758074dChris Lattner 33825ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // AsSize - Set if this instruction requires an operand size prefix (0x67), 33925ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // which most often indicates that the instruction address 16 bit address 34025ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // instead of 32 bit address (or 32 bit address in 64 bit mode). 34125ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng AdSize = 1 << 7, 34225ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng 34325ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng //===------------------------------------------------------------------===// 3444c299f5da1013cd36563a82f188c731b2758074dChris Lattner // Op0Mask - There are several prefix bytes that are used to form two byte 345915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 346915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner // used to obtain the setting of this field. If no bits in this field is 347915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner // set, there is no prefix byte for obtaining a multibyte opcode. 3484c299f5da1013cd36563a82f188c731b2758074dChris Lattner // 34925ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng Op0Shift = 8, 350229e4523f2f12929defa09ac4ef9f3652f21f1ecJoerg Sonnenberger Op0Mask = 0x1F << Op0Shift, 3514c299f5da1013cd36563a82f188c731b2758074dChris Lattner 3524c299f5da1013cd36563a82f188c731b2758074dChris Lattner // TB - TwoByte - Set if this instruction has a two byte opcode, which 3534c299f5da1013cd36563a82f188c731b2758074dChris Lattner // starts with a 0x0F byte before the real opcode. 3542959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner TB = 1 << Op0Shift, 3554c299f5da1013cd36563a82f188c731b2758074dChris Lattner 356915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner // REP - The 0xF3 prefix byte indicating repetition of the following 357915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner // instruction. 358915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner REP = 2 << Op0Shift, 359915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner 3604c299f5da1013cd36563a82f188c731b2758074dChris Lattner // D8-DF - These escape opcodes are used by the floating point unit. These 3614c299f5da1013cd36563a82f188c731b2758074dChris Lattner // values must remain sequential. 362915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 363915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner DA = 5 << Op0Shift, DB = 6 << Op0Shift, 364915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner DC = 7 << Op0Shift, DD = 8 << Op0Shift, 365915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner DE = 9 << Op0Shift, DF = 10 << Op0Shift, 3669eb59ec548b861d6ede05b4e6dc22aabf645e665Jeff Cohen 367f63be7d3959939b2ffaf0bba5519b71216ec9ee6Nate Begeman // XS, XD - These prefix codes are for single and double precision scalar 368f63be7d3959939b2ffaf0bba5519b71216ec9ee6Nate Begeman // floating point operations performed in the SSE registers. 369bb1ee05253d965e0944351a21e9970c02b1aebfeBill Wendling XD = 11 << Op0Shift, XS = 12 << Op0Shift, 370bb1ee05253d965e0944351a21e9970c02b1aebfeBill Wendling 3714a8ac8de1ddfeaadb9ff13ce361bfc6435f18028Joerg Sonnenberger // T8, TA, A6, A7 - Prefix after the 0x0F prefix. 372bb1ee05253d965e0944351a21e9970c02b1aebfeBill Wendling T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 3734a8ac8de1ddfeaadb9ff13ce361bfc6435f18028Joerg Sonnenberger A6 = 15 << Op0Shift, A7 = 16 << Op0Shift, 3748d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 375b4dc13cab7ef894d3bb17657fa993b9f09af476bEric Christopher // TF - Prefix before and after 0x0F 3764a8ac8de1ddfeaadb9ff13ce361bfc6435f18028Joerg Sonnenberger TF = 17 << Op0Shift, 3774c299f5da1013cd36563a82f188c731b2758074dChris Lattner 3780c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner //===------------------------------------------------------------------===// 37925ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 38025ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // They are used to specify GPRs and SSE registers, 64-bit operand size, 38125ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // etc. We only cares about REX.W and REX.R bits and only the former is 38225ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // statically determined. 38325ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // 384229e4523f2f12929defa09ac4ef9f3652f21f1ecJoerg Sonnenberger REXShift = Op0Shift + 5, 38525ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng REX_W = 1 << REXShift, 38625ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng 38725ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng //===------------------------------------------------------------------===// 38825ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // This three-bit field describes the size of an immediate operand. Zero is 3895ab29b504d49d3fa84d76f79e73704260f900682Alkis Evlogimenos // unused so that we can tell if we forgot to set a value. 390229e4523f2f12929defa09ac4ef9f3652f21f1ecJoerg Sonnenberger ImmShift = REXShift + 1, 391a0331199fc1a6edc5cf0b41d4745c843b82b51e9Chris Lattner ImmMask = 7 << ImmShift, 392a0331199fc1a6edc5cf0b41d4745c843b82b51e9Chris Lattner Imm8 = 1 << ImmShift, 393a0331199fc1a6edc5cf0b41d4745c843b82b51e9Chris Lattner Imm8PCRel = 2 << ImmShift, 394a0331199fc1a6edc5cf0b41d4745c843b82b51e9Chris Lattner Imm16 = 3 << ImmShift, 3959fc05227a2596c545b845ed9a72673995e49d16bChris Lattner Imm16PCRel = 4 << ImmShift, 3969fc05227a2596c545b845ed9a72673995e49d16bChris Lattner Imm32 = 5 << ImmShift, 3979fc05227a2596c545b845ed9a72673995e49d16bChris Lattner Imm32PCRel = 6 << ImmShift, 3989fc05227a2596c545b845ed9a72673995e49d16bChris Lattner Imm64 = 7 << ImmShift, 3994c299f5da1013cd36563a82f188c731b2758074dChris Lattner 4000c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner //===------------------------------------------------------------------===// 4010c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // FP Instruction Classification... Zero is non-fp instruction. 4020c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 4032959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner // FPTypeMask - Mask for all of the FP types... 404229e4523f2f12929defa09ac4ef9f3652f21f1ecJoerg Sonnenberger FPTypeShift = ImmShift + 3, 4052959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner FPTypeMask = 7 << FPTypeShift, 4062959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner 40779b13735adcc034a6869f1fd5670051c6dd0a28aChris Lattner // NotFP - The default, set for instructions that do not use FP registers. 40879b13735adcc034a6869f1fd5670051c6dd0a28aChris Lattner NotFP = 0 << FPTypeShift, 40979b13735adcc034a6869f1fd5670051c6dd0a28aChris Lattner 4100c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 4112959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner ZeroArgFP = 1 << FPTypeShift, 4120c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 4130c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 4142959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner OneArgFP = 2 << FPTypeShift, 4150c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 4160c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 4170c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // result back to ST(0). For example, fcos, fsqrt, etc. 4180c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // 4192959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner OneArgFPRW = 3 << FPTypeShift, 4200c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 4210c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 4220c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // explicit argument, storing the result to either ST(0) or the implicit 4230c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // argument. For example: fadd, fsub, fmul, etc... 4242959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner TwoArgFP = 4 << FPTypeShift, 4250c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 426ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 427ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner // explicit argument, but have no destination. Example: fucom, fucomi, ... 428ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner CompareFP = 5 << FPTypeShift, 429ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner 4301c54a8544788156d6864430182a3a79b8839b7daChris Lattner // CondMovFP - "2 operand" floating point conditional move instructions. 431ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner CondMovFP = 6 << FPTypeShift, 4321c54a8544788156d6864430182a3a79b8839b7daChris Lattner 4330c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 434ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner SpecialFP = 7 << FPTypeShift, 4351c54a8544788156d6864430182a3a79b8839b7daChris Lattner 436ea7da50e5a7f291295c10d91fc3fdba76d339579Andrew Lenharth // Lock prefix 437229e4523f2f12929defa09ac4ef9f3652f21f1ecJoerg Sonnenberger LOCKShift = FPTypeShift + 3, 438ea7da50e5a7f291295c10d91fc3fdba76d339579Andrew Lenharth LOCK = 1 << LOCKShift, 439ea7da50e5a7f291295c10d91fc3fdba76d339579Andrew Lenharth 440ef93cecd80ebdecb0ea2b2c316370998151308e2Anton Korobeynikov // Segment override prefixes. Currently we just need ability to address 441ef93cecd80ebdecb0ea2b2c316370998151308e2Anton Korobeynikov // stuff in gs and fs segments. 442229e4523f2f12929defa09ac4ef9f3652f21f1ecJoerg Sonnenberger SegOvrShift = LOCKShift + 1, 443ef93cecd80ebdecb0ea2b2c316370998151308e2Anton Korobeynikov SegOvrMask = 3 << SegOvrShift, 444ef93cecd80ebdecb0ea2b2c316370998151308e2Anton Korobeynikov FS = 1 << SegOvrShift, 445ef93cecd80ebdecb0ea2b2c316370998151308e2Anton Korobeynikov GS = 2 << SegOvrShift, 446ef93cecd80ebdecb0ea2b2c316370998151308e2Anton Korobeynikov 447229e4523f2f12929defa09ac4ef9f3652f21f1ecJoerg Sonnenberger // Execution domain for SSE instructions in bits 23, 24. 448229e4523f2f12929defa09ac4ef9f3652f21f1ecJoerg Sonnenberger // 0 in bits 23-24 means normal, non-SSE instruction. 449229e4523f2f12929defa09ac4ef9f3652f21f1ecJoerg Sonnenberger SSEDomainShift = SegOvrShift + 2, 450352aa503faee6c58e9cdb5054cc5ec1d90c696b4Jakob Stoklund Olesen 451229e4523f2f12929defa09ac4ef9f3652f21f1ecJoerg Sonnenberger OpcodeShift = SSEDomainShift + 2, 452c15a91dfc84822037c40ae9d37f63ce1b1a763bbJoerg Sonnenberger OpcodeMask = 0xFFULL << OpcodeShift, 45399405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes 45499405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes //===------------------------------------------------------------------===// 455548abfcbd671b1144bf517b17643259dcae76f4fChris Lattner /// VEX - The opcode prefix used by AVX instructions 456229e4523f2f12929defa09ac4ef9f3652f21f1ecJoerg Sonnenberger VEXShift = OpcodeShift + 8, 457e943c15621035fa7fbeda7b4922d06a8c2b05b2dBruno Cardoso Lopes VEX = 1U << 0, 45807de40629f73fb018a2a7f0a5bbd1ee4defe95fdBruno Cardoso Lopes 459548abfcbd671b1144bf517b17643259dcae76f4fChris Lattner /// VEX_W - Has a opcode specific functionality, but is used in the same 460548abfcbd671b1144bf517b17643259dcae76f4fChris Lattner /// way as REX_W is for regular SSE instructions. 461e943c15621035fa7fbeda7b4922d06a8c2b05b2dBruno Cardoso Lopes VEX_W = 1U << 1, 46207de40629f73fb018a2a7f0a5bbd1ee4defe95fdBruno Cardoso Lopes 463548abfcbd671b1144bf517b17643259dcae76f4fChris Lattner /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2 464548abfcbd671b1144bf517b17643259dcae76f4fChris Lattner /// address instructions in SSE are represented as 3 address ones in AVX 465548abfcbd671b1144bf517b17643259dcae76f4fChris Lattner /// and the additional register is encoded in VEX_VVVV prefix. 466e943c15621035fa7fbeda7b4922d06a8c2b05b2dBruno Cardoso Lopes VEX_4V = 1U << 2, 46707de40629f73fb018a2a7f0a5bbd1ee4defe95fdBruno Cardoso Lopes 468548abfcbd671b1144bf517b17643259dcae76f4fChris Lattner /// VEX_I8IMM - Specifies that the last register used in a AVX instruction, 469548abfcbd671b1144bf517b17643259dcae76f4fChris Lattner /// must be encoded in the i8 immediate field. This usually happens in 470548abfcbd671b1144bf517b17643259dcae76f4fChris Lattner /// instructions with 4 operands. 471e943c15621035fa7fbeda7b4922d06a8c2b05b2dBruno Cardoso Lopes VEX_I8IMM = 1U << 3, 47287a85c7ef0d1a96c73473de90d3b2b28d24538a5Bruno Cardoso Lopes 473548abfcbd671b1144bf517b17643259dcae76f4fChris Lattner /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current 474548abfcbd671b1144bf517b17643259dcae76f4fChris Lattner /// instruction uses 256-bit wide registers. This is usually auto detected 475548abfcbd671b1144bf517b17643259dcae76f4fChris Lattner /// if a VR256 register is used, but some AVX instructions also have this 476548abfcbd671b1144bf517b17643259dcae76f4fChris Lattner /// field marked when using a f256 memory references. 477548abfcbd671b1144bf517b17643259dcae76f4fChris Lattner VEX_L = 1U << 4, 4788d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 479548abfcbd671b1144bf517b17643259dcae76f4fChris Lattner /// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the 480548abfcbd671b1144bf517b17643259dcae76f4fChris Lattner /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents 481548abfcbd671b1144bf517b17643259dcae76f4fChris Lattner /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction 482548abfcbd671b1144bf517b17643259dcae76f4fChris Lattner /// storing a classifier in the imm8 field. To simplify our implementation, 483548abfcbd671b1144bf517b17643259dcae76f4fChris Lattner /// we handle this by storeing the classifier in the opcode field and using 484548abfcbd671b1144bf517b17643259dcae76f4fChris Lattner /// this flag to indicate that the encoder should do the wacky 3DNow! thing. 485548abfcbd671b1144bf517b17643259dcae76f4fChris Lattner Has3DNow0F0FOpcode = 1U << 5 48699405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes }; 4878d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 48874a2151392a08e202f497ece7a3129663526d431Chris Lattner // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 48974a2151392a08e202f497ece7a3129663526d431Chris Lattner // specified machine instruction. 49074a2151392a08e202f497ece7a3129663526d431Chris Lattner // 49199405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { 49274a2151392a08e202f497ece7a3129663526d431Chris Lattner return TSFlags >> X86II::OpcodeShift; 49374a2151392a08e202f497ece7a3129663526d431Chris Lattner } 4948d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 49599405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes static inline bool hasImm(uint64_t TSFlags) { 496835acabce13993e210b7cef0020a585125f9cb1eChris Lattner return (TSFlags & X86II::ImmMask) != 0; 497835acabce13993e210b7cef0020a585125f9cb1eChris Lattner } 4988d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 49974a2151392a08e202f497ece7a3129663526d431Chris Lattner /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field 50074a2151392a08e202f497ece7a3129663526d431Chris Lattner /// of the specified instruction. 50199405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes static inline unsigned getSizeOfImm(uint64_t TSFlags) { 50274a2151392a08e202f497ece7a3129663526d431Chris Lattner switch (TSFlags & X86II::ImmMask) { 50374a2151392a08e202f497ece7a3129663526d431Chris Lattner default: assert(0 && "Unknown immediate size"); 504a0331199fc1a6edc5cf0b41d4745c843b82b51e9Chris Lattner case X86II::Imm8: 505a0331199fc1a6edc5cf0b41d4745c843b82b51e9Chris Lattner case X86II::Imm8PCRel: return 1; 5069fc05227a2596c545b845ed9a72673995e49d16bChris Lattner case X86II::Imm16: 5079fc05227a2596c545b845ed9a72673995e49d16bChris Lattner case X86II::Imm16PCRel: return 2; 508a0331199fc1a6edc5cf0b41d4745c843b82b51e9Chris Lattner case X86II::Imm32: 509a0331199fc1a6edc5cf0b41d4745c843b82b51e9Chris Lattner case X86II::Imm32PCRel: return 4; 510a0331199fc1a6edc5cf0b41d4745c843b82b51e9Chris Lattner case X86II::Imm64: return 8; 511a0331199fc1a6edc5cf0b41d4745c843b82b51e9Chris Lattner } 512a0331199fc1a6edc5cf0b41d4745c843b82b51e9Chris Lattner } 5138d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 514a0331199fc1a6edc5cf0b41d4745c843b82b51e9Chris Lattner /// isImmPCRel - Return true if the immediate of the specified instruction's 515a0331199fc1a6edc5cf0b41d4745c843b82b51e9Chris Lattner /// TSFlags indicates that it is pc relative. 51699405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes static inline unsigned isImmPCRel(uint64_t TSFlags) { 517a0331199fc1a6edc5cf0b41d4745c843b82b51e9Chris Lattner switch (TSFlags & X86II::ImmMask) { 518751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner default: assert(0 && "Unknown immediate size"); 519751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::Imm8PCRel: 520751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::Imm16PCRel: 521751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::Imm32PCRel: 522751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner return true; 523751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::Imm8: 524751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::Imm16: 525751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::Imm32: 526751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::Imm64: 527751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner return false; 52874a2151392a08e202f497ece7a3129663526d431Chris Lattner } 529751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner } 5308d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 531751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner /// getMemoryOperandNo - The function returns the MCInst operand # for the 532751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner /// first field of the memory operand. If the instruction doesn't have a 533751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner /// memory operand, this returns -1. 534751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner /// 535751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner /// Note that this ignores tied operands. If there is a tied register which 536751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only 537751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner /// counted as one operand. 538751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner /// 539751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner static inline int getMemoryOperandNo(uint64_t TSFlags) { 540751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner switch (TSFlags & X86II::FormMask) { 541751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRMInitReg: assert(0 && "FIXME: Remove this form"); 542751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner default: assert(0 && "Unknown FormMask value in getMemoryOperandNo!"); 543751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::Pseudo: 544751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::RawFrm: 545751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::AddRegFrm: 546751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRMDestReg: 547751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRMSrcReg: 54840cc3f8783a4e426a0d439bb2b070b5c072b5947Chris Lattner case X86II::RawFrmImm8: 54959f8a6a66621f7c6f45b838e48fbf210af9d1fb5Chris Lattner case X86II::RawFrmImm16: 550751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner return -1; 551751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRMDestMem: 552751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner return 0; 553751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRMSrcMem: { 554229e4523f2f12929defa09ac4ef9f3652f21f1ecJoerg Sonnenberger bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 555751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner unsigned FirstMemOp = 1; 556751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner if (HasVEX_4V) 557751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV). 5588d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 559751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner // FIXME: Maybe lea should have its own form? This is a horrible hack. 560751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner //if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r || 561751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner // Opcode == X86::LEA16r || Opcode == X86::LEA32r) 562751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner return FirstMemOp; 563751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner } 564751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRM0r: case X86II::MRM1r: 565751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRM2r: case X86II::MRM3r: 566751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRM4r: case X86II::MRM5r: 567751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRM6r: case X86II::MRM7r: 568751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner return -1; 569751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRM0m: case X86II::MRM1m: 570751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRM2m: case X86II::MRM3m: 571751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRM4m: case X86II::MRM5m: 572751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRM6m: case X86II::MRM7m: 573751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner return 0; 574751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRM_C1: 575751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRM_C2: 576751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRM_C3: 577751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRM_C4: 578751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRM_C8: 579751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRM_C9: 580751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRM_E8: 581751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRM_F0: 582751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRM_F8: 583751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner case X86II::MRM_F9: 58487ca0e077d91b96a765b3b24cadfa8891026a33aRafael Espindola case X86II::MRM_D0: 58587ca0e077d91b96a765b3b24cadfa8891026a33aRafael Espindola case X86II::MRM_D1: 586751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner return -1; 587751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner } 588751e1123cecc4b5c2a86849bb39de317b396c303Chris Lattner } 5899d17740295838f94120646ef619b2e187f2d71bdChris Lattner} 5909d17740295838f94120646ef619b2e187f2d71bdChris Lattner 5911c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikovinline static bool isScale(const MachineOperand &MO) { 592d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman return MO.isImm() && 5931c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikov (MO.getImm() == 1 || MO.getImm() == 2 || 5941c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikov MO.getImm() == 4 || MO.getImm() == 8); 5951c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikov} 5961c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikov 597094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindolainline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { 598d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MI->getOperand(Op).isFI()) return true; 5991c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikov return Op+4 <= MI->getNumOperands() && 600d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 601d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI->getOperand(Op+2).isReg() && 602d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman (MI->getOperand(Op+3).isImm() || 603d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI->getOperand(Op+3).isGlobal() || 604d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI->getOperand(Op+3).isCPI() || 605d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI->getOperand(Op+3).isJTI()); 6061c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikov} 6071c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikov 608094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindolainline static bool isMem(const MachineInstr *MI, unsigned Op) { 609094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindola if (MI->getOperand(Op).isFI()) return true; 610094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindola return Op+5 <= MI->getNumOperands() && 611094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindola MI->getOperand(Op+4).isReg() && 612094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindola isLeaMem(MI, Op); 613094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindola} 614094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindola 615641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerclass X86InstrInfo : public TargetInstrInfoImpl { 616aa3c1410b427909da350f2b5e8d4ec3db62a3618Evan Cheng X86TargetMachine &TM; 617726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner const X86RegisterInfo RI; 6188d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 61943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 62043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// RegOp2MemOpTable2 - Load / store folding opcode maps. 62143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// 62245a1cb26a3b92c3c1bec0db9d67449c17b43c8fdChris Lattner DenseMap<unsigned, std::pair<unsigned,unsigned> > RegOp2MemOpTable2Addr; 62345a1cb26a3b92c3c1bec0db9d67449c17b43c8fdChris Lattner DenseMap<unsigned, std::pair<unsigned,unsigned> > RegOp2MemOpTable0; 62445a1cb26a3b92c3c1bec0db9d67449c17b43c8fdChris Lattner DenseMap<unsigned, std::pair<unsigned,unsigned> > RegOp2MemOpTable1; 62545a1cb26a3b92c3c1bec0db9d67449c17b43c8fdChris Lattner DenseMap<unsigned, std::pair<unsigned,unsigned> > RegOp2MemOpTable2; 6268d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 62743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// MemOp2RegOpTable - Load / store unfolding opcode map. 62843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// 62945a1cb26a3b92c3c1bec0db9d67449c17b43c8fdChris Lattner DenseMap<unsigned, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 630352aa503faee6c58e9cdb5054cc5ec1d90c696b4Jakob Stoklund Olesen 631726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattnerpublic: 632950a4c40b823cd4f09dc71be635229246dfd6cacDan Gohman explicit X86InstrInfo(X86TargetMachine &tm); 633726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 6343501feab811c86c9659248a4875fc31a3165f84dChris Lattner /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 635726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner /// such, whenever a client has an instance of instruction info, it should 636726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner /// always be able to get register info as well (through this method). 637726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner /// 638c9f5f3f64f896d0a8c8fa35a1dd98bc57b8960f6Dan Gohman virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 639726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 6407da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 6417da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// extension instruction. That is, it's like a copy where it's legal for the 6427da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 6437da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// true, then it's expected the pre-extension value is available as a subreg 6447da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// of the result register. This also returns the sub-register index in 6457da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// SubIdx. 6467da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng virtual bool isCoalescableExtInstr(const MachineInstr &MI, 6477da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng unsigned &SrcReg, unsigned &DstReg, 6487da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng unsigned &SubIdx) const; 649a5a81d70720a4ce6ac7538927c2a874b0dfa8bd2Evan Cheng 650cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 651dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 652dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// stack locations as well. This uses a heuristic so it isn't 653dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// reliable for correctness. 654dda3978d7877d2d60390833c73ed24857295e89cDavid Greene unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 655dda3978d7877d2d60390833c73ed24857295e89cDavid Greene int &FrameIndex) const; 656b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene 657b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// hasLoadFromStackSlot - If the specified machine instruction has 658b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// a load from a stack slot, return true along with the FrameIndex 65929dbf50b180bb3342af84ff042a3ff06405c5071David Greene /// of the loaded stack slot and the machine mem operand containing 66029dbf50b180bb3342af84ff042a3ff06405c5071David Greene /// the reference. If not, return false. Unlike 661b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// isLoadFromStackSlot, this returns true for any instructions that 662b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// loads from the stack. This is a hint only and may not catch all 663b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// cases. 66429dbf50b180bb3342af84ff042a3ff06405c5071David Greene bool hasLoadFromStackSlot(const MachineInstr *MI, 66529dbf50b180bb3342af84ff042a3ff06405c5071David Greene const MachineMemOperand *&MMO, 66629dbf50b180bb3342af84ff042a3ff06405c5071David Greene int &FrameIndex) const; 667b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene 668cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; 669dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 670dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// stack locations as well. This uses a heuristic so it isn't 671dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// reliable for correctness. 672dda3978d7877d2d60390833c73ed24857295e89cDavid Greene unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 673dda3978d7877d2d60390833c73ed24857295e89cDavid Greene int &FrameIndex) const; 674ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng 675b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// hasStoreToStackSlot - If the specified machine instruction has a 676b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// store to a stack slot, return true along with the FrameIndex of 67729dbf50b180bb3342af84ff042a3ff06405c5071David Greene /// the loaded stack slot and the machine mem operand containing the 67829dbf50b180bb3342af84ff042a3ff06405c5071David Greene /// reference. If not, return false. Unlike isStoreToStackSlot, 67929dbf50b180bb3342af84ff042a3ff06405c5071David Greene /// this returns true for any instructions that loads from the 68029dbf50b180bb3342af84ff042a3ff06405c5071David Greene /// stack. This is a hint only and may not catch all cases. 68129dbf50b180bb3342af84ff042a3ff06405c5071David Greene bool hasStoreToStackSlot(const MachineInstr *MI, 68229dbf50b180bb3342af84ff042a3ff06405c5071David Greene const MachineMemOperand *&MMO, 68329dbf50b180bb3342af84ff042a3ff06405c5071David Greene int &FrameIndex) const; 684b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene 6853731bc026cc6c4fb7deb7ac67e2c3be0c22498beDan Gohman bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 6863731bc026cc6c4fb7deb7ac67e2c3be0c22498beDan Gohman AliasAnalysis *AA) const; 687ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 688378445303b10b092a898a75131141a8259cff50bEvan Cheng unsigned DestReg, unsigned SubIdx, 689d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 6909edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const; 691ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng 692bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// convertToThreeAddress - This method must be implemented by targets that 693bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 694bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// may be able to convert a two-address instruction into a true 695bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// three-address instruction on demand. This allows the X86 target (for 696bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// example) to convert ADD and SHL instructions into LEA instructions if they 697bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// would require register copies due to two-addressness. 698bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// 699bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// This method returns a null pointer if the transformation cannot be 700bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// performed, otherwise it returns the new instruction. 701bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// 702ba59a1e453e110f7b84233f07613f9c5d9a39b87Evan Cheng virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 703ba59a1e453e110f7b84233f07613f9c5d9a39b87Evan Cheng MachineBasicBlock::iterator &MBBI, 704f660c171c838793b87b7e58e91609cecf256378dOwen Anderson LiveVariables *LV) const; 705bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner 70641e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner /// commuteInstruction - We have a few instructions that must be hacked on to 70741e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner /// commute them. 70841e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner /// 70958dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 71041e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner 7117fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner // Branch analysis. 712318093b6f8d21ac8eab34573b0526984895fe941Dale Johannesen virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 7137fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 7147fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner MachineBasicBlock *&FBB, 715dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng SmallVectorImpl<MachineOperand> &Cond, 716dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng bool AllowModify) const; 7176ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Cheng virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 7186ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Cheng virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 7196ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Cheng MachineBasicBlock *FBB, 7203bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 7213bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const; 722320bdcbfe2691021702085f718db1617b1d4df49Jakob Stoklund Olesen virtual void copyPhysReg(MachineBasicBlock &MBB, 723320bdcbfe2691021702085f718db1617b1d4df49Jakob Stoklund Olesen MachineBasicBlock::iterator MI, DebugLoc DL, 724320bdcbfe2691021702085f718db1617b1d4df49Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 725320bdcbfe2691021702085f718db1617b1d4df49Jakob Stoklund Olesen bool KillSrc) const; 726f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 727f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MI, 728f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned SrcReg, bool isKill, int FrameIndex, 729746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 730746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const; 731f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 732f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 733f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineOperand> &Addr, 734f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC, 73591e69c37153eb7d8cd149d9c2484c3115027b90fDan Gohman MachineInstr::mmo_iterator MMOBegin, 73691e69c37153eb7d8cd149d9c2484c3115027b90fDan Gohman MachineInstr::mmo_iterator MMOEnd, 737f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) const; 738f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 739f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 740f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MI, 741f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned DestReg, int FrameIndex, 742746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 743746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const; 744f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 745f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 746f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineOperand> &Addr, 747f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC, 74891e69c37153eb7d8cd149d9c2484c3115027b90fDan Gohman MachineInstr::mmo_iterator MMOBegin, 74991e69c37153eb7d8cd149d9c2484c3115027b90fDan Gohman MachineInstr::mmo_iterator MMOEnd, 750f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) const; 751962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng virtual 752962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 7538601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, uint64_t Offset, 754962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng const MDNode *MDPtr, 755962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng DebugLoc DL) const; 756962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng 75743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// foldMemoryOperand - If this target supports it, fold a load or store of 75843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// the specified stack slot into the specified machine instruction for the 75943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// specified operand(s). If this is possible, the target should perform the 76043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// folding and return true, otherwise it should return false. If it folds 76143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// the instruction, it is likely that the MachineInstruction the iterator 76243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// references has been changed. 763c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 764c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 765c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 766c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman int FrameIndex) const; 76743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 76843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// foldMemoryOperand - Same as the previous version except it allows folding 76943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// of any load and store from / to any address, not just from a specific 77043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// stack slot. 771c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 772c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 773c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 774c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* LoadMI) const; 77543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 77643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// canFoldMemoryOperand - Returns true if the specified load / store is 77743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// folding is possible. 7788e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman virtual bool canFoldMemoryOperand(const MachineInstr*, 7798e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman const SmallVectorImpl<unsigned> &) const; 78043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 78143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// unfoldMemoryOperand - Separate a single instruction which folded a load or 78243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// a store or a load and a store into two or more instruction. If this is 78343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// possible, returns true as well as the new instructions by reference. 78443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 78543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 78643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) const; 78743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 78843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 78943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson SmallVectorImpl<SDNode*> &NewNodes) const; 79043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 79143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 79243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// instruction after load / store are unfolded from an instruction of the 79343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// specified opcode. It returns zero if the specified unfolding is not 7940115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman /// possible. If LoadRegIndex is non-null, it is filled in with the operand 7950115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman /// index of the operand which will hold the register holding the loaded 7960115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman /// value. 79743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 7980115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman bool UnfoldLoad, bool UnfoldStore, 7990115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman unsigned *LoadRegIndex = 0) const; 8008d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 80196dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 80296dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// to determine if two loads are loading from the same base address. It 80396dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// should only return true if the base pointers are the same and the 80496dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// only differences between the two addresses are the offset. It also returns 80596dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// the offsets by reference. 80696dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 80796dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng int64_t &Offset1, int64_t &Offset2) const; 80896dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng 80996dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 8107a2bdde0a0eebcd2125055e0eacaca040f0b766cChris Lattner /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 81196dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// be scheduled togther. On some targets if two loads are loading from 81296dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// addresses in the same cache line, it's better if they are scheduled 81396dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// together. This function takes two integers that represent the load offsets 81496dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// from the common base address. It returns true if it decides it's desirable 81596dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// to schedule the two loads together. "NumLoads" is the number of loads that 81696dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// have already been scheduled after Load1. 81796dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 81896dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng int64_t Offset1, int64_t Offset2, 81996dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng unsigned NumLoads) const; 82096dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng 821ee9eb411fffddbb8fe70418c05946a131889b487Chris Lattner virtual void getNoopForMachoTarget(MCInst &NopInst) const; 822ee9eb411fffddbb8fe70418c05946a131889b487Chris Lattner 82344eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson virtual 82444eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 82541e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner 8264350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 8274350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng /// instruction that defines the specified register class. 8284350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 82923066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng 83052e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray static bool isX86_64NonExtLowByteReg(unsigned reg) { 83152e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray return (reg == X86::SPL || reg == X86::BPL || 83252e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray reg == X86::SIL || reg == X86::DIL); 83352e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray } 8348d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 83539a612e6f9e63806af410a0ab0d81895391e4c79Chris Lattner static bool isX86_64ExtendedReg(const MachineOperand &MO) { 83639a612e6f9e63806af410a0ab0d81895391e4c79Chris Lattner if (!MO.isReg()) return false; 83739a612e6f9e63806af410a0ab0d81895391e4c79Chris Lattner return isX86_64ExtendedReg(MO.getReg()); 83839a612e6f9e63806af410a0ab0d81895391e4c79Chris Lattner } 83952e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray 84039a612e6f9e63806af410a0ab0d81895391e4c79Chris Lattner /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or 84139a612e6f9e63806af410a0ab0d81895391e4c79Chris Lattner /// higher) register? e.g. r8, xmm8, xmm13, etc. 84239a612e6f9e63806af410a0ab0d81895391e4c79Chris Lattner static bool isX86_64ExtendedReg(unsigned RegNo); 84339a612e6f9e63806af410a0ab0d81895391e4c79Chris Lattner 84457c3dac0df7ac1b53ae7c0e5d2adc459fc7bd37cDan Gohman /// getGlobalBaseReg - Return a virtual register initialized with the 84557c3dac0df7ac1b53ae7c0e5d2adc459fc7bd37cDan Gohman /// the global base register value. Output instructions required to 84657c3dac0df7ac1b53ae7c0e5d2adc459fc7bd37cDan Gohman /// initialize the register in the function entry block, if necessary. 8478b746969baee26237e4c52de9862d06795eabcdaDan Gohman /// 84857c3dac0df7ac1b53ae7c0e5d2adc459fc7bd37cDan Gohman unsigned getGlobalBaseReg(MachineFunction *MF) const; 8498b746969baee26237e4c52de9862d06795eabcdaDan Gohman 850e4b94b4efb9a4670f25a5a80dd3b97f9583de202Jakob Stoklund Olesen /// GetSSEDomain - Return the SSE execution domain of MI as the first element, 851e4b94b4efb9a4670f25a5a80dd3b97f9583de202Jakob Stoklund Olesen /// and a bitmask of possible arguments to SetSSEDomain ase the second. 852e4b94b4efb9a4670f25a5a80dd3b97f9583de202Jakob Stoklund Olesen std::pair<uint16_t, uint16_t> GetSSEDomain(const MachineInstr *MI) const; 853e4b94b4efb9a4670f25a5a80dd3b97f9583de202Jakob Stoklund Olesen 854e4b94b4efb9a4670f25a5a80dd3b97f9583de202Jakob Stoklund Olesen /// SetSSEDomain - Set the SSEDomain of MI. 855e4b94b4efb9a4670f25a5a80dd3b97f9583de202Jakob Stoklund Olesen void SetSSEDomain(MachineInstr *MI, unsigned Domain) const; 856352aa503faee6c58e9cdb5054cc5ec1d90c696b4Jakob Stoklund Olesen 857beac75da3784929aee9f0357fc5cd76d49d6c3d7Chris Lattner MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 858beac75da3784929aee9f0357fc5cd76d49d6c3d7Chris Lattner MachineInstr* MI, 859beac75da3784929aee9f0357fc5cd76d49d6c3d7Chris Lattner unsigned OpNum, 860beac75da3784929aee9f0357fc5cd76d49d6c3d7Chris Lattner const SmallVectorImpl<MachineOperand> &MOs, 861beac75da3784929aee9f0357fc5cd76d49d6c3d7Chris Lattner unsigned Size, unsigned Alignment) const; 8622312842de0c641107dd04d7e056d02491cc781caEvan Cheng 863e0ef509aeb47b396cf1bdc170ca4f468f799719fAndrew Trick bool isHighLatencyDef(int opc) const; 864e0ef509aeb47b396cf1bdc170ca4f468f799719fAndrew Trick 8652312842de0c641107dd04d7e056d02491cc781caEvan Cheng bool hasHighOperandLatency(const InstrItineraryData *ItinData, 8662312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineRegisterInfo *MRI, 8672312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 8682312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const; 8698d4a4225135f1f4647e675902359b64cc21af7efAndrew Trick 87043dbe05279b753aabda571d9c83eaeb36987001aOwen Andersonprivate: 871656e51454ac70f5d500565fd33c883f6dea549f2Evan Cheng MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc, 872656e51454ac70f5d500565fd33c883f6dea549f2Evan Cheng MachineFunction::iterator &MFI, 873656e51454ac70f5d500565fd33c883f6dea549f2Evan Cheng MachineBasicBlock::iterator &MBBI, 874656e51454ac70f5d500565fd33c883f6dea549f2Evan Cheng LiveVariables *LV) const; 875656e51454ac70f5d500565fd33c883f6dea549f2Evan Cheng 876b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// isFrameOperand - Return true and the FrameIndex if the specified 877b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// operand and follow operands form a reference to the stack frame. 878b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene bool isFrameOperand(const MachineInstr *MI, unsigned int Op, 879b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene int &FrameIndex) const; 880726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner}; 881726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 882d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 883d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 884726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#endif 885