X86InstrInfo.h revision 07de40629f73fb018a2a7f0a5bbd1ee4defe95fd
1//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86INSTRUCTIONINFO_H 15#define X86INSTRUCTIONINFO_H 16 17#include "llvm/Target/TargetInstrInfo.h" 18#include "X86.h" 19#include "X86RegisterInfo.h" 20#include "llvm/ADT/DenseMap.h" 21 22namespace llvm { 23 class X86RegisterInfo; 24 class X86TargetMachine; 25 26namespace X86 { 27 // X86 specific condition code. These correspond to X86_*_COND in 28 // X86InstrInfo.td. They must be kept in synch. 29 enum CondCode { 30 COND_A = 0, 31 COND_AE = 1, 32 COND_B = 2, 33 COND_BE = 3, 34 COND_E = 4, 35 COND_G = 5, 36 COND_GE = 6, 37 COND_L = 7, 38 COND_LE = 8, 39 COND_NE = 9, 40 COND_NO = 10, 41 COND_NP = 11, 42 COND_NS = 12, 43 COND_O = 13, 44 COND_P = 14, 45 COND_S = 15, 46 47 // Artificial condition codes. These are used by AnalyzeBranch 48 // to indicate a block terminated with two conditional branches to 49 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 50 // which can't be represented on x86 with a single condition. These 51 // are never used in MachineInstrs. 52 COND_NE_OR_P, 53 COND_NP_OR_E, 54 55 COND_INVALID 56 }; 57 58 // Turn condition code into conditional branch opcode. 59 unsigned GetCondBranchFromCond(CondCode CC); 60 61 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 62 /// e.g. turning COND_E to COND_NE. 63 CondCode GetOppositeBranchCondition(X86::CondCode CC); 64 65} 66 67/// X86II - This namespace holds all of the target specific flags that 68/// instruction info tracks. 69/// 70namespace X86II { 71 /// Target Operand Flag enum. 72 enum TOF { 73 //===------------------------------------------------------------------===// 74 // X86 Specific MachineOperand flags. 75 76 MO_NO_FLAG, 77 78 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 79 /// relocation of: 80 /// SYMBOL_LABEL + [. - PICBASELABEL] 81 MO_GOT_ABSOLUTE_ADDRESS, 82 83 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 84 /// immediate should get the value of the symbol minus the PIC base label: 85 /// SYMBOL_LABEL - PICBASELABEL 86 MO_PIC_BASE_OFFSET, 87 88 /// MO_GOT - On a symbol operand this indicates that the immediate is the 89 /// offset to the GOT entry for the symbol name from the base of the GOT. 90 /// 91 /// See the X86-64 ELF ABI supplement for more details. 92 /// SYMBOL_LABEL @GOT 93 MO_GOT, 94 95 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 96 /// the offset to the location of the symbol name from the base of the GOT. 97 /// 98 /// See the X86-64 ELF ABI supplement for more details. 99 /// SYMBOL_LABEL @GOTOFF 100 MO_GOTOFF, 101 102 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 103 /// offset to the GOT entry for the symbol name from the current code 104 /// location. 105 /// 106 /// See the X86-64 ELF ABI supplement for more details. 107 /// SYMBOL_LABEL @GOTPCREL 108 MO_GOTPCREL, 109 110 /// MO_PLT - On a symbol operand this indicates that the immediate is 111 /// offset to the PLT entry of symbol name from the current code location. 112 /// 113 /// See the X86-64 ELF ABI supplement for more details. 114 /// SYMBOL_LABEL @PLT 115 MO_PLT, 116 117 /// MO_TLSGD - On a symbol operand this indicates that the immediate is 118 /// some TLS offset. 119 /// 120 /// See 'ELF Handling for Thread-Local Storage' for more details. 121 /// SYMBOL_LABEL @TLSGD 122 MO_TLSGD, 123 124 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 125 /// some TLS offset. 126 /// 127 /// See 'ELF Handling for Thread-Local Storage' for more details. 128 /// SYMBOL_LABEL @GOTTPOFF 129 MO_GOTTPOFF, 130 131 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 132 /// some TLS offset. 133 /// 134 /// See 'ELF Handling for Thread-Local Storage' for more details. 135 /// SYMBOL_LABEL @INDNTPOFF 136 MO_INDNTPOFF, 137 138 /// MO_TPOFF - On a symbol operand this indicates that the immediate is 139 /// some TLS offset. 140 /// 141 /// See 'ELF Handling for Thread-Local Storage' for more details. 142 /// SYMBOL_LABEL @TPOFF 143 MO_TPOFF, 144 145 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 146 /// some TLS offset. 147 /// 148 /// See 'ELF Handling for Thread-Local Storage' for more details. 149 /// SYMBOL_LABEL @NTPOFF 150 MO_NTPOFF, 151 152 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 153 /// reference is actually to the "__imp_FOO" symbol. This is used for 154 /// dllimport linkage on windows. 155 MO_DLLIMPORT, 156 157 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the 158 /// reference is actually to the "FOO$stub" symbol. This is used for calls 159 /// and jumps to external functions on Tiger and before. 160 MO_DARWIN_STUB, 161 162 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 163 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 164 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 165 MO_DARWIN_NONLAZY, 166 167 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 168 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 169 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 170 MO_DARWIN_NONLAZY_PIC_BASE, 171 172 /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this 173 /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE", 174 /// which is a PIC-base-relative reference to a hidden dyld lazy pointer 175 /// stub. 176 MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, 177 178 /// MO_TLVP - On a symbol operand this indicates that the immediate is 179 /// some TLS offset. 180 /// 181 /// This is the TLS offset for the Darwin TLS mechanism. 182 MO_TLVP, 183 184 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate 185 /// is some TLS offset from the picbase. 186 /// 187 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode. 188 MO_TLVP_PIC_BASE 189 }; 190} 191 192/// isGlobalStubReference - Return true if the specified TargetFlag operand is 193/// a reference to a stub for a global, not the global itself. 194inline static bool isGlobalStubReference(unsigned char TargetFlag) { 195 switch (TargetFlag) { 196 case X86II::MO_DLLIMPORT: // dllimport stub. 197 case X86II::MO_GOTPCREL: // rip-relative GOT reference. 198 case X86II::MO_GOT: // normal GOT reference. 199 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. 200 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. 201 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref. 202 return true; 203 default: 204 return false; 205 } 206} 207 208/// isGlobalRelativeToPICBase - Return true if the specified global value 209/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this 210/// is true, the addressing mode has the PIC base register added in (e.g. EBX). 211inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { 212 switch (TargetFlag) { 213 case X86II::MO_GOTOFF: // isPICStyleGOT: local global. 214 case X86II::MO_GOT: // isPICStyleGOT: other global. 215 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. 216 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. 217 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global. 218 case X86II::MO_TLVP: // ??? Pretty sure.. 219 return true; 220 default: 221 return false; 222 } 223} 224 225/// X86II - This namespace holds all of the target specific flags that 226/// instruction info tracks. 227/// 228namespace X86II { 229 enum { 230 //===------------------------------------------------------------------===// 231 // Instruction encodings. These are the standard/most common forms for X86 232 // instructions. 233 // 234 235 // PseudoFrm - This represents an instruction that is a pseudo instruction 236 // or one that has not been implemented yet. It is illegal to code generate 237 // it, but tolerated for intermediate implementation stages. 238 Pseudo = 0, 239 240 /// Raw - This form is for instructions that don't have any operands, so 241 /// they are just a fixed opcode value, like 'leave'. 242 RawFrm = 1, 243 244 /// AddRegFrm - This form is used for instructions like 'push r32' that have 245 /// their one register operand added to their opcode. 246 AddRegFrm = 2, 247 248 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 249 /// to specify a destination, which in this case is a register. 250 /// 251 MRMDestReg = 3, 252 253 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 254 /// to specify a destination, which in this case is memory. 255 /// 256 MRMDestMem = 4, 257 258 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 259 /// to specify a source, which in this case is a register. 260 /// 261 MRMSrcReg = 5, 262 263 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 264 /// to specify a source, which in this case is memory. 265 /// 266 MRMSrcMem = 6, 267 268 /// MRM[0-7][rm] - These forms are used to represent instructions that use 269 /// a Mod/RM byte, and use the middle field to hold extended opcode 270 /// information. In the intel manual these are represented as /0, /1, ... 271 /// 272 273 // First, instructions that operate on a register r/m operand... 274 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 275 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 276 277 // Next, instructions that operate on a memory r/m operand... 278 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 279 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 280 281 // MRMInitReg - This form is used for instructions whose source and 282 // destinations are the same register. 283 MRMInitReg = 32, 284 285 //// MRM_C1 - A mod/rm byte of exactly 0xC1. 286 MRM_C1 = 33, 287 MRM_C2 = 34, 288 MRM_C3 = 35, 289 MRM_C4 = 36, 290 MRM_C8 = 37, 291 MRM_C9 = 38, 292 MRM_E8 = 39, 293 MRM_F0 = 40, 294 MRM_F8 = 41, 295 MRM_F9 = 42, 296 297 FormMask = 63, 298 299 //===------------------------------------------------------------------===// 300 // Actual flags... 301 302 // OpSize - Set if this instruction requires an operand size prefix (0x66), 303 // which most often indicates that the instruction operates on 16 bit data 304 // instead of 32 bit data. 305 OpSize = 1 << 6, 306 307 // AsSize - Set if this instruction requires an operand size prefix (0x67), 308 // which most often indicates that the instruction address 16 bit address 309 // instead of 32 bit address (or 32 bit address in 64 bit mode). 310 AdSize = 1 << 7, 311 312 //===------------------------------------------------------------------===// 313 // Op0Mask - There are several prefix bytes that are used to form two byte 314 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 315 // used to obtain the setting of this field. If no bits in this field is 316 // set, there is no prefix byte for obtaining a multibyte opcode. 317 // 318 Op0Shift = 8, 319 Op0Mask = 0xF << Op0Shift, 320 321 // TB - TwoByte - Set if this instruction has a two byte opcode, which 322 // starts with a 0x0F byte before the real opcode. 323 TB = 1 << Op0Shift, 324 325 // REP - The 0xF3 prefix byte indicating repetition of the following 326 // instruction. 327 REP = 2 << Op0Shift, 328 329 // D8-DF - These escape opcodes are used by the floating point unit. These 330 // values must remain sequential. 331 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 332 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 333 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 334 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 335 336 // XS, XD - These prefix codes are for single and double precision scalar 337 // floating point operations performed in the SSE registers. 338 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 339 340 // T8, TA - Prefix after the 0x0F prefix. 341 T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 342 343 // TF - Prefix before and after 0x0F 344 TF = 15 << Op0Shift, 345 346 //===------------------------------------------------------------------===// 347 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 348 // They are used to specify GPRs and SSE registers, 64-bit operand size, 349 // etc. We only cares about REX.W and REX.R bits and only the former is 350 // statically determined. 351 // 352 REXShift = 12, 353 REX_W = 1 << REXShift, 354 355 //===------------------------------------------------------------------===// 356 // This three-bit field describes the size of an immediate operand. Zero is 357 // unused so that we can tell if we forgot to set a value. 358 ImmShift = 13, 359 ImmMask = 7 << ImmShift, 360 Imm8 = 1 << ImmShift, 361 Imm8PCRel = 2 << ImmShift, 362 Imm16 = 3 << ImmShift, 363 Imm32 = 4 << ImmShift, 364 Imm32PCRel = 5 << ImmShift, 365 Imm64 = 6 << ImmShift, 366 367 //===------------------------------------------------------------------===// 368 // FP Instruction Classification... Zero is non-fp instruction. 369 370 // FPTypeMask - Mask for all of the FP types... 371 FPTypeShift = 16, 372 FPTypeMask = 7 << FPTypeShift, 373 374 // NotFP - The default, set for instructions that do not use FP registers. 375 NotFP = 0 << FPTypeShift, 376 377 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 378 ZeroArgFP = 1 << FPTypeShift, 379 380 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 381 OneArgFP = 2 << FPTypeShift, 382 383 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 384 // result back to ST(0). For example, fcos, fsqrt, etc. 385 // 386 OneArgFPRW = 3 << FPTypeShift, 387 388 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 389 // explicit argument, storing the result to either ST(0) or the implicit 390 // argument. For example: fadd, fsub, fmul, etc... 391 TwoArgFP = 4 << FPTypeShift, 392 393 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 394 // explicit argument, but have no destination. Example: fucom, fucomi, ... 395 CompareFP = 5 << FPTypeShift, 396 397 // CondMovFP - "2 operand" floating point conditional move instructions. 398 CondMovFP = 6 << FPTypeShift, 399 400 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 401 SpecialFP = 7 << FPTypeShift, 402 403 // Lock prefix 404 LOCKShift = 19, 405 LOCK = 1 << LOCKShift, 406 407 // Segment override prefixes. Currently we just need ability to address 408 // stuff in gs and fs segments. 409 SegOvrShift = 20, 410 SegOvrMask = 3 << SegOvrShift, 411 FS = 1 << SegOvrShift, 412 GS = 2 << SegOvrShift, 413 414 // Execution domain for SSE instructions in bits 22, 23. 415 // 0 in bits 22-23 means normal, non-SSE instruction. 416 SSEDomainShift = 22, 417 418 OpcodeShift = 24, 419 OpcodeMask = 0xFF << OpcodeShift 420 421 }; 422 423 // FIXME: The enum opcode space is over and more bits are needed. Anywhere 424 // those enums below are used, TSFlags must be shifted right by 32 first. 425 enum { 426 //===------------------------------------------------------------------===// 427 // VEX - A prefix used by AVX instructions 428 VEX = 1, 429 430 // VEX_W is has a opcode specific functionality, but is used in the same 431 // way as REX_W is for regular SSE instructions. 432 VEX_W = 1 << 1, 433 434 // VEX_4V is used to specify an additional AVX/SSE register. Several 2 435 // address instructions in SSE are represented as 3 address ones in AVX 436 // and the additional register is encoded in VEX_VVVV prefix. 437 VEX_4V = 1 << 2, 438 439 // VEX_I8IMM specifies that the last register used in a AVX instruction, 440 // must be encoded in the i8 immediate field. This usually happens in 441 // instructions with 4 operands. 442 VEX_I8IMM = 1 << 3 443 }; 444 445 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 446 // specified machine instruction. 447 // 448 static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { 449 return TSFlags >> X86II::OpcodeShift; 450 } 451 452 static inline bool hasImm(uint64_t TSFlags) { 453 return (TSFlags & X86II::ImmMask) != 0; 454 } 455 456 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field 457 /// of the specified instruction. 458 static inline unsigned getSizeOfImm(uint64_t TSFlags) { 459 switch (TSFlags & X86II::ImmMask) { 460 default: assert(0 && "Unknown immediate size"); 461 case X86II::Imm8: 462 case X86II::Imm8PCRel: return 1; 463 case X86II::Imm16: return 2; 464 case X86II::Imm32: 465 case X86II::Imm32PCRel: return 4; 466 case X86II::Imm64: return 8; 467 } 468 } 469 470 /// isImmPCRel - Return true if the immediate of the specified instruction's 471 /// TSFlags indicates that it is pc relative. 472 static inline unsigned isImmPCRel(uint64_t TSFlags) { 473 switch (TSFlags & X86II::ImmMask) { 474 default: assert(0 && "Unknown immediate size"); 475 case X86II::Imm8PCRel: 476 case X86II::Imm32PCRel: 477 return true; 478 case X86II::Imm8: 479 case X86II::Imm16: 480 case X86II::Imm32: 481 case X86II::Imm64: 482 return false; 483 } 484 } 485} 486 487const int X86AddrNumOperands = 5; 488 489inline static bool isScale(const MachineOperand &MO) { 490 return MO.isImm() && 491 (MO.getImm() == 1 || MO.getImm() == 2 || 492 MO.getImm() == 4 || MO.getImm() == 8); 493} 494 495inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { 496 if (MI->getOperand(Op).isFI()) return true; 497 return Op+4 <= MI->getNumOperands() && 498 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 499 MI->getOperand(Op+2).isReg() && 500 (MI->getOperand(Op+3).isImm() || 501 MI->getOperand(Op+3).isGlobal() || 502 MI->getOperand(Op+3).isCPI() || 503 MI->getOperand(Op+3).isJTI()); 504} 505 506inline static bool isMem(const MachineInstr *MI, unsigned Op) { 507 if (MI->getOperand(Op).isFI()) return true; 508 return Op+5 <= MI->getNumOperands() && 509 MI->getOperand(Op+4).isReg() && 510 isLeaMem(MI, Op); 511} 512 513class X86InstrInfo : public TargetInstrInfoImpl { 514 X86TargetMachine &TM; 515 const X86RegisterInfo RI; 516 517 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 518 /// RegOp2MemOpTable2 - Load / store folding opcode maps. 519 /// 520 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2Addr; 521 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable0; 522 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable1; 523 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2; 524 525 /// MemOp2RegOpTable - Load / store unfolding opcode map. 526 /// 527 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 528 529public: 530 explicit X86InstrInfo(X86TargetMachine &tm); 531 532 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 533 /// such, whenever a client has an instance of instruction info, it should 534 /// always be able to get register info as well (through this method). 535 /// 536 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 537 538 /// Return true if the instruction is a register to register move and return 539 /// the source and dest operands and their sub-register indices by reference. 540 virtual bool isMoveInstr(const MachineInstr &MI, 541 unsigned &SrcReg, unsigned &DstReg, 542 unsigned &SrcSubIdx, unsigned &DstSubIdx) const; 543 544 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 545 /// extension instruction. That is, it's like a copy where it's legal for the 546 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 547 /// true, then it's expected the pre-extension value is available as a subreg 548 /// of the result register. This also returns the sub-register index in 549 /// SubIdx. 550 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 551 unsigned &SrcReg, unsigned &DstReg, 552 unsigned &SubIdx) const; 553 554 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 555 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 556 /// stack locations as well. This uses a heuristic so it isn't 557 /// reliable for correctness. 558 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 559 int &FrameIndex) const; 560 561 /// hasLoadFromStackSlot - If the specified machine instruction has 562 /// a load from a stack slot, return true along with the FrameIndex 563 /// of the loaded stack slot and the machine mem operand containing 564 /// the reference. If not, return false. Unlike 565 /// isLoadFromStackSlot, this returns true for any instructions that 566 /// loads from the stack. This is a hint only and may not catch all 567 /// cases. 568 bool hasLoadFromStackSlot(const MachineInstr *MI, 569 const MachineMemOperand *&MMO, 570 int &FrameIndex) const; 571 572 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; 573 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 574 /// stack locations as well. This uses a heuristic so it isn't 575 /// reliable for correctness. 576 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 577 int &FrameIndex) const; 578 579 /// hasStoreToStackSlot - If the specified machine instruction has a 580 /// store to a stack slot, return true along with the FrameIndex of 581 /// the loaded stack slot and the machine mem operand containing the 582 /// reference. If not, return false. Unlike isStoreToStackSlot, 583 /// this returns true for any instructions that loads from the 584 /// stack. This is a hint only and may not catch all cases. 585 bool hasStoreToStackSlot(const MachineInstr *MI, 586 const MachineMemOperand *&MMO, 587 int &FrameIndex) const; 588 589 bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 590 AliasAnalysis *AA) const; 591 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 592 unsigned DestReg, unsigned SubIdx, 593 const MachineInstr *Orig, 594 const TargetRegisterInfo &TRI) const; 595 596 /// convertToThreeAddress - This method must be implemented by targets that 597 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 598 /// may be able to convert a two-address instruction into a true 599 /// three-address instruction on demand. This allows the X86 target (for 600 /// example) to convert ADD and SHL instructions into LEA instructions if they 601 /// would require register copies due to two-addressness. 602 /// 603 /// This method returns a null pointer if the transformation cannot be 604 /// performed, otherwise it returns the new instruction. 605 /// 606 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 607 MachineBasicBlock::iterator &MBBI, 608 LiveVariables *LV) const; 609 610 /// commuteInstruction - We have a few instructions that must be hacked on to 611 /// commute them. 612 /// 613 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 614 615 // Branch analysis. 616 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 617 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 618 MachineBasicBlock *&FBB, 619 SmallVectorImpl<MachineOperand> &Cond, 620 bool AllowModify) const; 621 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 622 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 623 MachineBasicBlock *FBB, 624 const SmallVectorImpl<MachineOperand> &Cond, 625 DebugLoc DL) const; 626 virtual bool copyRegToReg(MachineBasicBlock &MBB, 627 MachineBasicBlock::iterator MI, 628 unsigned DestReg, unsigned SrcReg, 629 const TargetRegisterClass *DestRC, 630 const TargetRegisterClass *SrcRC, 631 DebugLoc DL) const; 632 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 633 MachineBasicBlock::iterator MI, 634 unsigned SrcReg, bool isKill, int FrameIndex, 635 const TargetRegisterClass *RC, 636 const TargetRegisterInfo *TRI) const; 637 638 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 639 SmallVectorImpl<MachineOperand> &Addr, 640 const TargetRegisterClass *RC, 641 MachineInstr::mmo_iterator MMOBegin, 642 MachineInstr::mmo_iterator MMOEnd, 643 SmallVectorImpl<MachineInstr*> &NewMIs) const; 644 645 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 646 MachineBasicBlock::iterator MI, 647 unsigned DestReg, int FrameIndex, 648 const TargetRegisterClass *RC, 649 const TargetRegisterInfo *TRI) const; 650 651 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 652 SmallVectorImpl<MachineOperand> &Addr, 653 const TargetRegisterClass *RC, 654 MachineInstr::mmo_iterator MMOBegin, 655 MachineInstr::mmo_iterator MMOEnd, 656 SmallVectorImpl<MachineInstr*> &NewMIs) const; 657 658 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 659 MachineBasicBlock::iterator MI, 660 const std::vector<CalleeSavedInfo> &CSI, 661 const TargetRegisterInfo *TRI) const; 662 663 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 664 MachineBasicBlock::iterator MI, 665 const std::vector<CalleeSavedInfo> &CSI, 666 const TargetRegisterInfo *TRI) const; 667 668 virtual 669 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 670 int FrameIx, uint64_t Offset, 671 const MDNode *MDPtr, 672 DebugLoc DL) const; 673 674 /// foldMemoryOperand - If this target supports it, fold a load or store of 675 /// the specified stack slot into the specified machine instruction for the 676 /// specified operand(s). If this is possible, the target should perform the 677 /// folding and return true, otherwise it should return false. If it folds 678 /// the instruction, it is likely that the MachineInstruction the iterator 679 /// references has been changed. 680 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 681 MachineInstr* MI, 682 const SmallVectorImpl<unsigned> &Ops, 683 int FrameIndex) const; 684 685 /// foldMemoryOperand - Same as the previous version except it allows folding 686 /// of any load and store from / to any address, not just from a specific 687 /// stack slot. 688 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 689 MachineInstr* MI, 690 const SmallVectorImpl<unsigned> &Ops, 691 MachineInstr* LoadMI) const; 692 693 /// canFoldMemoryOperand - Returns true if the specified load / store is 694 /// folding is possible. 695 virtual bool canFoldMemoryOperand(const MachineInstr*, 696 const SmallVectorImpl<unsigned> &) const; 697 698 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 699 /// a store or a load and a store into two or more instruction. If this is 700 /// possible, returns true as well as the new instructions by reference. 701 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 702 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 703 SmallVectorImpl<MachineInstr*> &NewMIs) const; 704 705 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 706 SmallVectorImpl<SDNode*> &NewNodes) const; 707 708 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 709 /// instruction after load / store are unfolded from an instruction of the 710 /// specified opcode. It returns zero if the specified unfolding is not 711 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 712 /// index of the operand which will hold the register holding the loaded 713 /// value. 714 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 715 bool UnfoldLoad, bool UnfoldStore, 716 unsigned *LoadRegIndex = 0) const; 717 718 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 719 /// to determine if two loads are loading from the same base address. It 720 /// should only return true if the base pointers are the same and the 721 /// only differences between the two addresses are the offset. It also returns 722 /// the offsets by reference. 723 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 724 int64_t &Offset1, int64_t &Offset2) const; 725 726 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 727 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 728 /// be scheduled togther. On some targets if two loads are loading from 729 /// addresses in the same cache line, it's better if they are scheduled 730 /// together. This function takes two integers that represent the load offsets 731 /// from the common base address. It returns true if it decides it's desirable 732 /// to schedule the two loads together. "NumLoads" is the number of loads that 733 /// have already been scheduled after Load1. 734 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 735 int64_t Offset1, int64_t Offset2, 736 unsigned NumLoads) const; 737 738 virtual void getNoopForMachoTarget(MCInst &NopInst) const; 739 740 virtual 741 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 742 743 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 744 /// instruction that defines the specified register class. 745 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 746 747 static bool isX86_64NonExtLowByteReg(unsigned reg) { 748 return (reg == X86::SPL || reg == X86::BPL || 749 reg == X86::SIL || reg == X86::DIL); 750 } 751 752 static bool isX86_64ExtendedReg(const MachineOperand &MO) { 753 if (!MO.isReg()) return false; 754 return isX86_64ExtendedReg(MO.getReg()); 755 } 756 static unsigned determineREX(const MachineInstr &MI); 757 758 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or 759 /// higher) register? e.g. r8, xmm8, xmm13, etc. 760 static bool isX86_64ExtendedReg(unsigned RegNo); 761 762 /// GetInstSize - Returns the size of the specified MachineInstr. 763 /// 764 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 765 766 /// getGlobalBaseReg - Return a virtual register initialized with the 767 /// the global base register value. Output instructions required to 768 /// initialize the register in the function entry block, if necessary. 769 /// 770 unsigned getGlobalBaseReg(MachineFunction *MF) const; 771 772 /// GetSSEDomain - Return the SSE execution domain of MI as the first element, 773 /// and a bitmask of possible arguments to SetSSEDomain ase the second. 774 std::pair<uint16_t, uint16_t> GetSSEDomain(const MachineInstr *MI) const; 775 776 /// SetSSEDomain - Set the SSEDomain of MI. 777 void SetSSEDomain(MachineInstr *MI, unsigned Domain) const; 778 779private: 780 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc, 781 MachineFunction::iterator &MFI, 782 MachineBasicBlock::iterator &MBBI, 783 LiveVariables *LV) const; 784 785 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 786 MachineInstr* MI, 787 unsigned OpNum, 788 const SmallVectorImpl<MachineOperand> &MOs, 789 unsigned Size, unsigned Alignment) const; 790 791 /// isFrameOperand - Return true and the FrameIndex if the specified 792 /// operand and follow operands form a reference to the stack frame. 793 bool isFrameOperand(const MachineInstr *MI, unsigned int Op, 794 int &FrameIndex) const; 795}; 796 797} // End llvm namespace 798 799#endif 800