X86InstrInfo.h revision 0ef73f3e2975d240cb6a7fa62c438e7c928df043 
1//===- X86InstructionInfo.h - X86 Instruction Information ---------*-C++-*-===//
2//
3// This file contains the X86 implementation of the MachineInstrInfo class.
4//
5//===----------------------------------------------------------------------===//
6
7#ifndef X86INSTRUCTIONINFO_H
8#define X86INSTRUCTIONINFO_H
9
10#include "llvm/Target/MachineInstrInfo.h"
11#include "X86RegisterInfo.h"
12
13/// X86II - This namespace holds all of the target specific flags that
14/// instruction info tracks.
15///
16namespace X86II {
17  enum {
18    //===------------------------------------------------------------------===//
19    // Instruction types.  These are the standard/most common forms for X86
20    // instructions.
21    //
22
23    // PseudoFrm - This represents an instruction that is a pseudo instruction
24    // or one that has not been implemented yet.  It is illegal to code generate
25    // it, but tolerated for intermediate implementation stages.
26    Pseudo         = 0,
27
28    /// Raw - This form is for instructions that don't have any operands, so
29    /// they are just a fixed opcode value, like 'leave'.
30    RawFrm         = 1,
31
32    /// AddRegFrm - This form is used for instructions like 'push r32' that have
33    /// their one register operand added to their opcode.
34    AddRegFrm      = 2,
35
36    /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
37    /// to specify a destination, which in this case is a register.
38    ///
39    MRMDestReg     = 3,
40
41    /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
42    /// to specify a destination, which in this case is memory.
43    ///
44    MRMDestMem     = 4,
45
46    /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
47    /// to specify a source, which in this case is a register.
48    ///
49    MRMSrcReg      = 5,
50
51    /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
52    /// to specify a source, which in this case is memory.
53    ///
54    MRMSrcMem      = 6,
55
56    /// MRMS[0-7][rm] - These forms are used to represent instructions that use
57    /// a Mod/RM byte, and use the middle field to hold extended opcode
58    /// information.  In the intel manual these are represented as /0, /1, ...
59    ///
60
61    // First, instructions that operate on a register r/m operand...
62    MRMS0r = 16,  MRMS1r = 17,  MRMS2r = 18,  MRMS3r = 19, // Format /0 /1 /2 /3
63    MRMS4r = 20,  MRMS5r = 21,  MRMS6r = 22,  MRMS7r = 23, // Format /4 /5 /6 /7
64
65    // Next, instructions that operate on a memory r/m operand...
66    MRMS0m = 24,  MRMS1m = 25,  MRMS2m = 26,  MRMS3m = 27, // Format /0 /1 /2 /3
67    MRMS4m = 28,  MRMS5m = 29,  MRMS6m = 30,  MRMS7m = 31, // Format /4 /5 /6 /7
68
69    FormMask       = 31,
70
71    //===------------------------------------------------------------------===//
72    // Actual flags...
73
74    /// Void - Set if this instruction produces no value
75    Void        = 1 << 5,
76
77    // OpSize - Set if this instruction requires an operand size prefix (0x66),
78    // which most often indicates that the instruction operates on 16 bit data
79    // instead of 32 bit data.
80    OpSize      = 1 << 6,
81
82    // Op0Mask - There are several prefix bytes that are used to form two byte
83    // opcodes.  These are currently 0x0F, and 0xD8-0xDF.  This mask is used to
84    // obtain the setting of this field.  If no bits in this field is set, there
85    // is no prefix byte for obtaining a multibyte opcode.
86    //
87    Op0Mask     = 0xF << 7,
88
89    // TB - TwoByte - Set if this instruction has a two byte opcode, which
90    // starts with a 0x0F byte before the real opcode.
91    TB          = 1 << 7,
92
93    // D8-DF - These escape opcodes are used by the floating point unit.  These
94    // values must remain sequential.
95    D8 = 2 << 7,   D9 = 3 << 7,   DA = 4 << 7,   DB = 5 << 7,
96    DC = 6 << 7,   DD = 7 << 7,   DE = 8 << 7,   DF = 9 << 7,
97
98    // This three-bit field describes the size of a memory operand.  Zero is
99    // unused so that we can tell if we forgot to set a value.
100    Arg8     = 1 << 11,
101    Arg16    = 2 << 11,
102    Arg32    = 3 << 11,
103    ArgF32   = 4 << 11,
104    ArgF64   = 5 << 11,
105    ArgF80   = 6 << 11,
106    ArgMask  = 7 << 11,
107
108    // Bits 14 -> 31 are unused
109  };
110}
111
112class X86InstrInfo : public MachineInstrInfo {
113  const X86RegisterInfo RI;
114public:
115  X86InstrInfo();
116
117  /// getRegisterInfo - MachineInstrInfo is a superset of MRegister info.  As
118  /// such, whenever a client has an instance of instruction info, it should
119  /// always be able to get register info as well (through this method).
120  ///
121  virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
122
123  /// print - Print out an x86 instruction in intel syntax
124  ///
125  virtual void print(const MachineInstr *MI, std::ostream &O,
126                     const TargetMachine &TM) const;
127
128  // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
129  // specified opcode number.
130  //
131  unsigned char getBaseOpcodeFor(unsigned Opcode) const;
132};
133
134
135#endif
136