X86InstrInfo.h revision 19f2ffce4598c4c70f32eed7c6740b43185200b1
1bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com// 3bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com// The LLVM Compiler Infrastructure 4bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com// 5bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com// This file was developed by the LLVM research group and is distributed under 6bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com// the University of Illinois Open Source License. See LICENSE.TXT for details. 7bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com// 8bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com//===----------------------------------------------------------------------===// 9bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com// 10bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com// This file contains the X86 implementation of the TargetInstrInfo class. 118f6884aab8aecd7657cf3f9cdbc682f0deca29c5tfarina@chromium.org// 12bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com//===----------------------------------------------------------------------===// 13bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 14bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com#ifndef X86INSTRUCTIONINFO_H 15bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com#define X86INSTRUCTIONINFO_H 16bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 17bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com#include "llvm/Target/TargetInstrInfo.h" 18bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com#include "X86RegisterInfo.h" 194e23068b374023d43c4c725138d523721d975892bsalomon@google.com 20bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.comnamespace llvm { 21bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com class X86RegisterInfo; 22bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com class X86TargetMachine; 23bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 24bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.comnamespace X86 { 25bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // X86 specific condition code. These correspond to X86_*_COND in 26bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // X86InstrInfo.td. They must be kept in synch. 27bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com enum CondCode { 28bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com COND_A = 0, 29bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com COND_AE = 1, 30bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com COND_B = 2, 31bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com COND_BE = 3, 32bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com COND_E = 4, 33bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com COND_G = 5, 34bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com COND_GE = 6, 35bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com COND_L = 7, 36bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com COND_LE = 8, 37bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com COND_NE = 9, 38bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com COND_NO = 10, 39515dcd36032997ce335daa0163c6d67e851bcad1commit-bot@chromium.org COND_NP = 11, 40dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com COND_NS = 12, 41bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com COND_O = 13, 42bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com COND_P = 14, 43bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com COND_S = 15, 44bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com COND_INVALID 45bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com }; 46bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 47bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // Turn condition code into conditional branch opcode. 48bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com unsigned GetCondBranchFromCond(CondCode CC); 49bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 50bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com /// GetOppositeBranchCondition - Return the inverse of the specified cond, 51bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com /// e.g. turning COND_E to COND_NE. 52bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com CondCode GetOppositeBranchCondition(X86::CondCode CC); 53bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 54bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com} 55bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 56bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com/// X86II - This namespace holds all of the target specific flags that 57bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com/// instruction info tracks. 58bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com/// 59bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.comnamespace X86II { 60bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com enum { 61bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com //===------------------------------------------------------------------===// 62bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // Instruction types. These are the standard/most common forms for X86 63bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // instructions. 64bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // 65bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 66bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // PseudoFrm - This represents an instruction that is a pseudo instruction 67bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // or one that has not been implemented yet. It is illegal to code generate 68bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // it, but tolerated for intermediate implementation stages. 69bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com Pseudo = 0, 70bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 71bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com /// Raw - This form is for instructions that don't have any operands, so 72bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com /// they are just a fixed opcode value, like 'leave'. 73bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com RawFrm = 1, 74bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 75bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com /// AddRegFrm - This form is used for instructions like 'push r32' that have 7649f085dddff10473b6ebf832a974288300224e60bsalomon /// their one register operand added to their opcode. 77bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com AddRegFrm = 2, 78bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 79bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 80bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com /// to specify a destination, which in this case is a register. 8149f085dddff10473b6ebf832a974288300224e60bsalomon /// 82bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com MRMDestReg = 3, 83bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 84bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 85bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com /// to specify a destination, which in this case is memory. 86bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com /// 87bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com MRMDestMem = 4, 88bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 89bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 90bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com /// to specify a source, which in this case is a register. 91bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com /// 92bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com MRMSrcReg = 5, 93bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 94bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 95bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com /// to specify a source, which in this case is memory. 96bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com /// 97dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com MRMSrcMem = 6, 98dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com 99dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com /// MRM[0-7][rm] - These forms are used to represent instructions that use 100dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com /// a Mod/RM byte, and use the middle field to hold extended opcode 101dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com /// information. In the intel manual these are represented as /0, /1, ... 102dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com /// 103dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com 104dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com // First, instructions that operate on a register r/m operand... 105dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 106dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 107dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com 108dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com // Next, instructions that operate on a memory r/m operand... 109dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 110dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 111dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com 112dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com // MRMInitReg - This form is used for instructions whose source and 113dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com // destinations are the same register. 114dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com MRMInitReg = 32, 115dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com 116dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com FormMask = 63, 11749f085dddff10473b6ebf832a974288300224e60bsalomon 118dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com //===------------------------------------------------------------------===// 119dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com // Actual flags... 120bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 121bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // OpSize - Set if this instruction requires an operand size prefix (0x66), 122bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // which most often indicates that the instruction operates on 16 bit data 123bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // instead of 32 bit data. 124bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com OpSize = 1 << 6, 125e0e7cfe44bb9d66d76120a79e5275c294bacaa22commit-bot@chromium.org 126bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // AsSize - Set if this instruction requires an operand size prefix (0x67), 127bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // which most often indicates that the instruction address 16 bit address 128bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // instead of 32 bit address (or 32 bit address in 64 bit mode). 129bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com AdSize = 1 << 7, 130bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 131bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com //===------------------------------------------------------------------===// 132bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // Op0Mask - There are several prefix bytes that are used to form two byte 133bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 134bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // used to obtain the setting of this field. If no bits in this field is 135bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // set, there is no prefix byte for obtaining a multibyte opcode. 1364e23068b374023d43c4c725138d523721d975892bsalomon@google.com // 137bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com Op0Shift = 8, 138bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com Op0Mask = 0xF << Op0Shift, 139bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 140bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // TB - TwoByte - Set if this instruction has a two byte opcode, which 141bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // starts with a 0x0F byte before the real opcode. 142bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com TB = 1 << Op0Shift, 143bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 144bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // REP - The 0xF3 prefix byte indicating repetition of the following 145bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // instruction. 146bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com REP = 2 << Op0Shift, 147bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 148bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // D8-DF - These escape opcodes are used by the floating point unit. These 149bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // values must remain sequential. 150bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 151bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com DA = 5 << Op0Shift, DB = 6 << Op0Shift, 1524e23068b374023d43c4c725138d523721d975892bsalomon@google.com DC = 7 << Op0Shift, DD = 8 << Op0Shift, 153bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com DE = 9 << Op0Shift, DF = 10 << Op0Shift, 154bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 155bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // XS, XD - These prefix codes are for single and double precision scalar 156bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // floating point operations performed in the SSE registers. 157bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com XD = 11 << Op0Shift, XS = 12 << Op0Shift, 158bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 159bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com //===------------------------------------------------------------------===// 160bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 161bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // They are used to specify GPRs and SSE registers, 64-bit operand size, 162bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // etc. We only cares about REX.W and REX.R bits and only the former is 163e659c2e820de0b8d12d81247ed4430022ded0a90skia.committer@gmail.com // statically determined. 164dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com // 165dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com REXShift = 12, 166dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com REX_W = 1 << REXShift, 167dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com 168dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com //===------------------------------------------------------------------===// 169dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com // This three-bit field describes the size of an immediate operand. Zero is 170e659c2e820de0b8d12d81247ed4430022ded0a90skia.committer@gmail.com // unused so that we can tell if we forgot to set a value. 171dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com ImmShift = 13, 172dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com ImmMask = 7 << ImmShift, 173dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com Imm8 = 1 << ImmShift, 174bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com Imm16 = 2 << ImmShift, 175ebce0301082cda9dc3e3298f6db91d46fe66298bbsalomon@google.com Imm32 = 3 << ImmShift, 176ebce0301082cda9dc3e3298f6db91d46fe66298bbsalomon@google.com Imm64 = 4 << ImmShift, 177bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 178ebce0301082cda9dc3e3298f6db91d46fe66298bbsalomon@google.com //===------------------------------------------------------------------===// 1794e23068b374023d43c4c725138d523721d975892bsalomon@google.com // FP Instruction Classification... Zero is non-fp instruction. 180bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 181bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // FPTypeMask - Mask for all of the FP types... 182dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com FPTypeShift = 16, 183bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com FPTypeMask = 7 << FPTypeShift, 184bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 185bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // NotFP - The default, set for instructions that do not use FP registers. 186bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com NotFP = 0 << FPTypeShift, 187bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 188bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 189bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com ZeroArgFP = 1 << FPTypeShift, 1904e23068b374023d43c4c725138d523721d975892bsalomon@google.com 191bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 192bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com OneArgFP = 2 << FPTypeShift, 193bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 194bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 195bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // result back to ST(0). For example, fcos, fsqrt, etc. 196bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // 1974e23068b374023d43c4c725138d523721d975892bsalomon@google.com OneArgFPRW = 3 << FPTypeShift, 198bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 199bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 200bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // explicit argument, storing the result to either ST(0) or the implicit 201bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // argument. For example: fadd, fsub, fmul, etc... 202dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com TwoArgFP = 4 << FPTypeShift, 203bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 204bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 205bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // explicit argument, but have no destination. Example: fucom, fucomi, ... 206dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com CompareFP = 5 << FPTypeShift, 207dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com 208dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com // CondMovFP - "2 operand" floating point conditional move instructions. 209dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com CondMovFP = 6 << FPTypeShift, 210dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com 211dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 212dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com SpecialFP = 7 << FPTypeShift, 213dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com 214dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com // Bits 19 -> 23 are unused 215dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com OpcodeShift = 24, 216dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com OpcodeMask = 0xFF << OpcodeShift 217dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com }; 218dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com} 219dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com 220dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.comclass X86InstrInfo : public TargetInstrInfo { 221dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com X86TargetMachine &TM; 222dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com const X86RegisterInfo RI; 223dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.compublic: 224dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com X86InstrInfo(X86TargetMachine &tm); 225dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com 226dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 227dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com /// such, whenever a client has an instance of instruction info, it should 228dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com /// always be able to get register info as well (through this method). 229dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com /// 230dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com virtual const MRegisterInfo &getRegisterInfo() const { return RI; } 23149f085dddff10473b6ebf832a974288300224e60bsalomon 232dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com // Return true if the instruction is a register to register move and 233dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com // leave the source and dest operands in the passed parameters. 234dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com // 235dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, 236dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com unsigned& destReg) const; 237dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; 238dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; 239dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com 24049f085dddff10473b6ebf832a974288300224e60bsalomon /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL 241dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com /// instruction if it has one. This is used by codegen passes that update 242dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com /// DWARF line number info as they modify the code. 24349f085dddff10473b6ebf832a974288300224e60bsalomon virtual unsigned getDWARF_LABELOpcode() const; 244dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com 245dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com /// convertToThreeAddress - This method must be implemented by targets that 246dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 247dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com /// may be able to convert a two-address instruction into a true 248dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com /// three-address instruction on demand. This allows the X86 target (for 249dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com /// example) to convert ADD and SHL instructions into LEA instructions if they 250dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com /// would require register copies due to two-addressness. 251dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com /// 25249f085dddff10473b6ebf832a974288300224e60bsalomon /// This method returns a null pointer if the transformation cannot be 253dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com /// performed, otherwise it returns the new instruction. 254dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com /// 25549f085dddff10473b6ebf832a974288300224e60bsalomon virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 256dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com MachineBasicBlock::iterator &MBBI, 257dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com LiveVariables &LV) const; 258dd3f7a9efefc486833d564527367155eb93691d4bsalomon@google.com 259e659c2e820de0b8d12d81247ed4430022ded0a90skia.committer@gmail.com /// commuteInstruction - We have a few instructions that must be hacked on to 260bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com /// commute them. 261bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com /// 262bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 263bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 264bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // Branch analysis. 265bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 266bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com MachineBasicBlock *&FBB, 267e659c2e820de0b8d12d81247ed4430022ded0a90skia.committer@gmail.com std::vector<MachineOperand> &Cond) const; 268bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com virtual void RemoveBranch(MachineBasicBlock &MBB) const; 269bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 270bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com MachineBasicBlock *FBB, 271bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com const std::vector<MachineOperand> &Cond) const; 272bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; 273bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const; 274bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 275bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com const TargetRegisterClass *getPointerRegClass() const; 276bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 277bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 278bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com // specified opcode number. 27949f085dddff10473b6ebf832a974288300224e60bsalomon // 280bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com unsigned char getBaseOpcodeFor(const TargetInstrDescriptor *TID) const { 281bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com return TID->TSFlags >> X86II::OpcodeShift; 28249f085dddff10473b6ebf832a974288300224e60bsalomon } 283bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com}; 284bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 285bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com} // End llvm namespace 286bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com 287bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com#endif 288bbe52908a23d5eada9a0e5c58e620b35a2770c10bsalomon@google.com