X86InstrInfo.h revision 2df3f58a0b3937f2cbd76d3417d2905ca86cf8fa
15821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 25821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 35821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// The LLVM Compiler Infrastructure 45821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 55821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file is distributed under the University of Illinois Open Source 65821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// License. See LICENSE.TXT for details. 75821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 85821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 95821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file contains the X86 implementation of the TargetInstrInfo class. 115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 12868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)//===----------------------------------------------------------------------===// 135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 142a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)#ifndef X86INSTRUCTIONINFO_H 155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#define X86INSTRUCTIONINFO_H 165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/Target/TargetInstrInfo.h" 185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "X86.h" 195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "X86RegisterInfo.h" 205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/ADT/DenseMap.h" 215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#define GET_INSTRINFO_HEADER 235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "X86GenInstrInfo.inc" 245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)namespace llvm { 265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) class X86RegisterInfo; 275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) class X86TargetMachine; 285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 292a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)namespace X86 { 305821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // X86 specific condition code. These correspond to X86_*_COND in 312a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // X86InstrInfo.td. They must be kept in synch. 325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) enum CondCode { 335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_A = 0, 345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_AE = 1, 355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_B = 2, 365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_BE = 3, 375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_E = 4, 385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_G = 5, 395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_GE = 6, 405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_L = 7, 415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_LE = 8, 422a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) COND_NE = 9, 435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_NO = 10, 441320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci COND_NP = 11, 452a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) COND_NS = 12, 465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_O = 13, 475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_P = 14, 485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_S = 15, 495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Artificial condition codes. These are used by AnalyzeBranch 515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // to indicate a block terminated with two conditional branches to 525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // which can't be represented on x86 with a single condition. These 545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // are never used in MachineInstrs. 555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_NE_OR_P, 565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_NP_OR_E, 57a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 585821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_INVALID 595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) }; 605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Turn condition code into conditional branch opcode. 625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned GetCondBranchFromCond(CondCode CC); 632a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 642a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// GetOppositeBranchCondition - Return the inverse of the specified cond, 655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// e.g. turning COND_E to COND_NE. 665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) CondCode GetOppositeBranchCondition(X86::CondCode CC); 675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} // end namespace X86; 685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// isGlobalStubReference - Return true if the specified TargetFlag operand is 715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// a reference to a stub for a global, not the global itself. 725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)inline static bool isGlobalStubReference(unsigned char TargetFlag) { 735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) switch (TargetFlag) { 745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case X86II::MO_DLLIMPORT: // dllimport stub. 755821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case X86II::MO_GOTPCREL: // rip-relative GOT reference. 765821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case X86II::MO_GOT: // normal GOT reference. 77f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. 78f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. 79f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref. 805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return true; 815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) default: 822a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return false; 835821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 845821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 852a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 865821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// isGlobalRelativeToPICBase - Return true if the specified global value 875821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this 885821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// is true, the addressing mode has the PIC base register added in (e.g. EBX). 895821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { 905821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) switch (TargetFlag) { 91 case X86II::MO_GOTOFF: // isPICStyleGOT: local global. 92 case X86II::MO_GOT: // isPICStyleGOT: other global. 93 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. 94 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. 95 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global. 96 case X86II::MO_TLVP: // ??? Pretty sure.. 97 return true; 98 default: 99 return false; 100 } 101} 102 103inline static bool isScale(const MachineOperand &MO) { 104 return MO.isImm() && 105 (MO.getImm() == 1 || MO.getImm() == 2 || 106 MO.getImm() == 4 || MO.getImm() == 8); 107} 108 109inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { 110 if (MI->getOperand(Op).isFI()) return true; 111 return Op+4 <= MI->getNumOperands() && 112 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 113 MI->getOperand(Op+2).isReg() && 114 (MI->getOperand(Op+3).isImm() || 115 MI->getOperand(Op+3).isGlobal() || 116 MI->getOperand(Op+3).isCPI() || 117 MI->getOperand(Op+3).isJTI()); 118} 119 120inline static bool isMem(const MachineInstr *MI, unsigned Op) { 121 if (MI->getOperand(Op).isFI()) return true; 122 return Op+5 <= MI->getNumOperands() && 123 MI->getOperand(Op+4).isReg() && 124 isLeaMem(MI, Op); 125} 126 127class X86InstrInfo : public X86GenInstrInfo { 128 X86TargetMachine &TM; 129 const X86RegisterInfo RI; 130 131 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 132 /// RegOp2MemOpTable2 - Load / store folding opcode maps. 133 /// 134 DenseMap<unsigned, std::pair<unsigned,unsigned> > RegOp2MemOpTable2Addr; 135 DenseMap<unsigned, std::pair<unsigned,unsigned> > RegOp2MemOpTable0; 136 DenseMap<unsigned, std::pair<unsigned,unsigned> > RegOp2MemOpTable1; 137 DenseMap<unsigned, std::pair<unsigned,unsigned> > RegOp2MemOpTable2; 138 139 /// MemOp2RegOpTable - Load / store unfolding opcode map. 140 /// 141 DenseMap<unsigned, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 142 143public: 144 explicit X86InstrInfo(X86TargetMachine &tm); 145 146 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 147 /// such, whenever a client has an instance of instruction info, it should 148 /// always be able to get register info as well (through this method). 149 /// 150 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 151 152 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 153 /// extension instruction. That is, it's like a copy where it's legal for the 154 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 155 /// true, then it's expected the pre-extension value is available as a subreg 156 /// of the result register. This also returns the sub-register index in 157 /// SubIdx. 158 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 159 unsigned &SrcReg, unsigned &DstReg, 160 unsigned &SubIdx) const; 161 162 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 163 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 164 /// stack locations as well. This uses a heuristic so it isn't 165 /// reliable for correctness. 166 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 167 int &FrameIndex) const; 168 169 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; 170 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 171 /// stack locations as well. This uses a heuristic so it isn't 172 /// reliable for correctness. 173 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 174 int &FrameIndex) const; 175 176 bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 177 AliasAnalysis *AA) const; 178 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 179 unsigned DestReg, unsigned SubIdx, 180 const MachineInstr *Orig, 181 const TargetRegisterInfo &TRI) const; 182 183 /// convertToThreeAddress - This method must be implemented by targets that 184 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 185 /// may be able to convert a two-address instruction into a true 186 /// three-address instruction on demand. This allows the X86 target (for 187 /// example) to convert ADD and SHL instructions into LEA instructions if they 188 /// would require register copies due to two-addressness. 189 /// 190 /// This method returns a null pointer if the transformation cannot be 191 /// performed, otherwise it returns the new instruction. 192 /// 193 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 194 MachineBasicBlock::iterator &MBBI, 195 LiveVariables *LV) const; 196 197 /// commuteInstruction - We have a few instructions that must be hacked on to 198 /// commute them. 199 /// 200 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 201 202 // Branch analysis. 203 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 204 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 205 MachineBasicBlock *&FBB, 206 SmallVectorImpl<MachineOperand> &Cond, 207 bool AllowModify) const; 208 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 209 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 210 MachineBasicBlock *FBB, 211 const SmallVectorImpl<MachineOperand> &Cond, 212 DebugLoc DL) const; 213 virtual void copyPhysReg(MachineBasicBlock &MBB, 214 MachineBasicBlock::iterator MI, DebugLoc DL, 215 unsigned DestReg, unsigned SrcReg, 216 bool KillSrc) const; 217 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 218 MachineBasicBlock::iterator MI, 219 unsigned SrcReg, bool isKill, int FrameIndex, 220 const TargetRegisterClass *RC, 221 const TargetRegisterInfo *TRI) const; 222 223 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 224 SmallVectorImpl<MachineOperand> &Addr, 225 const TargetRegisterClass *RC, 226 MachineInstr::mmo_iterator MMOBegin, 227 MachineInstr::mmo_iterator MMOEnd, 228 SmallVectorImpl<MachineInstr*> &NewMIs) const; 229 230 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 231 MachineBasicBlock::iterator MI, 232 unsigned DestReg, int FrameIndex, 233 const TargetRegisterClass *RC, 234 const TargetRegisterInfo *TRI) const; 235 236 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 237 SmallVectorImpl<MachineOperand> &Addr, 238 const TargetRegisterClass *RC, 239 MachineInstr::mmo_iterator MMOBegin, 240 MachineInstr::mmo_iterator MMOEnd, 241 SmallVectorImpl<MachineInstr*> &NewMIs) const; 242 virtual 243 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 244 int FrameIx, uint64_t Offset, 245 const MDNode *MDPtr, 246 DebugLoc DL) const; 247 248 /// foldMemoryOperand - If this target supports it, fold a load or store of 249 /// the specified stack slot into the specified machine instruction for the 250 /// specified operand(s). If this is possible, the target should perform the 251 /// folding and return true, otherwise it should return false. If it folds 252 /// the instruction, it is likely that the MachineInstruction the iterator 253 /// references has been changed. 254 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 255 MachineInstr* MI, 256 const SmallVectorImpl<unsigned> &Ops, 257 int FrameIndex) const; 258 259 /// foldMemoryOperand - Same as the previous version except it allows folding 260 /// of any load and store from / to any address, not just from a specific 261 /// stack slot. 262 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 263 MachineInstr* MI, 264 const SmallVectorImpl<unsigned> &Ops, 265 MachineInstr* LoadMI) const; 266 267 /// canFoldMemoryOperand - Returns true if the specified load / store is 268 /// folding is possible. 269 virtual bool canFoldMemoryOperand(const MachineInstr*, 270 const SmallVectorImpl<unsigned> &) const; 271 272 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 273 /// a store or a load and a store into two or more instruction. If this is 274 /// possible, returns true as well as the new instructions by reference. 275 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 276 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 277 SmallVectorImpl<MachineInstr*> &NewMIs) const; 278 279 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 280 SmallVectorImpl<SDNode*> &NewNodes) const; 281 282 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 283 /// instruction after load / store are unfolded from an instruction of the 284 /// specified opcode. It returns zero if the specified unfolding is not 285 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 286 /// index of the operand which will hold the register holding the loaded 287 /// value. 288 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 289 bool UnfoldLoad, bool UnfoldStore, 290 unsigned *LoadRegIndex = 0) const; 291 292 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 293 /// to determine if two loads are loading from the same base address. It 294 /// should only return true if the base pointers are the same and the 295 /// only differences between the two addresses are the offset. It also returns 296 /// the offsets by reference. 297 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 298 int64_t &Offset1, int64_t &Offset2) const; 299 300 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 301 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 302 /// be scheduled togther. On some targets if two loads are loading from 303 /// addresses in the same cache line, it's better if they are scheduled 304 /// together. This function takes two integers that represent the load offsets 305 /// from the common base address. It returns true if it decides it's desirable 306 /// to schedule the two loads together. "NumLoads" is the number of loads that 307 /// have already been scheduled after Load1. 308 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 309 int64_t Offset1, int64_t Offset2, 310 unsigned NumLoads) const; 311 312 virtual void getNoopForMachoTarget(MCInst &NopInst) const; 313 314 virtual 315 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 316 317 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 318 /// instruction that defines the specified register class. 319 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 320 321 static bool isX86_64ExtendedReg(const MachineOperand &MO) { 322 if (!MO.isReg()) return false; 323 return X86II::isX86_64ExtendedReg(MO.getReg()); 324 } 325 326 /// getGlobalBaseReg - Return a virtual register initialized with the 327 /// the global base register value. Output instructions required to 328 /// initialize the register in the function entry block, if necessary. 329 /// 330 unsigned getGlobalBaseReg(MachineFunction *MF) const; 331 332 /// GetSSEDomain - Return the SSE execution domain of MI as the first element, 333 /// and a bitmask of possible arguments to SetSSEDomain ase the second. 334 std::pair<uint16_t, uint16_t> GetSSEDomain(const MachineInstr *MI) const; 335 336 /// SetSSEDomain - Set the SSEDomain of MI. 337 void SetSSEDomain(MachineInstr *MI, unsigned Domain) const; 338 339 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 340 MachineInstr* MI, 341 unsigned OpNum, 342 const SmallVectorImpl<MachineOperand> &MOs, 343 unsigned Size, unsigned Alignment) const; 344 345 bool isHighLatencyDef(int opc) const; 346 347 bool hasHighOperandLatency(const InstrItineraryData *ItinData, 348 const MachineRegisterInfo *MRI, 349 const MachineInstr *DefMI, unsigned DefIdx, 350 const MachineInstr *UseMI, unsigned UseIdx) const; 351 352private: 353 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc, 354 MachineFunction::iterator &MFI, 355 MachineBasicBlock::iterator &MBBI, 356 LiveVariables *LV) const; 357 358 /// isFrameOperand - Return true and the FrameIndex if the specified 359 /// operand and follow operands form a reference to the stack frame. 360 bool isFrameOperand(const MachineInstr *MI, unsigned int Op, 361 int &FrameIndex) const; 362}; 363 364} // End llvm namespace 365 366#endif 367