X86InstrInfo.h revision 3fafd935607844085a23c012e2a8778fa97206a0
1//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86INSTRUCTIONINFO_H 15#define X86INSTRUCTIONINFO_H 16 17#include "llvm/Target/TargetInstrInfo.h" 18#include "X86.h" 19#include "X86RegisterInfo.h" 20#include "llvm/ADT/IndexedMap.h" 21#include "llvm/Target/TargetRegisterInfo.h" 22 23namespace llvm { 24 class X86RegisterInfo; 25 class X86TargetMachine; 26 27namespace X86 { 28 // X86 specific condition code. These correspond to X86_*_COND in 29 // X86InstrInfo.td. They must be kept in synch. 30 enum CondCode { 31 COND_A = 0, 32 COND_AE = 1, 33 COND_B = 2, 34 COND_BE = 3, 35 COND_E = 4, 36 COND_G = 5, 37 COND_GE = 6, 38 COND_L = 7, 39 COND_LE = 8, 40 COND_NE = 9, 41 COND_NO = 10, 42 COND_NP = 11, 43 COND_NS = 12, 44 COND_NC = 13, 45 COND_O = 14, 46 COND_P = 15, 47 COND_S = 16, 48 COND_C = 17, 49 50 // Artificial condition codes. These are used by AnalyzeBranch 51 // to indicate a block terminated with two conditional branches to 52 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 53 // which can't be represented on x86 with a single condition. These 54 // are never used in MachineInstrs. 55 COND_NE_OR_P, 56 COND_NP_OR_E, 57 58 COND_INVALID 59 }; 60 61 // Turn condition code into conditional branch opcode. 62 unsigned GetCondBranchFromCond(CondCode CC); 63 64 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 65 /// e.g. turning COND_E to COND_NE. 66 CondCode GetOppositeBranchCondition(X86::CondCode CC); 67 68} 69 70/// X86II - This namespace holds all of the target specific flags that 71/// instruction info tracks. 72/// 73namespace X86II { 74 enum { 75 //===------------------------------------------------------------------===// 76 // Instruction types. These are the standard/most common forms for X86 77 // instructions. 78 // 79 80 // PseudoFrm - This represents an instruction that is a pseudo instruction 81 // or one that has not been implemented yet. It is illegal to code generate 82 // it, but tolerated for intermediate implementation stages. 83 Pseudo = 0, 84 85 /// Raw - This form is for instructions that don't have any operands, so 86 /// they are just a fixed opcode value, like 'leave'. 87 RawFrm = 1, 88 89 /// AddRegFrm - This form is used for instructions like 'push r32' that have 90 /// their one register operand added to their opcode. 91 AddRegFrm = 2, 92 93 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 94 /// to specify a destination, which in this case is a register. 95 /// 96 MRMDestReg = 3, 97 98 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 99 /// to specify a destination, which in this case is memory. 100 /// 101 MRMDestMem = 4, 102 103 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 104 /// to specify a source, which in this case is a register. 105 /// 106 MRMSrcReg = 5, 107 108 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 109 /// to specify a source, which in this case is memory. 110 /// 111 MRMSrcMem = 6, 112 113 /// MRM[0-7][rm] - These forms are used to represent instructions that use 114 /// a Mod/RM byte, and use the middle field to hold extended opcode 115 /// information. In the intel manual these are represented as /0, /1, ... 116 /// 117 118 // First, instructions that operate on a register r/m operand... 119 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 120 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 121 122 // Next, instructions that operate on a memory r/m operand... 123 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 124 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 125 126 // MRMInitReg - This form is used for instructions whose source and 127 // destinations are the same register. 128 MRMInitReg = 32, 129 130 FormMask = 63, 131 132 //===------------------------------------------------------------------===// 133 // Actual flags... 134 135 // OpSize - Set if this instruction requires an operand size prefix (0x66), 136 // which most often indicates that the instruction operates on 16 bit data 137 // instead of 32 bit data. 138 OpSize = 1 << 6, 139 140 // AsSize - Set if this instruction requires an operand size prefix (0x67), 141 // which most often indicates that the instruction address 16 bit address 142 // instead of 32 bit address (or 32 bit address in 64 bit mode). 143 AdSize = 1 << 7, 144 145 //===------------------------------------------------------------------===// 146 // Op0Mask - There are several prefix bytes that are used to form two byte 147 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 148 // used to obtain the setting of this field. If no bits in this field is 149 // set, there is no prefix byte for obtaining a multibyte opcode. 150 // 151 Op0Shift = 8, 152 Op0Mask = 0xF << Op0Shift, 153 154 // TB - TwoByte - Set if this instruction has a two byte opcode, which 155 // starts with a 0x0F byte before the real opcode. 156 TB = 1 << Op0Shift, 157 158 // REP - The 0xF3 prefix byte indicating repetition of the following 159 // instruction. 160 REP = 2 << Op0Shift, 161 162 // D8-DF - These escape opcodes are used by the floating point unit. These 163 // values must remain sequential. 164 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 165 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 166 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 167 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 168 169 // XS, XD - These prefix codes are for single and double precision scalar 170 // floating point operations performed in the SSE registers. 171 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 172 173 // T8, TA - Prefix after the 0x0F prefix. 174 T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 175 176 //===------------------------------------------------------------------===// 177 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 178 // They are used to specify GPRs and SSE registers, 64-bit operand size, 179 // etc. We only cares about REX.W and REX.R bits and only the former is 180 // statically determined. 181 // 182 REXShift = 12, 183 REX_W = 1 << REXShift, 184 185 //===------------------------------------------------------------------===// 186 // This three-bit field describes the size of an immediate operand. Zero is 187 // unused so that we can tell if we forgot to set a value. 188 ImmShift = 13, 189 ImmMask = 7 << ImmShift, 190 Imm8 = 1 << ImmShift, 191 Imm16 = 2 << ImmShift, 192 Imm32 = 3 << ImmShift, 193 Imm64 = 4 << ImmShift, 194 195 //===------------------------------------------------------------------===// 196 // FP Instruction Classification... Zero is non-fp instruction. 197 198 // FPTypeMask - Mask for all of the FP types... 199 FPTypeShift = 16, 200 FPTypeMask = 7 << FPTypeShift, 201 202 // NotFP - The default, set for instructions that do not use FP registers. 203 NotFP = 0 << FPTypeShift, 204 205 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 206 ZeroArgFP = 1 << FPTypeShift, 207 208 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 209 OneArgFP = 2 << FPTypeShift, 210 211 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 212 // result back to ST(0). For example, fcos, fsqrt, etc. 213 // 214 OneArgFPRW = 3 << FPTypeShift, 215 216 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 217 // explicit argument, storing the result to either ST(0) or the implicit 218 // argument. For example: fadd, fsub, fmul, etc... 219 TwoArgFP = 4 << FPTypeShift, 220 221 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 222 // explicit argument, but have no destination. Example: fucom, fucomi, ... 223 CompareFP = 5 << FPTypeShift, 224 225 // CondMovFP - "2 operand" floating point conditional move instructions. 226 CondMovFP = 6 << FPTypeShift, 227 228 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 229 SpecialFP = 7 << FPTypeShift, 230 231 // Lock prefix 232 LOCKShift = 19, 233 LOCK = 1 << LOCKShift, 234 235 // Segment override prefixes. Currently we just need ability to address 236 // stuff in gs and fs segments. 237 SegOvrShift = 20, 238 SegOvrMask = 3 << SegOvrShift, 239 FS = 1 << SegOvrShift, 240 GS = 2 << SegOvrShift, 241 242 // Bits 22 -> 23 are unused 243 OpcodeShift = 24, 244 OpcodeMask = 0xFF << OpcodeShift 245 }; 246} 247 248inline static bool isScale(const MachineOperand &MO) { 249 return MO.isImm() && 250 (MO.getImm() == 1 || MO.getImm() == 2 || 251 MO.getImm() == 4 || MO.getImm() == 8); 252} 253 254inline static bool isMem(const MachineInstr *MI, unsigned Op) { 255 if (MI->getOperand(Op).isFI()) return true; 256 return Op+4 <= MI->getNumOperands() && 257 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 258 MI->getOperand(Op+2).isReg() && 259 (MI->getOperand(Op+3).isImm() || 260 MI->getOperand(Op+3).isGlobal() || 261 MI->getOperand(Op+3).isCPI() || 262 MI->getOperand(Op+3).isJTI()); 263} 264 265class X86InstrInfo : public TargetInstrInfoImpl { 266 X86TargetMachine &TM; 267 const X86RegisterInfo RI; 268 269 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 270 /// RegOp2MemOpTable2 - Load / store folding opcode maps. 271 /// 272 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr; 273 DenseMap<unsigned*, unsigned> RegOp2MemOpTable0; 274 DenseMap<unsigned*, unsigned> RegOp2MemOpTable1; 275 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2; 276 277 /// MemOp2RegOpTable - Load / store unfolding opcode map. 278 /// 279 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 280 281public: 282 explicit X86InstrInfo(X86TargetMachine &tm); 283 284 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 285 /// such, whenever a client has an instance of instruction info, it should 286 /// always be able to get register info as well (through this method). 287 /// 288 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 289 290 // Return true if the instruction is a register to register move and 291 // leave the source and dest operands in the passed parameters. 292 // 293 bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, 294 unsigned& destReg) const; 295 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 296 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; 297 298 bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const; 299 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 300 unsigned DestReg, const MachineInstr *Orig) const; 301 302 bool isInvariantLoad(const MachineInstr *MI) const; 303 304 /// convertToThreeAddress - This method must be implemented by targets that 305 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 306 /// may be able to convert a two-address instruction into a true 307 /// three-address instruction on demand. This allows the X86 target (for 308 /// example) to convert ADD and SHL instructions into LEA instructions if they 309 /// would require register copies due to two-addressness. 310 /// 311 /// This method returns a null pointer if the transformation cannot be 312 /// performed, otherwise it returns the new instruction. 313 /// 314 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 315 MachineBasicBlock::iterator &MBBI, 316 LiveVariables *LV) const; 317 318 /// commuteInstruction - We have a few instructions that must be hacked on to 319 /// commute them. 320 /// 321 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 322 323 // Branch analysis. 324 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 325 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 326 MachineBasicBlock *&FBB, 327 SmallVectorImpl<MachineOperand> &Cond) const; 328 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 329 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 330 MachineBasicBlock *FBB, 331 const SmallVectorImpl<MachineOperand> &Cond) const; 332 virtual bool copyRegToReg(MachineBasicBlock &MBB, 333 MachineBasicBlock::iterator MI, 334 unsigned DestReg, unsigned SrcReg, 335 const TargetRegisterClass *DestRC, 336 const TargetRegisterClass *SrcRC) const; 337 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 338 MachineBasicBlock::iterator MI, 339 unsigned SrcReg, bool isKill, int FrameIndex, 340 const TargetRegisterClass *RC) const; 341 342 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 343 SmallVectorImpl<MachineOperand> &Addr, 344 const TargetRegisterClass *RC, 345 SmallVectorImpl<MachineInstr*> &NewMIs) const; 346 347 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 348 MachineBasicBlock::iterator MI, 349 unsigned DestReg, int FrameIndex, 350 const TargetRegisterClass *RC) const; 351 352 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 353 SmallVectorImpl<MachineOperand> &Addr, 354 const TargetRegisterClass *RC, 355 SmallVectorImpl<MachineInstr*> &NewMIs) const; 356 357 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 358 MachineBasicBlock::iterator MI, 359 const std::vector<CalleeSavedInfo> &CSI) const; 360 361 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 362 MachineBasicBlock::iterator MI, 363 const std::vector<CalleeSavedInfo> &CSI) const; 364 365 /// foldMemoryOperand - If this target supports it, fold a load or store of 366 /// the specified stack slot into the specified machine instruction for the 367 /// specified operand(s). If this is possible, the target should perform the 368 /// folding and return true, otherwise it should return false. If it folds 369 /// the instruction, it is likely that the MachineInstruction the iterator 370 /// references has been changed. 371 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, 372 MachineInstr* MI, 373 const SmallVectorImpl<unsigned> &Ops, 374 int FrameIndex) const; 375 376 /// foldMemoryOperand - Same as the previous version except it allows folding 377 /// of any load and store from / to any address, not just from a specific 378 /// stack slot. 379 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, 380 MachineInstr* MI, 381 const SmallVectorImpl<unsigned> &Ops, 382 MachineInstr* LoadMI) const; 383 384 /// canFoldMemoryOperand - Returns true if the specified load / store is 385 /// folding is possible. 386 virtual bool canFoldMemoryOperand(const MachineInstr*, 387 const SmallVectorImpl<unsigned> &) const; 388 389 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 390 /// a store or a load and a store into two or more instruction. If this is 391 /// possible, returns true as well as the new instructions by reference. 392 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 393 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 394 SmallVectorImpl<MachineInstr*> &NewMIs) const; 395 396 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 397 SmallVectorImpl<SDNode*> &NewNodes) const; 398 399 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 400 /// instruction after load / store are unfolded from an instruction of the 401 /// specified opcode. It returns zero if the specified unfolding is not 402 /// possible. 403 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 404 bool UnfoldLoad, bool UnfoldStore) const; 405 406 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const; 407 virtual 408 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 409 410 /// IgnoreRegisterClassBarriers - Returns true if pre-register allocation 411 /// live interval splitting pass should ignore barriers of the specified 412 /// register class. 413 bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const; 414 415 const TargetRegisterClass *getPointerRegClass() const; 416 417 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 418 // specified machine instruction. 419 // 420 unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const { 421 return TID->TSFlags >> X86II::OpcodeShift; 422 } 423 unsigned char getBaseOpcodeFor(unsigned Opcode) const { 424 return getBaseOpcodeFor(&get(Opcode)); 425 } 426 427 static bool isX86_64NonExtLowByteReg(unsigned reg) { 428 return (reg == X86::SPL || reg == X86::BPL || 429 reg == X86::SIL || reg == X86::DIL); 430 } 431 432 static unsigned sizeOfImm(const TargetInstrDesc *Desc); 433 static bool isX86_64ExtendedReg(const MachineOperand &MO); 434 static unsigned determineREX(const MachineInstr &MI); 435 436 /// GetInstSize - Returns the size of the specified MachineInstr. 437 /// 438 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 439 440 /// getGlobalBaseReg - Return a virtual register initialized with the 441 /// the global base register value. Output instructions required to 442 /// initialize the register in the function entry block, if necessary. 443 /// 444 unsigned getGlobalBaseReg(MachineFunction *MF) const; 445 446private: 447 MachineInstr* foldMemoryOperand(MachineFunction &MF, 448 MachineInstr* MI, 449 unsigned OpNum, 450 const SmallVector<MachineOperand,4> &MOs) const; 451}; 452 453} // End llvm namespace 454 455#endif 456