X86InstrInfo.h revision 3feb0170a8d65984ce5c01a85e7dfd4005f8bb35
1//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86INSTRUCTIONINFO_H 15#define X86INSTRUCTIONINFO_H 16 17#include "llvm/Target/TargetInstrInfo.h" 18#include "X86RegisterInfo.h" 19#include "llvm/ADT/IndexedMap.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21 22namespace llvm { 23 class X86RegisterInfo; 24 class X86TargetMachine; 25 26namespace X86 { 27 // X86 specific condition code. These correspond to X86_*_COND in 28 // X86InstrInfo.td. They must be kept in synch. 29 enum CondCode { 30 COND_A = 0, 31 COND_AE = 1, 32 COND_B = 2, 33 COND_BE = 3, 34 COND_E = 4, 35 COND_G = 5, 36 COND_GE = 6, 37 COND_L = 7, 38 COND_LE = 8, 39 COND_NE = 9, 40 COND_NO = 10, 41 COND_NP = 11, 42 COND_NS = 12, 43 COND_O = 13, 44 COND_P = 14, 45 COND_S = 15, 46 COND_INVALID 47 }; 48 49 // X86 specific implict values used for subregister inserts. 50 // This can be used to model the fact that x86-64 by default 51 // inserts 32-bit values into 64-bit registers implicitly containing zeros. 52 enum ImplicitVal { 53 IMPL_VAL_UNDEF = 0, 54 IMPL_VAL_ZERO = 1 55 }; 56 57 // Turn condition code into conditional branch opcode. 58 unsigned GetCondBranchFromCond(CondCode CC); 59 60 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 61 /// e.g. turning COND_E to COND_NE. 62 CondCode GetOppositeBranchCondition(X86::CondCode CC); 63 64} 65 66/// X86II - This namespace holds all of the target specific flags that 67/// instruction info tracks. 68/// 69namespace X86II { 70 enum { 71 //===------------------------------------------------------------------===// 72 // Instruction types. These are the standard/most common forms for X86 73 // instructions. 74 // 75 76 // PseudoFrm - This represents an instruction that is a pseudo instruction 77 // or one that has not been implemented yet. It is illegal to code generate 78 // it, but tolerated for intermediate implementation stages. 79 Pseudo = 0, 80 81 /// Raw - This form is for instructions that don't have any operands, so 82 /// they are just a fixed opcode value, like 'leave'. 83 RawFrm = 1, 84 85 /// AddRegFrm - This form is used for instructions like 'push r32' that have 86 /// their one register operand added to their opcode. 87 AddRegFrm = 2, 88 89 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 90 /// to specify a destination, which in this case is a register. 91 /// 92 MRMDestReg = 3, 93 94 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 95 /// to specify a destination, which in this case is memory. 96 /// 97 MRMDestMem = 4, 98 99 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 100 /// to specify a source, which in this case is a register. 101 /// 102 MRMSrcReg = 5, 103 104 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 105 /// to specify a source, which in this case is memory. 106 /// 107 MRMSrcMem = 6, 108 109 /// MRM[0-7][rm] - These forms are used to represent instructions that use 110 /// a Mod/RM byte, and use the middle field to hold extended opcode 111 /// information. In the intel manual these are represented as /0, /1, ... 112 /// 113 114 // First, instructions that operate on a register r/m operand... 115 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 116 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 117 118 // Next, instructions that operate on a memory r/m operand... 119 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 120 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 121 122 // MRMInitReg - This form is used for instructions whose source and 123 // destinations are the same register. 124 MRMInitReg = 32, 125 126 FormMask = 63, 127 128 //===------------------------------------------------------------------===// 129 // Actual flags... 130 131 // OpSize - Set if this instruction requires an operand size prefix (0x66), 132 // which most often indicates that the instruction operates on 16 bit data 133 // instead of 32 bit data. 134 OpSize = 1 << 6, 135 136 // AsSize - Set if this instruction requires an operand size prefix (0x67), 137 // which most often indicates that the instruction address 16 bit address 138 // instead of 32 bit address (or 32 bit address in 64 bit mode). 139 AdSize = 1 << 7, 140 141 //===------------------------------------------------------------------===// 142 // Op0Mask - There are several prefix bytes that are used to form two byte 143 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 144 // used to obtain the setting of this field. If no bits in this field is 145 // set, there is no prefix byte for obtaining a multibyte opcode. 146 // 147 Op0Shift = 8, 148 Op0Mask = 0xF << Op0Shift, 149 150 // TB - TwoByte - Set if this instruction has a two byte opcode, which 151 // starts with a 0x0F byte before the real opcode. 152 TB = 1 << Op0Shift, 153 154 // REP - The 0xF3 prefix byte indicating repetition of the following 155 // instruction. 156 REP = 2 << Op0Shift, 157 158 // D8-DF - These escape opcodes are used by the floating point unit. These 159 // values must remain sequential. 160 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 161 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 162 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 163 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 164 165 // XS, XD - These prefix codes are for single and double precision scalar 166 // floating point operations performed in the SSE registers. 167 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 168 169 // T8, TA - Prefix after the 0x0F prefix. 170 T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 171 172 //===------------------------------------------------------------------===// 173 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 174 // They are used to specify GPRs and SSE registers, 64-bit operand size, 175 // etc. We only cares about REX.W and REX.R bits and only the former is 176 // statically determined. 177 // 178 REXShift = 12, 179 REX_W = 1 << REXShift, 180 181 //===------------------------------------------------------------------===// 182 // This three-bit field describes the size of an immediate operand. Zero is 183 // unused so that we can tell if we forgot to set a value. 184 ImmShift = 13, 185 ImmMask = 7 << ImmShift, 186 Imm8 = 1 << ImmShift, 187 Imm16 = 2 << ImmShift, 188 Imm32 = 3 << ImmShift, 189 Imm64 = 4 << ImmShift, 190 191 //===------------------------------------------------------------------===// 192 // FP Instruction Classification... Zero is non-fp instruction. 193 194 // FPTypeMask - Mask for all of the FP types... 195 FPTypeShift = 16, 196 FPTypeMask = 7 << FPTypeShift, 197 198 // NotFP - The default, set for instructions that do not use FP registers. 199 NotFP = 0 << FPTypeShift, 200 201 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 202 ZeroArgFP = 1 << FPTypeShift, 203 204 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 205 OneArgFP = 2 << FPTypeShift, 206 207 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 208 // result back to ST(0). For example, fcos, fsqrt, etc. 209 // 210 OneArgFPRW = 3 << FPTypeShift, 211 212 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 213 // explicit argument, storing the result to either ST(0) or the implicit 214 // argument. For example: fadd, fsub, fmul, etc... 215 TwoArgFP = 4 << FPTypeShift, 216 217 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 218 // explicit argument, but have no destination. Example: fucom, fucomi, ... 219 CompareFP = 5 << FPTypeShift, 220 221 // CondMovFP - "2 operand" floating point conditional move instructions. 222 CondMovFP = 6 << FPTypeShift, 223 224 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 225 SpecialFP = 7 << FPTypeShift, 226 227 // Lock prefix 228 LOCKShift = 19, 229 LOCK = 1 << LOCKShift, 230 231 // Bits 20 -> 23 are unused 232 OpcodeShift = 24, 233 OpcodeMask = 0xFF << OpcodeShift 234 }; 235} 236 237class X86InstrInfo : public TargetInstrInfoImpl { 238 X86TargetMachine &TM; 239 const X86RegisterInfo RI; 240 241 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 242 /// RegOp2MemOpTable2 - Load / store folding opcode maps. 243 /// 244 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr; 245 DenseMap<unsigned*, unsigned> RegOp2MemOpTable0; 246 DenseMap<unsigned*, unsigned> RegOp2MemOpTable1; 247 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2; 248 249 /// MemOp2RegOpTable - Load / store unfolding opcode map. 250 /// 251 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 252 253public: 254 X86InstrInfo(X86TargetMachine &tm); 255 256 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 257 /// such, whenever a client has an instance of instruction info, it should 258 /// always be able to get register info as well (through this method). 259 /// 260 virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } 261 262 // Return true if the instruction is a register to register move and 263 // leave the source and dest operands in the passed parameters. 264 // 265 bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, 266 unsigned& destReg) const; 267 unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; 268 unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; 269 bool isReallyTriviallyReMaterializable(MachineInstr *MI) const; 270 bool isInvariantLoad(MachineInstr *MI) const; 271 272 /// convertToThreeAddress - This method must be implemented by targets that 273 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 274 /// may be able to convert a two-address instruction into a true 275 /// three-address instruction on demand. This allows the X86 target (for 276 /// example) to convert ADD and SHL instructions into LEA instructions if they 277 /// would require register copies due to two-addressness. 278 /// 279 /// This method returns a null pointer if the transformation cannot be 280 /// performed, otherwise it returns the new instruction. 281 /// 282 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 283 MachineBasicBlock::iterator &MBBI, 284 LiveVariables &LV) const; 285 286 /// commuteInstruction - We have a few instructions that must be hacked on to 287 /// commute them. 288 /// 289 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 290 291 // Branch analysis. 292 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 293 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 294 MachineBasicBlock *&FBB, 295 std::vector<MachineOperand> &Cond) const; 296 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 297 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 298 MachineBasicBlock *FBB, 299 const std::vector<MachineOperand> &Cond) const; 300 virtual void copyRegToReg(MachineBasicBlock &MBB, 301 MachineBasicBlock::iterator MI, 302 unsigned DestReg, unsigned SrcReg, 303 const TargetRegisterClass *DestRC, 304 const TargetRegisterClass *SrcRC) const; 305 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 306 MachineBasicBlock::iterator MI, 307 unsigned SrcReg, bool isKill, int FrameIndex, 308 const TargetRegisterClass *RC) const; 309 310 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 311 SmallVectorImpl<MachineOperand> &Addr, 312 const TargetRegisterClass *RC, 313 SmallVectorImpl<MachineInstr*> &NewMIs) const; 314 315 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 316 MachineBasicBlock::iterator MI, 317 unsigned DestReg, int FrameIndex, 318 const TargetRegisterClass *RC) const; 319 320 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 321 SmallVectorImpl<MachineOperand> &Addr, 322 const TargetRegisterClass *RC, 323 SmallVectorImpl<MachineInstr*> &NewMIs) const; 324 325 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 326 MachineBasicBlock::iterator MI, 327 const std::vector<CalleeSavedInfo> &CSI) const; 328 329 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 330 MachineBasicBlock::iterator MI, 331 const std::vector<CalleeSavedInfo> &CSI) const; 332 333 /// foldMemoryOperand - If this target supports it, fold a load or store of 334 /// the specified stack slot into the specified machine instruction for the 335 /// specified operand(s). If this is possible, the target should perform the 336 /// folding and return true, otherwise it should return false. If it folds 337 /// the instruction, it is likely that the MachineInstruction the iterator 338 /// references has been changed. 339 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, 340 MachineInstr* MI, 341 SmallVectorImpl<unsigned> &Ops, 342 int FrameIndex) const; 343 344 /// foldMemoryOperand - Same as the previous version except it allows folding 345 /// of any load and store from / to any address, not just from a specific 346 /// stack slot. 347 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, 348 MachineInstr* MI, 349 SmallVectorImpl<unsigned> &Ops, 350 MachineInstr* LoadMI) const; 351 352 /// canFoldMemoryOperand - Returns true if the specified load / store is 353 /// folding is possible. 354 virtual bool canFoldMemoryOperand(MachineInstr*, SmallVectorImpl<unsigned> &) const; 355 356 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 357 /// a store or a load and a store into two or more instruction. If this is 358 /// possible, returns true as well as the new instructions by reference. 359 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 360 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 361 SmallVectorImpl<MachineInstr*> &NewMIs) const; 362 363 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 364 SmallVectorImpl<SDNode*> &NewNodes) const; 365 366 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 367 /// instruction after load / store are unfolded from an instruction of the 368 /// specified opcode. It returns zero if the specified unfolding is not 369 /// possible. 370 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 371 bool UnfoldLoad, bool UnfoldStore) const; 372 373 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; 374 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const; 375 376 const TargetRegisterClass *getPointerRegClass() const; 377 378 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 379 // specified machine instruction. 380 // 381 unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const { 382 return TID->TSFlags >> X86II::OpcodeShift; 383 } 384 unsigned char getBaseOpcodeFor(unsigned Opcode) const { 385 return getBaseOpcodeFor(&get(Opcode)); 386 } 387 388private: 389 MachineInstr* foldMemoryOperand(MachineInstr* MI, 390 unsigned OpNum, 391 SmallVector<MachineOperand,4> &MOs) const; 392}; 393 394} // End llvm namespace 395 396#endif 397