X86InstrInfo.h revision 4d46d0af583b95a5d4f7d490f542c4fb65b9e824
1//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86INSTRUCTIONINFO_H 15#define X86INSTRUCTIONINFO_H 16 17#include "llvm/Target/TargetInstrInfo.h" 18#include "X86.h" 19#include "X86RegisterInfo.h" 20#include "llvm/ADT/IndexedMap.h" 21#include "llvm/Target/TargetRegisterInfo.h" 22 23namespace llvm { 24 class X86RegisterInfo; 25 class X86TargetMachine; 26 27namespace X86 { 28 // X86 specific condition code. These correspond to X86_*_COND in 29 // X86InstrInfo.td. They must be kept in synch. 30 enum CondCode { 31 COND_A = 0, 32 COND_AE = 1, 33 COND_B = 2, 34 COND_BE = 3, 35 COND_E = 4, 36 COND_G = 5, 37 COND_GE = 6, 38 COND_L = 7, 39 COND_LE = 8, 40 COND_NE = 9, 41 COND_NO = 10, 42 COND_NP = 11, 43 COND_NS = 12, 44 COND_O = 13, 45 COND_P = 14, 46 COND_S = 15, 47 COND_INVALID 48 }; 49 50 // Turn condition code into conditional branch opcode. 51 unsigned GetCondBranchFromCond(CondCode CC); 52 53 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 54 /// e.g. turning COND_E to COND_NE. 55 CondCode GetOppositeBranchCondition(X86::CondCode CC); 56 57 /// GetSwappedBranchCondition - Return the branch condition that would be 58 /// the result of exchanging the two operands of a comparison without 59 /// changing the result produced. 60 /// e.g. COND_E to COND_E, COND_G -> COND_L 61 CondCode GetSwappedBranchCondition(X86::CondCode CC); 62} 63 64/// X86II - This namespace holds all of the target specific flags that 65/// instruction info tracks. 66/// 67namespace X86II { 68 enum { 69 //===------------------------------------------------------------------===// 70 // Instruction types. These are the standard/most common forms for X86 71 // instructions. 72 // 73 74 // PseudoFrm - This represents an instruction that is a pseudo instruction 75 // or one that has not been implemented yet. It is illegal to code generate 76 // it, but tolerated for intermediate implementation stages. 77 Pseudo = 0, 78 79 /// Raw - This form is for instructions that don't have any operands, so 80 /// they are just a fixed opcode value, like 'leave'. 81 RawFrm = 1, 82 83 /// AddRegFrm - This form is used for instructions like 'push r32' that have 84 /// their one register operand added to their opcode. 85 AddRegFrm = 2, 86 87 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 88 /// to specify a destination, which in this case is a register. 89 /// 90 MRMDestReg = 3, 91 92 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 93 /// to specify a destination, which in this case is memory. 94 /// 95 MRMDestMem = 4, 96 97 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 98 /// to specify a source, which in this case is a register. 99 /// 100 MRMSrcReg = 5, 101 102 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 103 /// to specify a source, which in this case is memory. 104 /// 105 MRMSrcMem = 6, 106 107 /// MRM[0-7][rm] - These forms are used to represent instructions that use 108 /// a Mod/RM byte, and use the middle field to hold extended opcode 109 /// information. In the intel manual these are represented as /0, /1, ... 110 /// 111 112 // First, instructions that operate on a register r/m operand... 113 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 114 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 115 116 // Next, instructions that operate on a memory r/m operand... 117 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 118 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 119 120 // MRMInitReg - This form is used for instructions whose source and 121 // destinations are the same register. 122 MRMInitReg = 32, 123 124 FormMask = 63, 125 126 //===------------------------------------------------------------------===// 127 // Actual flags... 128 129 // OpSize - Set if this instruction requires an operand size prefix (0x66), 130 // which most often indicates that the instruction operates on 16 bit data 131 // instead of 32 bit data. 132 OpSize = 1 << 6, 133 134 // AsSize - Set if this instruction requires an operand size prefix (0x67), 135 // which most often indicates that the instruction address 16 bit address 136 // instead of 32 bit address (or 32 bit address in 64 bit mode). 137 AdSize = 1 << 7, 138 139 //===------------------------------------------------------------------===// 140 // Op0Mask - There are several prefix bytes that are used to form two byte 141 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 142 // used to obtain the setting of this field. If no bits in this field is 143 // set, there is no prefix byte for obtaining a multibyte opcode. 144 // 145 Op0Shift = 8, 146 Op0Mask = 0xF << Op0Shift, 147 148 // TB - TwoByte - Set if this instruction has a two byte opcode, which 149 // starts with a 0x0F byte before the real opcode. 150 TB = 1 << Op0Shift, 151 152 // REP - The 0xF3 prefix byte indicating repetition of the following 153 // instruction. 154 REP = 2 << Op0Shift, 155 156 // D8-DF - These escape opcodes are used by the floating point unit. These 157 // values must remain sequential. 158 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 159 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 160 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 161 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 162 163 // XS, XD - These prefix codes are for single and double precision scalar 164 // floating point operations performed in the SSE registers. 165 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 166 167 // T8, TA - Prefix after the 0x0F prefix. 168 T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 169 170 //===------------------------------------------------------------------===// 171 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 172 // They are used to specify GPRs and SSE registers, 64-bit operand size, 173 // etc. We only cares about REX.W and REX.R bits and only the former is 174 // statically determined. 175 // 176 REXShift = 12, 177 REX_W = 1 << REXShift, 178 179 //===------------------------------------------------------------------===// 180 // This three-bit field describes the size of an immediate operand. Zero is 181 // unused so that we can tell if we forgot to set a value. 182 ImmShift = 13, 183 ImmMask = 7 << ImmShift, 184 Imm8 = 1 << ImmShift, 185 Imm16 = 2 << ImmShift, 186 Imm32 = 3 << ImmShift, 187 Imm64 = 4 << ImmShift, 188 189 //===------------------------------------------------------------------===// 190 // FP Instruction Classification... Zero is non-fp instruction. 191 192 // FPTypeMask - Mask for all of the FP types... 193 FPTypeShift = 16, 194 FPTypeMask = 7 << FPTypeShift, 195 196 // NotFP - The default, set for instructions that do not use FP registers. 197 NotFP = 0 << FPTypeShift, 198 199 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 200 ZeroArgFP = 1 << FPTypeShift, 201 202 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 203 OneArgFP = 2 << FPTypeShift, 204 205 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 206 // result back to ST(0). For example, fcos, fsqrt, etc. 207 // 208 OneArgFPRW = 3 << FPTypeShift, 209 210 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 211 // explicit argument, storing the result to either ST(0) or the implicit 212 // argument. For example: fadd, fsub, fmul, etc... 213 TwoArgFP = 4 << FPTypeShift, 214 215 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 216 // explicit argument, but have no destination. Example: fucom, fucomi, ... 217 CompareFP = 5 << FPTypeShift, 218 219 // CondMovFP - "2 operand" floating point conditional move instructions. 220 CondMovFP = 6 << FPTypeShift, 221 222 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 223 SpecialFP = 7 << FPTypeShift, 224 225 // Lock prefix 226 LOCKShift = 19, 227 LOCK = 1 << LOCKShift, 228 229 // Bits 20 -> 23 are unused 230 OpcodeShift = 24, 231 OpcodeMask = 0xFF << OpcodeShift 232 }; 233} 234 235inline static bool isScale(const MachineOperand &MO) { 236 return MO.isImmediate() && 237 (MO.getImm() == 1 || MO.getImm() == 2 || 238 MO.getImm() == 4 || MO.getImm() == 8); 239} 240 241inline static bool isMem(const MachineInstr *MI, unsigned Op) { 242 if (MI->getOperand(Op).isFrameIndex()) return true; 243 return Op+4 <= MI->getNumOperands() && 244 MI->getOperand(Op ).isRegister() && isScale(MI->getOperand(Op+1)) && 245 MI->getOperand(Op+2).isRegister() && 246 (MI->getOperand(Op+3).isImmediate() || 247 MI->getOperand(Op+3).isGlobalAddress() || 248 MI->getOperand(Op+3).isConstantPoolIndex() || 249 MI->getOperand(Op+3).isJumpTableIndex()); 250} 251 252class X86InstrInfo : public TargetInstrInfoImpl { 253 X86TargetMachine &TM; 254 const X86RegisterInfo RI; 255 256 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 257 /// RegOp2MemOpTable2 - Load / store folding opcode maps. 258 /// 259 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr; 260 DenseMap<unsigned*, unsigned> RegOp2MemOpTable0; 261 DenseMap<unsigned*, unsigned> RegOp2MemOpTable1; 262 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2; 263 264 /// MemOp2RegOpTable - Load / store unfolding opcode map. 265 /// 266 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 267 268public: 269 explicit X86InstrInfo(X86TargetMachine &tm); 270 271 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 272 /// such, whenever a client has an instance of instruction info, it should 273 /// always be able to get register info as well (through this method). 274 /// 275 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 276 277 // Return true if the instruction is a register to register move and 278 // leave the source and dest operands in the passed parameters. 279 // 280 bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, 281 unsigned& destReg) const; 282 unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; 283 unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; 284 285 bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const; 286 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 287 unsigned DestReg, const MachineInstr *Orig) const; 288 289 bool isInvariantLoad(MachineInstr *MI) const; 290 291 /// convertToThreeAddress - This method must be implemented by targets that 292 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 293 /// may be able to convert a two-address instruction into a true 294 /// three-address instruction on demand. This allows the X86 target (for 295 /// example) to convert ADD and SHL instructions into LEA instructions if they 296 /// would require register copies due to two-addressness. 297 /// 298 /// This method returns a null pointer if the transformation cannot be 299 /// performed, otherwise it returns the new instruction. 300 /// 301 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 302 MachineBasicBlock::iterator &MBBI, 303 LiveVariables *LV) const; 304 305 /// commuteInstruction - We have a few instructions that must be hacked on to 306 /// commute them. 307 /// 308 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 309 310 // Branch analysis. 311 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 312 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 313 MachineBasicBlock *&FBB, 314 SmallVectorImpl<MachineOperand> &Cond) const; 315 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 316 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 317 MachineBasicBlock *FBB, 318 const SmallVectorImpl<MachineOperand> &Cond) const; 319 virtual bool copyRegToReg(MachineBasicBlock &MBB, 320 MachineBasicBlock::iterator MI, 321 unsigned DestReg, unsigned SrcReg, 322 const TargetRegisterClass *DestRC, 323 const TargetRegisterClass *SrcRC) const; 324 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 325 MachineBasicBlock::iterator MI, 326 unsigned SrcReg, bool isKill, int FrameIndex, 327 const TargetRegisterClass *RC) const; 328 329 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 330 SmallVectorImpl<MachineOperand> &Addr, 331 const TargetRegisterClass *RC, 332 SmallVectorImpl<MachineInstr*> &NewMIs) const; 333 334 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 335 MachineBasicBlock::iterator MI, 336 unsigned DestReg, int FrameIndex, 337 const TargetRegisterClass *RC) const; 338 339 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 340 SmallVectorImpl<MachineOperand> &Addr, 341 const TargetRegisterClass *RC, 342 SmallVectorImpl<MachineInstr*> &NewMIs) const; 343 344 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 345 MachineBasicBlock::iterator MI, 346 const std::vector<CalleeSavedInfo> &CSI) const; 347 348 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 349 MachineBasicBlock::iterator MI, 350 const std::vector<CalleeSavedInfo> &CSI) const; 351 352 /// foldMemoryOperand - If this target supports it, fold a load or store of 353 /// the specified stack slot into the specified machine instruction for the 354 /// specified operand(s). If this is possible, the target should perform the 355 /// folding and return true, otherwise it should return false. If it folds 356 /// the instruction, it is likely that the MachineInstruction the iterator 357 /// references has been changed. 358 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, 359 MachineInstr* MI, 360 SmallVectorImpl<unsigned> &Ops, 361 int FrameIndex) const; 362 363 /// foldMemoryOperand - Same as the previous version except it allows folding 364 /// of any load and store from / to any address, not just from a specific 365 /// stack slot. 366 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, 367 MachineInstr* MI, 368 SmallVectorImpl<unsigned> &Ops, 369 MachineInstr* LoadMI) const; 370 371 /// canFoldMemoryOperand - Returns true if the specified load / store is 372 /// folding is possible. 373 virtual bool canFoldMemoryOperand(MachineInstr*, SmallVectorImpl<unsigned> &) const; 374 375 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 376 /// a store or a load and a store into two or more instruction. If this is 377 /// possible, returns true as well as the new instructions by reference. 378 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 379 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 380 SmallVectorImpl<MachineInstr*> &NewMIs) const; 381 382 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 383 SmallVectorImpl<SDNode*> &NewNodes) const; 384 385 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 386 /// instruction after load / store are unfolded from an instruction of the 387 /// specified opcode. It returns zero if the specified unfolding is not 388 /// possible. 389 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 390 bool UnfoldLoad, bool UnfoldStore) const; 391 392 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; 393 virtual 394 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 395 396 const TargetRegisterClass *getPointerRegClass() const; 397 398 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 399 // specified machine instruction. 400 // 401 unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const { 402 return TID->TSFlags >> X86II::OpcodeShift; 403 } 404 unsigned char getBaseOpcodeFor(unsigned Opcode) const { 405 return getBaseOpcodeFor(&get(Opcode)); 406 } 407 408 static bool isX86_64NonExtLowByteReg(unsigned reg) { 409 return (reg == X86::SPL || reg == X86::BPL || 410 reg == X86::SIL || reg == X86::DIL); 411 } 412 413 static unsigned sizeOfImm(const TargetInstrDesc *Desc); 414 static unsigned getX86RegNum(unsigned RegNo); 415 static bool isX86_64ExtendedReg(const MachineOperand &MO); 416 static unsigned determineREX(const MachineInstr &MI); 417 418 /// GetInstSize - Returns the size of the specified MachineInstr. 419 /// 420 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 421 422private: 423 MachineInstr* foldMemoryOperand(MachineFunction &MF, 424 MachineInstr* MI, 425 unsigned OpNum, 426 SmallVector<MachineOperand,4> &MOs) const; 427}; 428 429} // End llvm namespace 430 431#endif 432