X86InstrInfo.h revision 55e7c827301da0e5e03b26835bff259c320b3bf7
1a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)// 3a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)// The LLVM Compiler Infrastructure 4a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)// 5a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)// This file is distributed under the University of Illinois Open Source 6a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)// License. See LICENSE.TXT for details. 7a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)// 8a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)//===----------------------------------------------------------------------===// 9a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)// 10a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)// This file contains the X86 implementation of the TargetInstrInfo class. 11a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)// 12a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)//===----------------------------------------------------------------------===// 13a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 14a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)#ifndef X86INSTRUCTIONINFO_H 15a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)#define X86INSTRUCTIONINFO_H 16a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 17a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)#include "llvm/Target/TargetInstrInfo.h" 18a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)#include "X86.h" 19a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)#include "X86RegisterInfo.h" 20a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)#include "llvm/ADT/DenseMap.h" 21a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)#include "llvm/Target/TargetRegisterInfo.h" 22a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 23a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)namespace llvm { 24a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) class X86RegisterInfo; 25a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) class X86TargetMachine; 26a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 27a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)namespace X86 { 28a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) // X86 specific condition code. These correspond to X86_*_COND in 29a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) // X86InstrInfo.td. They must be kept in synch. 30a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) enum CondCode { 31a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) COND_A = 0, 32a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) COND_AE = 1, 33a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) COND_B = 2, 34a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) COND_BE = 3, 35a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) COND_E = 4, 36a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) COND_G = 5, 37a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) COND_GE = 6, 38a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) COND_L = 7, 39a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) COND_LE = 8, 40a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) COND_NE = 9, 41a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) COND_NO = 10, 42a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) COND_NP = 11, 43a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) COND_NS = 12, 44a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) COND_O = 13, 45a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) COND_P = 14, 46a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) COND_S = 15, 47a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 48a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) // Artificial condition codes. These are used by AnalyzeBranch 49a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) // to indicate a block terminated with two conditional branches to 50a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 51a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) // which can't be represented on x86 with a single condition. These 52a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) // are never used in MachineInstrs. 53a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) COND_NE_OR_P, 54a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) COND_NP_OR_E, 55a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 56a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) COND_INVALID 57a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) }; 58a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 59a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) // Turn condition code into conditional branch opcode. 60a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) unsigned GetCondBranchFromCond(CondCode CC); 61a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 62a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// GetOppositeBranchCondition - Return the inverse of the specified cond, 63a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// e.g. turning COND_E to COND_NE. 64a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) CondCode GetOppositeBranchCondition(X86::CondCode CC); 65a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 66a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)} 67a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 68a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)/// X86II - This namespace holds all of the target specific flags that 69a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)/// instruction info tracks. 70a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)/// 71a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)namespace X86II { 72a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) enum { 73a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) //===------------------------------------------------------------------===// 74a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) // X86 Specific MachineOperand flags. 75a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 76a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) MO_NO_FLAG = 0, 77a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 78a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 79a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// relocation of: 80a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// SYMBOL_LABEL + [. - PICBASELABEL] 81a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) MO_GOT_ABSOLUTE_ADDRESS = 1, 82a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 83a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 84a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// immediate should get the value of the symbol minus the PIC base label: 85a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// SYMBOL_LABEL - PICBASELABEL 86a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) MO_PIC_BASE_OFFSET = 2, 87a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 88a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// MO_GOTOFF - On a symbol operand this indicates that the immediate should 89a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// the offset to the location of the symbol name from the base of the GOT. 90a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// SYMBOL_LABEL @GOTOFF 91a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) MO_GOTOFF = 3, 92a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 93a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 94a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) //===------------------------------------------------------------------===// 95a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) // Instruction encodings. These are the standard/most common forms for X86 96a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) // instructions. 97a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) // 98a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 99a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) // PseudoFrm - This represents an instruction that is a pseudo instruction 100a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) // or one that has not been implemented yet. It is illegal to code generate 101a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) // it, but tolerated for intermediate implementation stages. 102a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) Pseudo = 0, 103a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 104a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// Raw - This form is for instructions that don't have any operands, so 105a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// they are just a fixed opcode value, like 'leave'. 106a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) RawFrm = 1, 107a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 108a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// AddRegFrm - This form is used for instructions like 'push r32' that have 109a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// their one register operand added to their opcode. 110a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) AddRegFrm = 2, 111a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 112a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 113a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// to specify a destination, which in this case is a register. 114a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// 115a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) MRMDestReg = 3, 116a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 117a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 118a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// to specify a destination, which in this case is memory. 119a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// 120a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) MRMDestMem = 4, 121a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 122a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 123a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// to specify a source, which in this case is a register. 124a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// 125a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) MRMSrcReg = 5, 126 127 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 128 /// to specify a source, which in this case is memory. 129 /// 130 MRMSrcMem = 6, 131 132 /// MRM[0-7][rm] - These forms are used to represent instructions that use 133 /// a Mod/RM byte, and use the middle field to hold extended opcode 134 /// information. In the intel manual these are represented as /0, /1, ... 135 /// 136 137 // First, instructions that operate on a register r/m operand... 138 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 139 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 140 141 // Next, instructions that operate on a memory r/m operand... 142 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 143 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 144 145 // MRMInitReg - This form is used for instructions whose source and 146 // destinations are the same register. 147 MRMInitReg = 32, 148 149 FormMask = 63, 150 151 //===------------------------------------------------------------------===// 152 // Actual flags... 153 154 // OpSize - Set if this instruction requires an operand size prefix (0x66), 155 // which most often indicates that the instruction operates on 16 bit data 156 // instead of 32 bit data. 157 OpSize = 1 << 6, 158 159 // AsSize - Set if this instruction requires an operand size prefix (0x67), 160 // which most often indicates that the instruction address 16 bit address 161 // instead of 32 bit address (or 32 bit address in 64 bit mode). 162 AdSize = 1 << 7, 163 164 //===------------------------------------------------------------------===// 165 // Op0Mask - There are several prefix bytes that are used to form two byte 166 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 167 // used to obtain the setting of this field. If no bits in this field is 168 // set, there is no prefix byte for obtaining a multibyte opcode. 169 // 170 Op0Shift = 8, 171 Op0Mask = 0xF << Op0Shift, 172 173 // TB - TwoByte - Set if this instruction has a two byte opcode, which 174 // starts with a 0x0F byte before the real opcode. 175 TB = 1 << Op0Shift, 176 177 // REP - The 0xF3 prefix byte indicating repetition of the following 178 // instruction. 179 REP = 2 << Op0Shift, 180 181 // D8-DF - These escape opcodes are used by the floating point unit. These 182 // values must remain sequential. 183 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 184 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 185 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 186 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 187 188 // XS, XD - These prefix codes are for single and double precision scalar 189 // floating point operations performed in the SSE registers. 190 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 191 192 // T8, TA - Prefix after the 0x0F prefix. 193 T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 194 195 //===------------------------------------------------------------------===// 196 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 197 // They are used to specify GPRs and SSE registers, 64-bit operand size, 198 // etc. We only cares about REX.W and REX.R bits and only the former is 199 // statically determined. 200 // 201 REXShift = 12, 202 REX_W = 1 << REXShift, 203 204 //===------------------------------------------------------------------===// 205 // This three-bit field describes the size of an immediate operand. Zero is 206 // unused so that we can tell if we forgot to set a value. 207 ImmShift = 13, 208 ImmMask = 7 << ImmShift, 209 Imm8 = 1 << ImmShift, 210 Imm16 = 2 << ImmShift, 211 Imm32 = 3 << ImmShift, 212 Imm64 = 4 << ImmShift, 213 214 //===------------------------------------------------------------------===// 215 // FP Instruction Classification... Zero is non-fp instruction. 216 217 // FPTypeMask - Mask for all of the FP types... 218 FPTypeShift = 16, 219 FPTypeMask = 7 << FPTypeShift, 220 221 // NotFP - The default, set for instructions that do not use FP registers. 222 NotFP = 0 << FPTypeShift, 223 224 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 225 ZeroArgFP = 1 << FPTypeShift, 226 227 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 228 OneArgFP = 2 << FPTypeShift, 229 230 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 231 // result back to ST(0). For example, fcos, fsqrt, etc. 232 // 233 OneArgFPRW = 3 << FPTypeShift, 234 235 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 236 // explicit argument, storing the result to either ST(0) or the implicit 237 // argument. For example: fadd, fsub, fmul, etc... 238 TwoArgFP = 4 << FPTypeShift, 239 240 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 241 // explicit argument, but have no destination. Example: fucom, fucomi, ... 242 CompareFP = 5 << FPTypeShift, 243 244 // CondMovFP - "2 operand" floating point conditional move instructions. 245 CondMovFP = 6 << FPTypeShift, 246 247 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 248 SpecialFP = 7 << FPTypeShift, 249 250 // Lock prefix 251 LOCKShift = 19, 252 LOCK = 1 << LOCKShift, 253 254 // Segment override prefixes. Currently we just need ability to address 255 // stuff in gs and fs segments. 256 SegOvrShift = 20, 257 SegOvrMask = 3 << SegOvrShift, 258 FS = 1 << SegOvrShift, 259 GS = 2 << SegOvrShift, 260 261 // Bits 22 -> 23 are unused 262 OpcodeShift = 24, 263 OpcodeMask = 0xFF << OpcodeShift 264 }; 265} 266 267const int X86AddrNumOperands = 5; 268 269inline static bool isScale(const MachineOperand &MO) { 270 return MO.isImm() && 271 (MO.getImm() == 1 || MO.getImm() == 2 || 272 MO.getImm() == 4 || MO.getImm() == 8); 273} 274 275inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { 276 if (MI->getOperand(Op).isFI()) return true; 277 return Op+4 <= MI->getNumOperands() && 278 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 279 MI->getOperand(Op+2).isReg() && 280 (MI->getOperand(Op+3).isImm() || 281 MI->getOperand(Op+3).isGlobal() || 282 MI->getOperand(Op+3).isCPI() || 283 MI->getOperand(Op+3).isJTI()); 284} 285 286inline static bool isMem(const MachineInstr *MI, unsigned Op) { 287 if (MI->getOperand(Op).isFI()) return true; 288 return Op+5 <= MI->getNumOperands() && 289 MI->getOperand(Op+4).isReg() && 290 isLeaMem(MI, Op); 291} 292 293class X86InstrInfo : public TargetInstrInfoImpl { 294 X86TargetMachine &TM; 295 const X86RegisterInfo RI; 296 297 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 298 /// RegOp2MemOpTable2 - Load / store folding opcode maps. 299 /// 300 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr; 301 DenseMap<unsigned*, unsigned> RegOp2MemOpTable0; 302 DenseMap<unsigned*, unsigned> RegOp2MemOpTable1; 303 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2; 304 305 /// MemOp2RegOpTable - Load / store unfolding opcode map. 306 /// 307 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 308 309public: 310 explicit X86InstrInfo(X86TargetMachine &tm); 311 312 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 313 /// such, whenever a client has an instance of instruction info, it should 314 /// always be able to get register info as well (through this method). 315 /// 316 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 317 318 /// Return true if the instruction is a register to register move and return 319 /// the source and dest operands and their sub-register indices by reference. 320 virtual bool isMoveInstr(const MachineInstr &MI, 321 unsigned &SrcReg, unsigned &DstReg, 322 unsigned &SrcSubIdx, unsigned &DstSubIdx) const; 323 324 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 325 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; 326 327 bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const; 328 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 329 unsigned DestReg, const MachineInstr *Orig) const; 330 331 bool isInvariantLoad(const MachineInstr *MI) const; 332 333 /// convertToThreeAddress - This method must be implemented by targets that 334 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 335 /// may be able to convert a two-address instruction into a true 336 /// three-address instruction on demand. This allows the X86 target (for 337 /// example) to convert ADD and SHL instructions into LEA instructions if they 338 /// would require register copies due to two-addressness. 339 /// 340 /// This method returns a null pointer if the transformation cannot be 341 /// performed, otherwise it returns the new instruction. 342 /// 343 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 344 MachineBasicBlock::iterator &MBBI, 345 LiveVariables *LV) const; 346 347 /// commuteInstruction - We have a few instructions that must be hacked on to 348 /// commute them. 349 /// 350 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 351 352 // Branch analysis. 353 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 354 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 355 MachineBasicBlock *&FBB, 356 SmallVectorImpl<MachineOperand> &Cond, 357 bool AllowModify) const; 358 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 359 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 360 MachineBasicBlock *FBB, 361 const SmallVectorImpl<MachineOperand> &Cond) const; 362 virtual bool copyRegToReg(MachineBasicBlock &MBB, 363 MachineBasicBlock::iterator MI, 364 unsigned DestReg, unsigned SrcReg, 365 const TargetRegisterClass *DestRC, 366 const TargetRegisterClass *SrcRC) const; 367 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 368 MachineBasicBlock::iterator MI, 369 unsigned SrcReg, bool isKill, int FrameIndex, 370 const TargetRegisterClass *RC) const; 371 372 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 373 SmallVectorImpl<MachineOperand> &Addr, 374 const TargetRegisterClass *RC, 375 SmallVectorImpl<MachineInstr*> &NewMIs) const; 376 377 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 378 MachineBasicBlock::iterator MI, 379 unsigned DestReg, int FrameIndex, 380 const TargetRegisterClass *RC) const; 381 382 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 383 SmallVectorImpl<MachineOperand> &Addr, 384 const TargetRegisterClass *RC, 385 SmallVectorImpl<MachineInstr*> &NewMIs) const; 386 387 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 388 MachineBasicBlock::iterator MI, 389 const std::vector<CalleeSavedInfo> &CSI) const; 390 391 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 392 MachineBasicBlock::iterator MI, 393 const std::vector<CalleeSavedInfo> &CSI) const; 394 395 /// foldMemoryOperand - If this target supports it, fold a load or store of 396 /// the specified stack slot into the specified machine instruction for the 397 /// specified operand(s). If this is possible, the target should perform the 398 /// folding and return true, otherwise it should return false. If it folds 399 /// the instruction, it is likely that the MachineInstruction the iterator 400 /// references has been changed. 401 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 402 MachineInstr* MI, 403 const SmallVectorImpl<unsigned> &Ops, 404 int FrameIndex) const; 405 406 /// foldMemoryOperand - Same as the previous version except it allows folding 407 /// of any load and store from / to any address, not just from a specific 408 /// stack slot. 409 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 410 MachineInstr* MI, 411 const SmallVectorImpl<unsigned> &Ops, 412 MachineInstr* LoadMI) const; 413 414 /// canFoldMemoryOperand - Returns true if the specified load / store is 415 /// folding is possible. 416 virtual bool canFoldMemoryOperand(const MachineInstr*, 417 const SmallVectorImpl<unsigned> &) const; 418 419 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 420 /// a store or a load and a store into two or more instruction. If this is 421 /// possible, returns true as well as the new instructions by reference. 422 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 423 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 424 SmallVectorImpl<MachineInstr*> &NewMIs) const; 425 426 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 427 SmallVectorImpl<SDNode*> &NewNodes) const; 428 429 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 430 /// instruction after load / store are unfolded from an instruction of the 431 /// specified opcode. It returns zero if the specified unfolding is not 432 /// possible. 433 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 434 bool UnfoldLoad, bool UnfoldStore) const; 435 436 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const; 437 virtual 438 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 439 440 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 441 /// instruction that defines the specified register class. 442 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 443 444 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 445 // specified machine instruction. 446 // 447 unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const { 448 return TID->TSFlags >> X86II::OpcodeShift; 449 } 450 unsigned char getBaseOpcodeFor(unsigned Opcode) const { 451 return getBaseOpcodeFor(&get(Opcode)); 452 } 453 454 static bool isX86_64NonExtLowByteReg(unsigned reg) { 455 return (reg == X86::SPL || reg == X86::BPL || 456 reg == X86::SIL || reg == X86::DIL); 457 } 458 459 static unsigned sizeOfImm(const TargetInstrDesc *Desc); 460 static bool isX86_64ExtendedReg(const MachineOperand &MO); 461 static unsigned determineREX(const MachineInstr &MI); 462 463 /// GetInstSize - Returns the size of the specified MachineInstr. 464 /// 465 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 466 467 /// getGlobalBaseReg - Return a virtual register initialized with the 468 /// the global base register value. Output instructions required to 469 /// initialize the register in the function entry block, if necessary. 470 /// 471 unsigned getGlobalBaseReg(MachineFunction *MF) const; 472 473private: 474 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 475 MachineInstr* MI, 476 unsigned OpNum, 477 const SmallVectorImpl<MachineOperand> &MOs) const; 478}; 479 480} // End llvm namespace 481 482#endif 483