X86InstrInfo.h revision 74e726e3270c99169cc90fb3c676eeaae273f48c
1//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86INSTRUCTIONINFO_H 15#define X86INSTRUCTIONINFO_H 16 17#include "llvm/Target/TargetInstrInfo.h" 18#include "X86.h" 19#include "X86RegisterInfo.h" 20#include "llvm/ADT/DenseMap.h" 21#include "llvm/Target/TargetRegisterInfo.h" 22 23namespace llvm { 24 class X86RegisterInfo; 25 class X86TargetMachine; 26 27namespace X86 { 28 // X86 specific condition code. These correspond to X86_*_COND in 29 // X86InstrInfo.td. They must be kept in synch. 30 enum CondCode { 31 COND_A = 0, 32 COND_AE = 1, 33 COND_B = 2, 34 COND_BE = 3, 35 COND_E = 4, 36 COND_G = 5, 37 COND_GE = 6, 38 COND_L = 7, 39 COND_LE = 8, 40 COND_NE = 9, 41 COND_NO = 10, 42 COND_NP = 11, 43 COND_NS = 12, 44 COND_O = 13, 45 COND_P = 14, 46 COND_S = 15, 47 48 // Artificial condition codes. These are used by AnalyzeBranch 49 // to indicate a block terminated with two conditional branches to 50 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 51 // which can't be represented on x86 with a single condition. These 52 // are never used in MachineInstrs. 53 COND_NE_OR_P, 54 COND_NP_OR_E, 55 56 COND_INVALID 57 }; 58 59 // Turn condition code into conditional branch opcode. 60 unsigned GetCondBranchFromCond(CondCode CC); 61 62 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 63 /// e.g. turning COND_E to COND_NE. 64 CondCode GetOppositeBranchCondition(X86::CondCode CC); 65 66} 67 68/// X86II - This namespace holds all of the target specific flags that 69/// instruction info tracks. 70/// 71namespace X86II { 72 enum { 73 //===------------------------------------------------------------------===// 74 // X86 Specific MachineOperand flags. 75 76 MO_NO_FLAG = 0, 77 78 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 79 /// relocation of: 80 /// SYMBOL_LABEL + [. - PICBASELABEL] 81 MO_GOT_ABSOLUTE_ADDRESS = 1, 82 83 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 84 /// immediate should get the value of the symbol minus the PIC base label: 85 /// SYMBOL_LABEL - PICBASELABEL 86 MO_PIC_BASE_OFFSET = 2, 87 88 /// MO_GOT - On a symbol operand this indicates that the immediate is the 89 /// offset to the GOT entry for the symbol name from the base of the GOT. 90 /// 91 /// See the X86-64 ELF ABI supplement for more details. 92 /// SYMBOL_LABEL @GOT 93 MO_GOT = 3, 94 95 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 96 /// the offset to the location of the symbol name from the base of the GOT. 97 /// 98 /// See the X86-64 ELF ABI supplement for more details. 99 /// SYMBOL_LABEL @GOTOFF 100 MO_GOTOFF = 4, 101 102 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 103 /// offset to the GOT entry for the symbol name from the current code 104 /// location. 105 /// 106 /// See the X86-64 ELF ABI supplement for more details. 107 /// SYMBOL_LABEL @GOTPCREL 108 MO_GOTPCREL = 5, 109 110 /// MO_PLT - On a symbol operand this indicates that the immediate is 111 /// offset to the PLT entry of symbol name from the current code location. 112 /// 113 /// See the X86-64 ELF ABI supplement for more details. 114 /// SYMBOL_LABEL @PLT 115 MO_PLT = 6, 116 117 /// MO_TLSGD - On a symbol operand this indicates that the immediate is 118 /// some TLS offset. 119 /// 120 /// See 'ELF Handling for Thread-Local Storage' for more details. 121 /// SYMBOL_LABEL @TLSGD 122 MO_TLSGD = 7, 123 124 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 125 /// some TLS offset. 126 /// 127 /// See 'ELF Handling for Thread-Local Storage' for more details. 128 /// SYMBOL_LABEL @GOTTPOFF 129 MO_GOTTPOFF = 8, 130 131 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 132 /// some TLS offset. 133 /// 134 /// See 'ELF Handling for Thread-Local Storage' for more details. 135 /// SYMBOL_LABEL @INDNTPOFF 136 MO_INDNTPOFF = 9, 137 138 /// MO_TPOFF - On a symbol operand this indicates that the immediate is 139 /// some TLS offset. 140 /// 141 /// See 'ELF Handling for Thread-Local Storage' for more details. 142 /// SYMBOL_LABEL @TPOFF 143 MO_TPOFF = 10, 144 145 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 146 /// some TLS offset. 147 /// 148 /// See 'ELF Handling for Thread-Local Storage' for more details. 149 /// SYMBOL_LABEL @NTPOFF 150 MO_NTPOFF = 11, 151 152 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 153 /// reference is actually to the "__imp_FOO" symbol. This is used for 154 /// dllimport linkage on windows. 155 MO_DLLIMPORT = 12, 156 157 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the 158 /// reference is actually to the "FOO$stub" symbol. This is used for calls 159 /// and jumps to external functions on Tiger and before. 160 MO_DARWIN_STUB = 13, 161 162 163 //===------------------------------------------------------------------===// 164 // Instruction encodings. These are the standard/most common forms for X86 165 // instructions. 166 // 167 168 // PseudoFrm - This represents an instruction that is a pseudo instruction 169 // or one that has not been implemented yet. It is illegal to code generate 170 // it, but tolerated for intermediate implementation stages. 171 Pseudo = 0, 172 173 /// Raw - This form is for instructions that don't have any operands, so 174 /// they are just a fixed opcode value, like 'leave'. 175 RawFrm = 1, 176 177 /// AddRegFrm - This form is used for instructions like 'push r32' that have 178 /// their one register operand added to their opcode. 179 AddRegFrm = 2, 180 181 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 182 /// to specify a destination, which in this case is a register. 183 /// 184 MRMDestReg = 3, 185 186 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 187 /// to specify a destination, which in this case is memory. 188 /// 189 MRMDestMem = 4, 190 191 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 192 /// to specify a source, which in this case is a register. 193 /// 194 MRMSrcReg = 5, 195 196 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 197 /// to specify a source, which in this case is memory. 198 /// 199 MRMSrcMem = 6, 200 201 /// MRM[0-7][rm] - These forms are used to represent instructions that use 202 /// a Mod/RM byte, and use the middle field to hold extended opcode 203 /// information. In the intel manual these are represented as /0, /1, ... 204 /// 205 206 // First, instructions that operate on a register r/m operand... 207 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 208 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 209 210 // Next, instructions that operate on a memory r/m operand... 211 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 212 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 213 214 // MRMInitReg - This form is used for instructions whose source and 215 // destinations are the same register. 216 MRMInitReg = 32, 217 218 FormMask = 63, 219 220 //===------------------------------------------------------------------===// 221 // Actual flags... 222 223 // OpSize - Set if this instruction requires an operand size prefix (0x66), 224 // which most often indicates that the instruction operates on 16 bit data 225 // instead of 32 bit data. 226 OpSize = 1 << 6, 227 228 // AsSize - Set if this instruction requires an operand size prefix (0x67), 229 // which most often indicates that the instruction address 16 bit address 230 // instead of 32 bit address (or 32 bit address in 64 bit mode). 231 AdSize = 1 << 7, 232 233 //===------------------------------------------------------------------===// 234 // Op0Mask - There are several prefix bytes that are used to form two byte 235 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 236 // used to obtain the setting of this field. If no bits in this field is 237 // set, there is no prefix byte for obtaining a multibyte opcode. 238 // 239 Op0Shift = 8, 240 Op0Mask = 0xF << Op0Shift, 241 242 // TB - TwoByte - Set if this instruction has a two byte opcode, which 243 // starts with a 0x0F byte before the real opcode. 244 TB = 1 << Op0Shift, 245 246 // REP - The 0xF3 prefix byte indicating repetition of the following 247 // instruction. 248 REP = 2 << Op0Shift, 249 250 // D8-DF - These escape opcodes are used by the floating point unit. These 251 // values must remain sequential. 252 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 253 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 254 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 255 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 256 257 // XS, XD - These prefix codes are for single and double precision scalar 258 // floating point operations performed in the SSE registers. 259 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 260 261 // T8, TA - Prefix after the 0x0F prefix. 262 T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 263 264 //===------------------------------------------------------------------===// 265 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 266 // They are used to specify GPRs and SSE registers, 64-bit operand size, 267 // etc. We only cares about REX.W and REX.R bits and only the former is 268 // statically determined. 269 // 270 REXShift = 12, 271 REX_W = 1 << REXShift, 272 273 //===------------------------------------------------------------------===// 274 // This three-bit field describes the size of an immediate operand. Zero is 275 // unused so that we can tell if we forgot to set a value. 276 ImmShift = 13, 277 ImmMask = 7 << ImmShift, 278 Imm8 = 1 << ImmShift, 279 Imm16 = 2 << ImmShift, 280 Imm32 = 3 << ImmShift, 281 Imm64 = 4 << ImmShift, 282 283 //===------------------------------------------------------------------===// 284 // FP Instruction Classification... Zero is non-fp instruction. 285 286 // FPTypeMask - Mask for all of the FP types... 287 FPTypeShift = 16, 288 FPTypeMask = 7 << FPTypeShift, 289 290 // NotFP - The default, set for instructions that do not use FP registers. 291 NotFP = 0 << FPTypeShift, 292 293 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 294 ZeroArgFP = 1 << FPTypeShift, 295 296 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 297 OneArgFP = 2 << FPTypeShift, 298 299 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 300 // result back to ST(0). For example, fcos, fsqrt, etc. 301 // 302 OneArgFPRW = 3 << FPTypeShift, 303 304 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 305 // explicit argument, storing the result to either ST(0) or the implicit 306 // argument. For example: fadd, fsub, fmul, etc... 307 TwoArgFP = 4 << FPTypeShift, 308 309 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 310 // explicit argument, but have no destination. Example: fucom, fucomi, ... 311 CompareFP = 5 << FPTypeShift, 312 313 // CondMovFP - "2 operand" floating point conditional move instructions. 314 CondMovFP = 6 << FPTypeShift, 315 316 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 317 SpecialFP = 7 << FPTypeShift, 318 319 // Lock prefix 320 LOCKShift = 19, 321 LOCK = 1 << LOCKShift, 322 323 // Segment override prefixes. Currently we just need ability to address 324 // stuff in gs and fs segments. 325 SegOvrShift = 20, 326 SegOvrMask = 3 << SegOvrShift, 327 FS = 1 << SegOvrShift, 328 GS = 2 << SegOvrShift, 329 330 // Bits 22 -> 23 are unused 331 OpcodeShift = 24, 332 OpcodeMask = 0xFF << OpcodeShift 333 }; 334} 335 336const int X86AddrNumOperands = 5; 337 338inline static bool isScale(const MachineOperand &MO) { 339 return MO.isImm() && 340 (MO.getImm() == 1 || MO.getImm() == 2 || 341 MO.getImm() == 4 || MO.getImm() == 8); 342} 343 344inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { 345 if (MI->getOperand(Op).isFI()) return true; 346 return Op+4 <= MI->getNumOperands() && 347 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 348 MI->getOperand(Op+2).isReg() && 349 (MI->getOperand(Op+3).isImm() || 350 MI->getOperand(Op+3).isGlobal() || 351 MI->getOperand(Op+3).isCPI() || 352 MI->getOperand(Op+3).isJTI()); 353} 354 355inline static bool isMem(const MachineInstr *MI, unsigned Op) { 356 if (MI->getOperand(Op).isFI()) return true; 357 return Op+5 <= MI->getNumOperands() && 358 MI->getOperand(Op+4).isReg() && 359 isLeaMem(MI, Op); 360} 361 362class X86InstrInfo : public TargetInstrInfoImpl { 363 X86TargetMachine &TM; 364 const X86RegisterInfo RI; 365 366 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 367 /// RegOp2MemOpTable2 - Load / store folding opcode maps. 368 /// 369 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr; 370 DenseMap<unsigned*, unsigned> RegOp2MemOpTable0; 371 DenseMap<unsigned*, unsigned> RegOp2MemOpTable1; 372 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2; 373 374 /// MemOp2RegOpTable - Load / store unfolding opcode map. 375 /// 376 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 377 378public: 379 explicit X86InstrInfo(X86TargetMachine &tm); 380 381 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 382 /// such, whenever a client has an instance of instruction info, it should 383 /// always be able to get register info as well (through this method). 384 /// 385 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 386 387 /// Return true if the instruction is a register to register move and return 388 /// the source and dest operands and their sub-register indices by reference. 389 virtual bool isMoveInstr(const MachineInstr &MI, 390 unsigned &SrcReg, unsigned &DstReg, 391 unsigned &SrcSubIdx, unsigned &DstSubIdx) const; 392 393 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 394 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; 395 396 bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const; 397 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 398 unsigned DestReg, const MachineInstr *Orig) const; 399 400 bool isInvariantLoad(const MachineInstr *MI) const; 401 402 /// convertToThreeAddress - This method must be implemented by targets that 403 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 404 /// may be able to convert a two-address instruction into a true 405 /// three-address instruction on demand. This allows the X86 target (for 406 /// example) to convert ADD and SHL instructions into LEA instructions if they 407 /// would require register copies due to two-addressness. 408 /// 409 /// This method returns a null pointer if the transformation cannot be 410 /// performed, otherwise it returns the new instruction. 411 /// 412 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 413 MachineBasicBlock::iterator &MBBI, 414 LiveVariables *LV) const; 415 416 /// commuteInstruction - We have a few instructions that must be hacked on to 417 /// commute them. 418 /// 419 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 420 421 // Branch analysis. 422 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 423 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 424 MachineBasicBlock *&FBB, 425 SmallVectorImpl<MachineOperand> &Cond, 426 bool AllowModify) const; 427 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 428 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 429 MachineBasicBlock *FBB, 430 const SmallVectorImpl<MachineOperand> &Cond) const; 431 virtual bool copyRegToReg(MachineBasicBlock &MBB, 432 MachineBasicBlock::iterator MI, 433 unsigned DestReg, unsigned SrcReg, 434 const TargetRegisterClass *DestRC, 435 const TargetRegisterClass *SrcRC) const; 436 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 437 MachineBasicBlock::iterator MI, 438 unsigned SrcReg, bool isKill, int FrameIndex, 439 const TargetRegisterClass *RC) const; 440 441 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 442 SmallVectorImpl<MachineOperand> &Addr, 443 const TargetRegisterClass *RC, 444 SmallVectorImpl<MachineInstr*> &NewMIs) const; 445 446 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 447 MachineBasicBlock::iterator MI, 448 unsigned DestReg, int FrameIndex, 449 const TargetRegisterClass *RC) const; 450 451 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 452 SmallVectorImpl<MachineOperand> &Addr, 453 const TargetRegisterClass *RC, 454 SmallVectorImpl<MachineInstr*> &NewMIs) const; 455 456 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 457 MachineBasicBlock::iterator MI, 458 const std::vector<CalleeSavedInfo> &CSI) const; 459 460 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 461 MachineBasicBlock::iterator MI, 462 const std::vector<CalleeSavedInfo> &CSI) const; 463 464 /// foldMemoryOperand - If this target supports it, fold a load or store of 465 /// the specified stack slot into the specified machine instruction for the 466 /// specified operand(s). If this is possible, the target should perform the 467 /// folding and return true, otherwise it should return false. If it folds 468 /// the instruction, it is likely that the MachineInstruction the iterator 469 /// references has been changed. 470 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 471 MachineInstr* MI, 472 const SmallVectorImpl<unsigned> &Ops, 473 int FrameIndex) const; 474 475 /// foldMemoryOperand - Same as the previous version except it allows folding 476 /// of any load and store from / to any address, not just from a specific 477 /// stack slot. 478 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 479 MachineInstr* MI, 480 const SmallVectorImpl<unsigned> &Ops, 481 MachineInstr* LoadMI) const; 482 483 /// canFoldMemoryOperand - Returns true if the specified load / store is 484 /// folding is possible. 485 virtual bool canFoldMemoryOperand(const MachineInstr*, 486 const SmallVectorImpl<unsigned> &) const; 487 488 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 489 /// a store or a load and a store into two or more instruction. If this is 490 /// possible, returns true as well as the new instructions by reference. 491 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 492 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 493 SmallVectorImpl<MachineInstr*> &NewMIs) const; 494 495 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 496 SmallVectorImpl<SDNode*> &NewNodes) const; 497 498 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 499 /// instruction after load / store are unfolded from an instruction of the 500 /// specified opcode. It returns zero if the specified unfolding is not 501 /// possible. 502 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 503 bool UnfoldLoad, bool UnfoldStore) const; 504 505 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const; 506 virtual 507 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 508 509 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 510 /// instruction that defines the specified register class. 511 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 512 513 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 514 // specified machine instruction. 515 // 516 unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const { 517 return TID->TSFlags >> X86II::OpcodeShift; 518 } 519 unsigned char getBaseOpcodeFor(unsigned Opcode) const { 520 return getBaseOpcodeFor(&get(Opcode)); 521 } 522 523 static bool isX86_64NonExtLowByteReg(unsigned reg) { 524 return (reg == X86::SPL || reg == X86::BPL || 525 reg == X86::SIL || reg == X86::DIL); 526 } 527 528 static unsigned sizeOfImm(const TargetInstrDesc *Desc); 529 static bool isX86_64ExtendedReg(const MachineOperand &MO); 530 static unsigned determineREX(const MachineInstr &MI); 531 532 /// GetInstSize - Returns the size of the specified MachineInstr. 533 /// 534 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 535 536 /// getGlobalBaseReg - Return a virtual register initialized with the 537 /// the global base register value. Output instructions required to 538 /// initialize the register in the function entry block, if necessary. 539 /// 540 unsigned getGlobalBaseReg(MachineFunction *MF) const; 541 542private: 543 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 544 MachineInstr* MI, 545 unsigned OpNum, 546 const SmallVectorImpl<MachineOperand> &MOs) const; 547}; 548 549} // End llvm namespace 550 551#endif 552