X86InstrInfo.h revision 7da9ecf9677b751d81515f95168ae3cb2df54160
1c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath// 3c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath// The LLVM Compiler Infrastructure 4c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath// 5c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath// This file is distributed under the University of Illinois Open Source 6c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath// License. See LICENSE.TXT for details. 7c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath// 8c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath//===----------------------------------------------------------------------===// 9c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath// 10c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath// This file contains the X86 implementation of the TargetInstrInfo class. 11c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath// 12c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath//===----------------------------------------------------------------------===// 13c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 14c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath#ifndef X86INSTRUCTIONINFO_H 15c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath#define X86INSTRUCTIONINFO_H 167faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez 17c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath#include "llvm/Target/TargetInstrInfo.h" 18c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath#include "X86.h" 19c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath#include "X86RegisterInfo.h" 20c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath#include "llvm/ADT/DenseMap.h" 21c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath#include "llvm/Target/TargetRegisterInfo.h" 22c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 23c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamathnamespace llvm { 24c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath class X86RegisterInfo; 25c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath class X86TargetMachine; 26c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 27c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamathnamespace X86 { 28c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // X86 specific condition code. These correspond to X86_*_COND in 29c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // X86InstrInfo.td. They must be kept in synch. 30c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath enum CondCode { 31c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath COND_A = 0, 32c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath COND_AE = 1, 33c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath COND_B = 2, 34c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath COND_BE = 3, 35c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath COND_E = 4, 36c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath COND_G = 5, 37c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath COND_GE = 6, 38c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath COND_L = 7, 39c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath COND_LE = 8, 40c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath COND_NE = 9, 41c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath COND_NO = 10, 42c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath COND_NP = 11, 43c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath COND_NS = 12, 44c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath COND_O = 13, 45c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath COND_P = 14, 46c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath COND_S = 15, 47c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 48c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // Artificial condition codes. These are used by AnalyzeBranch 49c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // to indicate a block terminated with two conditional branches to 50c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 51c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // which can't be represented on x86 with a single condition. These 52c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // are never used in MachineInstrs. 53c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath COND_NE_OR_P, 54c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath COND_NP_OR_E, 55c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 56c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath COND_INVALID 57c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath }; 58c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 59c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // Turn condition code into conditional branch opcode. 60c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath unsigned GetCondBranchFromCond(CondCode CC); 61c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 62c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// GetOppositeBranchCondition - Return the inverse of the specified cond, 63c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// e.g. turning COND_E to COND_NE. 64c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath CondCode GetOppositeBranchCondition(X86::CondCode CC); 65c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 66c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath} 67c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 68c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath/// X86II - This namespace holds all of the target specific flags that 69c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath/// instruction info tracks. 70c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath/// 71c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamathnamespace X86II { 72c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// Target Operand Flag enum. 73c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath enum TOF { 74c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath //===------------------------------------------------------------------===// 75c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // X86 Specific MachineOperand flags. 76c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 77c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MO_NO_FLAG, 78c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 79c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 80c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// relocation of: 81c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// SYMBOL_LABEL + [. - PICBASELABEL] 82c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MO_GOT_ABSOLUTE_ADDRESS, 83c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 84c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 85c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// immediate should get the value of the symbol minus the PIC base label: 86c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// SYMBOL_LABEL - PICBASELABEL 87c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MO_PIC_BASE_OFFSET, 88c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 89c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// MO_GOT - On a symbol operand this indicates that the immediate is the 90c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// offset to the GOT entry for the symbol name from the base of the GOT. 91c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// 92c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// See the X86-64 ELF ABI supplement for more details. 93c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// SYMBOL_LABEL @GOT 94c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MO_GOT, 95c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 96c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 97c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// the offset to the location of the symbol name from the base of the GOT. 98c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// 99c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// See the X86-64 ELF ABI supplement for more details. 100c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// SYMBOL_LABEL @GOTOFF 101c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MO_GOTOFF, 102c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 103c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 104c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// offset to the GOT entry for the symbol name from the current code 105c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// location. 106c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// 107c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// See the X86-64 ELF ABI supplement for more details. 108c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// SYMBOL_LABEL @GOTPCREL 109c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MO_GOTPCREL, 110c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 111c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// MO_PLT - On a symbol operand this indicates that the immediate is 112c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// offset to the PLT entry of symbol name from the current code location. 113c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// 114c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// See the X86-64 ELF ABI supplement for more details. 115c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// SYMBOL_LABEL @PLT 116c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MO_PLT, 117c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 118c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// MO_TLSGD - On a symbol operand this indicates that the immediate is 119c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// some TLS offset. 120c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// 121c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// See 'ELF Handling for Thread-Local Storage' for more details. 122c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// SYMBOL_LABEL @TLSGD 123c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MO_TLSGD, 124c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 125c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 126c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// some TLS offset. 127c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// 128c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// See 'ELF Handling for Thread-Local Storage' for more details. 129c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// SYMBOL_LABEL @GOTTPOFF 130c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MO_GOTTPOFF, 131c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 132c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 133c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// some TLS offset. 134c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// 135c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// See 'ELF Handling for Thread-Local Storage' for more details. 136c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// SYMBOL_LABEL @INDNTPOFF 137c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MO_INDNTPOFF, 138c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 139c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// MO_TPOFF - On a symbol operand this indicates that the immediate is 140c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// some TLS offset. 141c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// 142c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// See 'ELF Handling for Thread-Local Storage' for more details. 143c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// SYMBOL_LABEL @TPOFF 144c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MO_TPOFF, 145c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 146c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 147c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// some TLS offset. 148c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// 149c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// See 'ELF Handling for Thread-Local Storage' for more details. 150c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// SYMBOL_LABEL @NTPOFF 151c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MO_NTPOFF, 152c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 153c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 154c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// reference is actually to the "__imp_FOO" symbol. This is used for 155c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// dllimport linkage on windows. 156c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MO_DLLIMPORT, 157c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 158c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the 159c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// reference is actually to the "FOO$stub" symbol. This is used for calls 160c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// and jumps to external functions on Tiger and before. 161c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MO_DARWIN_STUB, 162c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 163c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 164c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 165c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 166c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MO_DARWIN_NONLAZY, 167c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 168c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 169c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 170c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 171c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MO_DARWIN_NONLAZY_PIC_BASE, 172c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 173c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this 174c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE", 175c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// which is a PIC-base-relative reference to a hidden dyld lazy pointer 176c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// stub. 177c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE 178c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath }; 179c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath} 180c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 181c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath/// isGlobalStubReference - Return true if the specified TargetFlag operand is 182c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath/// a reference to a stub for a global, not the global itself. 183c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamathinline static bool isGlobalStubReference(unsigned char TargetFlag) { 184c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath switch (TargetFlag) { 185c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath case X86II::MO_DLLIMPORT: // dllimport stub. 186c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath case X86II::MO_GOTPCREL: // rip-relative GOT reference. 187c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath case X86II::MO_GOT: // normal GOT reference. 188c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. 189c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. 190c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref. 191c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath return true; 192c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath default: 193c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath return false; 194c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath } 195c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath} 196c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 197c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath/// isGlobalRelativeToPICBase - Return true if the specified global value 198c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this 199c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath/// is true, the addressing mode has the PIC base register added in (e.g. EBX). 200c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamathinline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { 201c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath switch (TargetFlag) { 202c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath case X86II::MO_GOTOFF: // isPICStyleGOT: local global. 203c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath case X86II::MO_GOT: // isPICStyleGOT: other global. 204c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. 205c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. 206c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global. 207c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath return true; 208c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath default: 209c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath return false; 210c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath } 211c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath} 212c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 213c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath/// X86II - This namespace holds all of the target specific flags that 214c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath/// instruction info tracks. 215c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath/// 216c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamathnamespace X86II { 217c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath enum { 218c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath //===------------------------------------------------------------------===// 219c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // Instruction encodings. These are the standard/most common forms for X86 220c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // instructions. 221c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // 222c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 223c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // PseudoFrm - This represents an instruction that is a pseudo instruction 224c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // or one that has not been implemented yet. It is illegal to code generate 225c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // it, but tolerated for intermediate implementation stages. 226c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath Pseudo = 0, 227c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 228c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// Raw - This form is for instructions that don't have any operands, so 229c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// they are just a fixed opcode value, like 'leave'. 230c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath RawFrm = 1, 2317faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez 232c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// AddRegFrm - This form is used for instructions like 'push r32' that have 233c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// their one register operand added to their opcode. 234c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath AddRegFrm = 2, 235c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 236c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 237c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// to specify a destination, which in this case is a register. 238c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// 239c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MRMDestReg = 3, 240c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 241c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 242c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// to specify a destination, which in this case is memory. 243c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// 244c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MRMDestMem = 4, 2457faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez 2467faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 247c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// to specify a source, which in this case is a register. 248c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// 249c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MRMSrcReg = 5, 250c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 251c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 252c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// to specify a source, which in this case is memory. 253c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// 254c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MRMSrcMem = 6, 255c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 256c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// MRM[0-7][rm] - These forms are used to represent instructions that use 257c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// a Mod/RM byte, and use the middle field to hold extended opcode 258c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// information. In the intel manual these are represented as /0, /1, ... 259c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// 260c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 261c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // First, instructions that operate on a register r/m operand... 262c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 263c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 2647faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez 2657faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez // Next, instructions that operate on a memory r/m operand... 2667faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 2677faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 2687faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez 269c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // MRMInitReg - This form is used for instructions whose source and 270c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // destinations are the same register. 271c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MRMInitReg = 32, 272c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 273c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath FormMask = 63, 274c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 275c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath //===------------------------------------------------------------------===// 276c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // Actual flags... 277c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 278c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // OpSize - Set if this instruction requires an operand size prefix (0x66), 279c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // which most often indicates that the instruction operates on 16 bit data 280c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // instead of 32 bit data. 281c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath OpSize = 1 << 6, 282c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 283c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // AsSize - Set if this instruction requires an operand size prefix (0x67), 284c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // which most often indicates that the instruction address 16 bit address 285c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // instead of 32 bit address (or 32 bit address in 64 bit mode). 2867faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez AdSize = 1 << 7, 287c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 288c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath //===------------------------------------------------------------------===// 289c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // Op0Mask - There are several prefix bytes that are used to form two byte 290c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 291c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // used to obtain the setting of this field. If no bits in this field is 292c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // set, there is no prefix byte for obtaining a multibyte opcode. 293c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // 2947faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez Op0Shift = 8, 2957faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez Op0Mask = 0xF << Op0Shift, 296c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 297c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // TB - TwoByte - Set if this instruction has a two byte opcode, which 298c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // starts with a 0x0F byte before the real opcode. 299c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath TB = 1 << Op0Shift, 300c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 301c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // REP - The 0xF3 prefix byte indicating repetition of the following 302c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // instruction. 303c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath REP = 2 << Op0Shift, 3047faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez 305c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // D8-DF - These escape opcodes are used by the floating point unit. These 306c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // values must remain sequential. 307c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 308c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath DA = 5 << Op0Shift, DB = 6 << Op0Shift, 309c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath DC = 7 << Op0Shift, DD = 8 << Op0Shift, 310c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath DE = 9 << Op0Shift, DF = 10 << Op0Shift, 311c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 312c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // XS, XD - These prefix codes are for single and double precision scalar 313c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // floating point operations performed in the SSE registers. 314c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath XD = 11 << Op0Shift, XS = 12 << Op0Shift, 315c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 3167faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez // T8, TA - Prefix after the 0x0F prefix. 3177faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 318c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 319c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // TF - Prefix before and after 0x0F 320c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath TF = 15 << Op0Shift, 321c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 322c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath //===------------------------------------------------------------------===// 323c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 324c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // They are used to specify GPRs and SSE registers, 64-bit operand size, 325c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // etc. We only cares about REX.W and REX.R bits and only the former is 3267faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez // statically determined. 327c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // 328c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath REXShift = 12, 329c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath REX_W = 1 << REXShift, 330c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 331c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath //===------------------------------------------------------------------===// 332c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // This three-bit field describes the size of an immediate operand. Zero is 333c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // unused so that we can tell if we forgot to set a value. 334c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath ImmShift = 13, 335c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath ImmMask = 7 << ImmShift, 336c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath Imm8 = 1 << ImmShift, 337c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath Imm16 = 2 << ImmShift, 338c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath Imm32 = 3 << ImmShift, 339c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath Imm64 = 4 << ImmShift, 340c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 3417faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez //===------------------------------------------------------------------===// 3427faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez // FP Instruction Classification... Zero is non-fp instruction. 343c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 344c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // FPTypeMask - Mask for all of the FP types... 345c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath FPTypeShift = 16, 346c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath FPTypeMask = 7 << FPTypeShift, 347c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 348c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // NotFP - The default, set for instructions that do not use FP registers. 349c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath NotFP = 0 << FPTypeShift, 350c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 351c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 352c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath ZeroArgFP = 1 << FPTypeShift, 353c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 354c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 355c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath OneArgFP = 2 << FPTypeShift, 356c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 357c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 358c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // result back to ST(0). For example, fcos, fsqrt, etc. 3597faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez // 3607faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez OneArgFPRW = 3 << FPTypeShift, 361c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 362c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 363c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // explicit argument, storing the result to either ST(0) or the implicit 364c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // argument. For example: fadd, fsub, fmul, etc... 365c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath TwoArgFP = 4 << FPTypeShift, 366c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 367c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 368c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // explicit argument, but have no destination. Example: fucom, fucomi, ... 369c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath CompareFP = 5 << FPTypeShift, 370c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 371c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // CondMovFP - "2 operand" floating point conditional move instructions. 372c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath CondMovFP = 6 << FPTypeShift, 373c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 374c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 375c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath SpecialFP = 7 << FPTypeShift, 376c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 3777faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez // Lock prefix 3787faaa9f3f0df9d23790277834d426c3d992ac3baCarlos Hernandez LOCKShift = 19, 379c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath LOCK = 1 << LOCKShift, 380c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 381c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // Segment override prefixes. Currently we just need ability to address 382c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // stuff in gs and fs segments. 383c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath SegOvrShift = 20, 384c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath SegOvrMask = 3 << SegOvrShift, 385c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath FS = 1 << SegOvrShift, 386c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath GS = 2 << SegOvrShift, 387c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 388c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath // Bits 22 -> 23 are unused 389c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath OpcodeShift = 24, 390c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath OpcodeMask = 0xFF << OpcodeShift 391c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath }; 392c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath} 393c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 394c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamathconst int X86AddrNumOperands = 5; 395c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 396c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamathinline static bool isScale(const MachineOperand &MO) { 397c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath return MO.isImm() && 398c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath (MO.getImm() == 1 || MO.getImm() == 2 || 399c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MO.getImm() == 4 || MO.getImm() == 8); 400c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath} 401c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 402c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamathinline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { 403c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath if (MI->getOperand(Op).isFI()) return true; 404c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath return Op+4 <= MI->getNumOperands() && 405c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 406c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MI->getOperand(Op+2).isReg() && 407c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath (MI->getOperand(Op+3).isImm() || 408c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MI->getOperand(Op+3).isGlobal() || 409c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MI->getOperand(Op+3).isCPI() || 410c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MI->getOperand(Op+3).isJTI()); 411c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath} 412c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 413c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamathinline static bool isMem(const MachineInstr *MI, unsigned Op) { 414c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath if (MI->getOperand(Op).isFI()) return true; 415c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath return Op+5 <= MI->getNumOperands() && 416c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath MI->getOperand(Op+4).isReg() && 417c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath isLeaMem(MI, Op); 418c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath} 419c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 420c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamathclass X86InstrInfo : public TargetInstrInfoImpl { 421c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath X86TargetMachine &TM; 422c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath const X86RegisterInfo RI; 423c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 424c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 425c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// RegOp2MemOpTable2 - Load / store folding opcode maps. 426c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// 427c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2Addr; 428c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable0; 429c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable1; 430c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2; 431c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 432c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// MemOp2RegOpTable - Load / store unfolding opcode map. 433c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// 434c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 435c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 436c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamathpublic: 437c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath explicit X86InstrInfo(X86TargetMachine &tm); 438c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 439c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 440c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// such, whenever a client has an instance of instruction info, it should 441c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// always be able to get register info as well (through this method). 442c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// 443c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 444c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 445c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// Return true if the instruction is a register to register move and return 446c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// the source and dest operands and their sub-register indices by reference. 447c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath virtual bool isMoveInstr(const MachineInstr &MI, 448c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath unsigned &SrcReg, unsigned &DstReg, 449c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath unsigned &SrcSubIdx, unsigned &DstSubIdx) const; 450c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath 451c981c48f5bc9aefeffc0bcb0cc3934c2fae179ddNarayan Kamath /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 452 /// extension instruction. That is, it's like a copy where it's legal for the 453 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 454 /// true, then it's expected the pre-extension value is available as a subreg 455 /// of the result register. This also returns the sub-register index in 456 /// SubIdx. 457 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 458 unsigned &SrcReg, unsigned &DstReg, 459 unsigned &SubIdx) const; 460 461 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 462 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 463 /// stack locations as well. This uses a heuristic so it isn't 464 /// reliable for correctness. 465 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 466 int &FrameIndex) const; 467 468 /// hasLoadFromStackSlot - If the specified machine instruction has 469 /// a load from a stack slot, return true along with the FrameIndex 470 /// of the loaded stack slot and the machine mem operand containing 471 /// the reference. If not, return false. Unlike 472 /// isLoadFromStackSlot, this returns true for any instructions that 473 /// loads from the stack. This is a hint only and may not catch all 474 /// cases. 475 bool hasLoadFromStackSlot(const MachineInstr *MI, 476 const MachineMemOperand *&MMO, 477 int &FrameIndex) const; 478 479 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; 480 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 481 /// stack locations as well. This uses a heuristic so it isn't 482 /// reliable for correctness. 483 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 484 int &FrameIndex) const; 485 486 /// hasStoreToStackSlot - If the specified machine instruction has a 487 /// store to a stack slot, return true along with the FrameIndex of 488 /// the loaded stack slot and the machine mem operand containing the 489 /// reference. If not, return false. Unlike isStoreToStackSlot, 490 /// this returns true for any instructions that loads from the 491 /// stack. This is a hint only and may not catch all cases. 492 bool hasStoreToStackSlot(const MachineInstr *MI, 493 const MachineMemOperand *&MMO, 494 int &FrameIndex) const; 495 496 bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 497 AliasAnalysis *AA) const; 498 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 499 unsigned DestReg, unsigned SubIdx, 500 const MachineInstr *Orig, 501 const TargetRegisterInfo *TRI) const; 502 503 /// convertToThreeAddress - This method must be implemented by targets that 504 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 505 /// may be able to convert a two-address instruction into a true 506 /// three-address instruction on demand. This allows the X86 target (for 507 /// example) to convert ADD and SHL instructions into LEA instructions if they 508 /// would require register copies due to two-addressness. 509 /// 510 /// This method returns a null pointer if the transformation cannot be 511 /// performed, otherwise it returns the new instruction. 512 /// 513 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 514 MachineBasicBlock::iterator &MBBI, 515 LiveVariables *LV) const; 516 517 /// commuteInstruction - We have a few instructions that must be hacked on to 518 /// commute them. 519 /// 520 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 521 522 // Branch analysis. 523 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 524 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 525 MachineBasicBlock *&FBB, 526 SmallVectorImpl<MachineOperand> &Cond, 527 bool AllowModify) const; 528 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 529 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 530 MachineBasicBlock *FBB, 531 const SmallVectorImpl<MachineOperand> &Cond) const; 532 virtual bool copyRegToReg(MachineBasicBlock &MBB, 533 MachineBasicBlock::iterator MI, 534 unsigned DestReg, unsigned SrcReg, 535 const TargetRegisterClass *DestRC, 536 const TargetRegisterClass *SrcRC) const; 537 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 538 MachineBasicBlock::iterator MI, 539 unsigned SrcReg, bool isKill, int FrameIndex, 540 const TargetRegisterClass *RC) const; 541 542 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 543 SmallVectorImpl<MachineOperand> &Addr, 544 const TargetRegisterClass *RC, 545 MachineInstr::mmo_iterator MMOBegin, 546 MachineInstr::mmo_iterator MMOEnd, 547 SmallVectorImpl<MachineInstr*> &NewMIs) const; 548 549 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 550 MachineBasicBlock::iterator MI, 551 unsigned DestReg, int FrameIndex, 552 const TargetRegisterClass *RC) const; 553 554 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 555 SmallVectorImpl<MachineOperand> &Addr, 556 const TargetRegisterClass *RC, 557 MachineInstr::mmo_iterator MMOBegin, 558 MachineInstr::mmo_iterator MMOEnd, 559 SmallVectorImpl<MachineInstr*> &NewMIs) const; 560 561 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 562 MachineBasicBlock::iterator MI, 563 const std::vector<CalleeSavedInfo> &CSI) const; 564 565 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 566 MachineBasicBlock::iterator MI, 567 const std::vector<CalleeSavedInfo> &CSI) const; 568 569 /// foldMemoryOperand - If this target supports it, fold a load or store of 570 /// the specified stack slot into the specified machine instruction for the 571 /// specified operand(s). If this is possible, the target should perform the 572 /// folding and return true, otherwise it should return false. If it folds 573 /// the instruction, it is likely that the MachineInstruction the iterator 574 /// references has been changed. 575 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 576 MachineInstr* MI, 577 const SmallVectorImpl<unsigned> &Ops, 578 int FrameIndex) const; 579 580 /// foldMemoryOperand - Same as the previous version except it allows folding 581 /// of any load and store from / to any address, not just from a specific 582 /// stack slot. 583 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 584 MachineInstr* MI, 585 const SmallVectorImpl<unsigned> &Ops, 586 MachineInstr* LoadMI) const; 587 588 /// canFoldMemoryOperand - Returns true if the specified load / store is 589 /// folding is possible. 590 virtual bool canFoldMemoryOperand(const MachineInstr*, 591 const SmallVectorImpl<unsigned> &) const; 592 593 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 594 /// a store or a load and a store into two or more instruction. If this is 595 /// possible, returns true as well as the new instructions by reference. 596 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 597 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 598 SmallVectorImpl<MachineInstr*> &NewMIs) const; 599 600 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 601 SmallVectorImpl<SDNode*> &NewNodes) const; 602 603 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 604 /// instruction after load / store are unfolded from an instruction of the 605 /// specified opcode. It returns zero if the specified unfolding is not 606 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 607 /// index of the operand which will hold the register holding the loaded 608 /// value. 609 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 610 bool UnfoldLoad, bool UnfoldStore, 611 unsigned *LoadRegIndex = 0) const; 612 613 virtual 614 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 615 616 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 617 /// instruction that defines the specified register class. 618 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 619 620 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 621 // specified machine instruction. 622 // 623 unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const { 624 return TID->TSFlags >> X86II::OpcodeShift; 625 } 626 unsigned char getBaseOpcodeFor(unsigned Opcode) const { 627 return getBaseOpcodeFor(&get(Opcode)); 628 } 629 630 static bool isX86_64NonExtLowByteReg(unsigned reg) { 631 return (reg == X86::SPL || reg == X86::BPL || 632 reg == X86::SIL || reg == X86::DIL); 633 } 634 635 static unsigned sizeOfImm(const TargetInstrDesc *Desc); 636 static bool isX86_64ExtendedReg(const MachineOperand &MO); 637 static unsigned determineREX(const MachineInstr &MI); 638 639 /// GetInstSize - Returns the size of the specified MachineInstr. 640 /// 641 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 642 643 /// getGlobalBaseReg - Return a virtual register initialized with the 644 /// the global base register value. Output instructions required to 645 /// initialize the register in the function entry block, if necessary. 646 /// 647 unsigned getGlobalBaseReg(MachineFunction *MF) const; 648 649private: 650 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc, 651 MachineFunction::iterator &MFI, 652 MachineBasicBlock::iterator &MBBI, 653 LiveVariables *LV) const; 654 655 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 656 MachineInstr* MI, 657 unsigned OpNum, 658 const SmallVectorImpl<MachineOperand> &MOs, 659 unsigned Size, unsigned Alignment) const; 660 661 /// isFrameOperand - Return true and the FrameIndex if the specified 662 /// operand and follow operands form a reference to the stack frame. 663 bool isFrameOperand(const MachineInstr *MI, unsigned int Op, 664 int &FrameIndex) const; 665}; 666 667} // End llvm namespace 668 669#endif 670