X86InstrInfo.h revision 856ba76200ec2302f2fe500bc507f426c7d566c8 
1//===- X86InstructionInfo.h - X86 Instruction Information ---------*-C++-*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef X86INSTRUCTIONINFO_H
15#define X86INSTRUCTIONINFO_H
16
17#include "llvm/Target/TargetInstrInfo.h"
18#include "X86RegisterInfo.h"
19
20/// X86II - This namespace holds all of the target specific flags that
21/// instruction info tracks.
22///
23namespace X86II {
24  enum {
25    //===------------------------------------------------------------------===//
26    // Instruction types.  These are the standard/most common forms for X86
27    // instructions.
28    //
29
30    // PseudoFrm - This represents an instruction that is a pseudo instruction
31    // or one that has not been implemented yet.  It is illegal to code generate
32    // it, but tolerated for intermediate implementation stages.
33    Pseudo         = 0,
34
35    /// Raw - This form is for instructions that don't have any operands, so
36    /// they are just a fixed opcode value, like 'leave'.
37    RawFrm         = 1,
38
39    /// AddRegFrm - This form is used for instructions like 'push r32' that have
40    /// their one register operand added to their opcode.
41    AddRegFrm      = 2,
42
43    /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
44    /// to specify a destination, which in this case is a register.
45    ///
46    MRMDestReg     = 3,
47
48    /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
49    /// to specify a destination, which in this case is memory.
50    ///
51    MRMDestMem     = 4,
52
53    /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
54    /// to specify a source, which in this case is a register.
55    ///
56    MRMSrcReg      = 5,
57
58    /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
59    /// to specify a source, which in this case is memory.
60    ///
61    MRMSrcMem      = 6,
62
63    /// MRMS[0-7][rm] - These forms are used to represent instructions that use
64    /// a Mod/RM byte, and use the middle field to hold extended opcode
65    /// information.  In the intel manual these are represented as /0, /1, ...
66    ///
67
68    // First, instructions that operate on a register r/m operand...
69    MRMS0r = 16,  MRMS1r = 17,  MRMS2r = 18,  MRMS3r = 19, // Format /0 /1 /2 /3
70    MRMS4r = 20,  MRMS5r = 21,  MRMS6r = 22,  MRMS7r = 23, // Format /4 /5 /6 /7
71
72    // Next, instructions that operate on a memory r/m operand...
73    MRMS0m = 24,  MRMS1m = 25,  MRMS2m = 26,  MRMS3m = 27, // Format /0 /1 /2 /3
74    MRMS4m = 28,  MRMS5m = 29,  MRMS6m = 30,  MRMS7m = 31, // Format /4 /5 /6 /7
75
76    FormMask       = 31,
77
78    //===------------------------------------------------------------------===//
79    // Actual flags...
80
81    // OpSize - Set if this instruction requires an operand size prefix (0x66),
82    // which most often indicates that the instruction operates on 16 bit data
83    // instead of 32 bit data.
84    OpSize      = 1 << 5,
85
86    // Op0Mask - There are several prefix bytes that are used to form two byte
87    // opcodes.  These are currently 0x0F, and 0xD8-0xDF.  This mask is used to
88    // obtain the setting of this field.  If no bits in this field is set, there
89    // is no prefix byte for obtaining a multibyte opcode.
90    //
91    Op0Shift    = 6,
92    Op0Mask     = 0xF << Op0Shift,
93
94    // TB - TwoByte - Set if this instruction has a two byte opcode, which
95    // starts with a 0x0F byte before the real opcode.
96    TB          = 1 << Op0Shift,
97
98    // D8-DF - These escape opcodes are used by the floating point unit.  These
99    // values must remain sequential.
100    D8 = 2 << Op0Shift,   D9 = 3 << Op0Shift,
101    DA = 4 << Op0Shift,   DB = 5 << Op0Shift,
102    DC = 6 << Op0Shift,   DD = 7 << Op0Shift,
103    DE = 8 << Op0Shift,   DF = 9 << Op0Shift,
104
105    //===------------------------------------------------------------------===//
106    // This three-bit field describes the size of a memory operand.  Zero is
107    // unused so that we can tell if we forgot to set a value.
108    ArgShift = 10,
109    ArgMask  = 7 << ArgShift,
110    Arg8     = 1 << ArgShift,
111    Arg16    = 2 << ArgShift,
112    Arg32    = 3 << ArgShift,
113    Arg64    = 4 << ArgShift,  // 64 bit int argument for FILD64
114    ArgF32   = 5 << ArgShift,
115    ArgF64   = 6 << ArgShift,
116    ArgF80   = 7 << ArgShift,
117
118    //===------------------------------------------------------------------===//
119    // FP Instruction Classification...  Zero is non-fp instruction.
120
121    // FPTypeMask - Mask for all of the FP types...
122    FPTypeShift = 13,
123    FPTypeMask  = 7 << FPTypeShift,
124
125    // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
126    ZeroArgFP  = 1 << FPTypeShift,
127
128    // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
129    OneArgFP   = 2 << FPTypeShift,
130
131    // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
132    // result back to ST(0).  For example, fcos, fsqrt, etc.
133    //
134    OneArgFPRW = 3 << FPTypeShift,
135
136    // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
137    // explicit argument, storing the result to either ST(0) or the implicit
138    // argument.  For example: fadd, fsub, fmul, etc...
139    TwoArgFP   = 4 << FPTypeShift,
140
141    // SpecialFP - Special instruction forms.  Dispatch by opcode explicitly.
142    SpecialFP  = 5 << FPTypeShift,
143
144    // PrintImplUses - Print out implicit uses in the assembly output.
145    PrintImplUses = 1 << 16,
146
147    OpcodeShift   = 17,
148    OpcodeMask    = 0xFF << OpcodeShift,
149    // Bits 25 -> 31 are unused
150  };
151}
152
153class X86InstrInfo : public TargetInstrInfo {
154  const X86RegisterInfo RI;
155public:
156  X86InstrInfo();
157
158  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
159  /// such, whenever a client has an instance of instruction info, it should
160  /// always be able to get register info as well (through this method).
161  ///
162  virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
163
164  /// createNOPinstr - returns the target's implementation of NOP, which is
165  /// usually a pseudo-instruction, implemented by a degenerate version of
166  /// another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0'
167  ///
168  MachineInstr* createNOPinstr() const;
169
170  /// isNOPinstr - not having a special NOP opcode, we need to know if a given
171  /// instruction is interpreted as an `official' NOP instr, i.e., there may be
172  /// more than one way to `do nothing' but only one canonical way to slack off.
173  ///
174  bool isNOPinstr(const MachineInstr &MI) const;
175
176  // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
177  // specified opcode number.
178  //
179  unsigned char getBaseOpcodeFor(unsigned Opcode) const {
180    return get(Opcode).TSFlags >> X86II::OpcodeShift;
181  }
182};
183
184#endif
185