X86InstrInfo.h revision ac5e887a6cf0a6182664d8c11beb0d2270272b02
1//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86INSTRUCTIONINFO_H 15#define X86INSTRUCTIONINFO_H 16 17#include "llvm/Target/TargetInstrInfo.h" 18#include "X86.h" 19#include "X86RegisterInfo.h" 20#include "llvm/ADT/DenseMap.h" 21#include "llvm/Target/TargetRegisterInfo.h" 22 23namespace llvm { 24 class X86RegisterInfo; 25 class X86TargetMachine; 26 27namespace X86 { 28 // X86 specific condition code. These correspond to X86_*_COND in 29 // X86InstrInfo.td. They must be kept in synch. 30 enum CondCode { 31 COND_A = 0, 32 COND_AE = 1, 33 COND_B = 2, 34 COND_BE = 3, 35 COND_E = 4, 36 COND_G = 5, 37 COND_GE = 6, 38 COND_L = 7, 39 COND_LE = 8, 40 COND_NE = 9, 41 COND_NO = 10, 42 COND_NP = 11, 43 COND_NS = 12, 44 COND_O = 13, 45 COND_P = 14, 46 COND_S = 15, 47 48 // Artificial condition codes. These are used by AnalyzeBranch 49 // to indicate a block terminated with two conditional branches to 50 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 51 // which can't be represented on x86 with a single condition. These 52 // are never used in MachineInstrs. 53 COND_NE_OR_P, 54 COND_NP_OR_E, 55 56 COND_INVALID 57 }; 58 59 // Turn condition code into conditional branch opcode. 60 unsigned GetCondBranchFromCond(CondCode CC); 61 62 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 63 /// e.g. turning COND_E to COND_NE. 64 CondCode GetOppositeBranchCondition(X86::CondCode CC); 65 66} 67 68/// X86II - This namespace holds all of the target specific flags that 69/// instruction info tracks. 70/// 71namespace X86II { 72 enum { 73 //===------------------------------------------------------------------===// 74 // X86 Specific MachineOperand flags. 75 76 MO_NO_FLAG = 0, 77 78 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 79 /// relocation of: 80 /// $SYMBOL_LABEL + [. - PICBASELABEL] 81 MO_GOT_ABSOLUTE_ADDRESS = 1, 82 83 84 //===------------------------------------------------------------------===// 85 // Instruction encodings. These are the standard/most common forms for X86 86 // instructions. 87 // 88 89 // PseudoFrm - This represents an instruction that is a pseudo instruction 90 // or one that has not been implemented yet. It is illegal to code generate 91 // it, but tolerated for intermediate implementation stages. 92 Pseudo = 0, 93 94 /// Raw - This form is for instructions that don't have any operands, so 95 /// they are just a fixed opcode value, like 'leave'. 96 RawFrm = 1, 97 98 /// AddRegFrm - This form is used for instructions like 'push r32' that have 99 /// their one register operand added to their opcode. 100 AddRegFrm = 2, 101 102 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 103 /// to specify a destination, which in this case is a register. 104 /// 105 MRMDestReg = 3, 106 107 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 108 /// to specify a destination, which in this case is memory. 109 /// 110 MRMDestMem = 4, 111 112 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 113 /// to specify a source, which in this case is a register. 114 /// 115 MRMSrcReg = 5, 116 117 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 118 /// to specify a source, which in this case is memory. 119 /// 120 MRMSrcMem = 6, 121 122 /// MRM[0-7][rm] - These forms are used to represent instructions that use 123 /// a Mod/RM byte, and use the middle field to hold extended opcode 124 /// information. In the intel manual these are represented as /0, /1, ... 125 /// 126 127 // First, instructions that operate on a register r/m operand... 128 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 129 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 130 131 // Next, instructions that operate on a memory r/m operand... 132 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 133 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 134 135 // MRMInitReg - This form is used for instructions whose source and 136 // destinations are the same register. 137 MRMInitReg = 32, 138 139 FormMask = 63, 140 141 //===------------------------------------------------------------------===// 142 // Actual flags... 143 144 // OpSize - Set if this instruction requires an operand size prefix (0x66), 145 // which most often indicates that the instruction operates on 16 bit data 146 // instead of 32 bit data. 147 OpSize = 1 << 6, 148 149 // AsSize - Set if this instruction requires an operand size prefix (0x67), 150 // which most often indicates that the instruction address 16 bit address 151 // instead of 32 bit address (or 32 bit address in 64 bit mode). 152 AdSize = 1 << 7, 153 154 //===------------------------------------------------------------------===// 155 // Op0Mask - There are several prefix bytes that are used to form two byte 156 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 157 // used to obtain the setting of this field. If no bits in this field is 158 // set, there is no prefix byte for obtaining a multibyte opcode. 159 // 160 Op0Shift = 8, 161 Op0Mask = 0xF << Op0Shift, 162 163 // TB - TwoByte - Set if this instruction has a two byte opcode, which 164 // starts with a 0x0F byte before the real opcode. 165 TB = 1 << Op0Shift, 166 167 // REP - The 0xF3 prefix byte indicating repetition of the following 168 // instruction. 169 REP = 2 << Op0Shift, 170 171 // D8-DF - These escape opcodes are used by the floating point unit. These 172 // values must remain sequential. 173 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 174 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 175 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 176 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 177 178 // XS, XD - These prefix codes are for single and double precision scalar 179 // floating point operations performed in the SSE registers. 180 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 181 182 // T8, TA - Prefix after the 0x0F prefix. 183 T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 184 185 //===------------------------------------------------------------------===// 186 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 187 // They are used to specify GPRs and SSE registers, 64-bit operand size, 188 // etc. We only cares about REX.W and REX.R bits and only the former is 189 // statically determined. 190 // 191 REXShift = 12, 192 REX_W = 1 << REXShift, 193 194 //===------------------------------------------------------------------===// 195 // This three-bit field describes the size of an immediate operand. Zero is 196 // unused so that we can tell if we forgot to set a value. 197 ImmShift = 13, 198 ImmMask = 7 << ImmShift, 199 Imm8 = 1 << ImmShift, 200 Imm16 = 2 << ImmShift, 201 Imm32 = 3 << ImmShift, 202 Imm64 = 4 << ImmShift, 203 204 //===------------------------------------------------------------------===// 205 // FP Instruction Classification... Zero is non-fp instruction. 206 207 // FPTypeMask - Mask for all of the FP types... 208 FPTypeShift = 16, 209 FPTypeMask = 7 << FPTypeShift, 210 211 // NotFP - The default, set for instructions that do not use FP registers. 212 NotFP = 0 << FPTypeShift, 213 214 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 215 ZeroArgFP = 1 << FPTypeShift, 216 217 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 218 OneArgFP = 2 << FPTypeShift, 219 220 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 221 // result back to ST(0). For example, fcos, fsqrt, etc. 222 // 223 OneArgFPRW = 3 << FPTypeShift, 224 225 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 226 // explicit argument, storing the result to either ST(0) or the implicit 227 // argument. For example: fadd, fsub, fmul, etc... 228 TwoArgFP = 4 << FPTypeShift, 229 230 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 231 // explicit argument, but have no destination. Example: fucom, fucomi, ... 232 CompareFP = 5 << FPTypeShift, 233 234 // CondMovFP - "2 operand" floating point conditional move instructions. 235 CondMovFP = 6 << FPTypeShift, 236 237 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 238 SpecialFP = 7 << FPTypeShift, 239 240 // Lock prefix 241 LOCKShift = 19, 242 LOCK = 1 << LOCKShift, 243 244 // Segment override prefixes. Currently we just need ability to address 245 // stuff in gs and fs segments. 246 SegOvrShift = 20, 247 SegOvrMask = 3 << SegOvrShift, 248 FS = 1 << SegOvrShift, 249 GS = 2 << SegOvrShift, 250 251 // Bits 22 -> 23 are unused 252 OpcodeShift = 24, 253 OpcodeMask = 0xFF << OpcodeShift 254 }; 255} 256 257const int X86AddrNumOperands = 5; 258 259inline static bool isScale(const MachineOperand &MO) { 260 return MO.isImm() && 261 (MO.getImm() == 1 || MO.getImm() == 2 || 262 MO.getImm() == 4 || MO.getImm() == 8); 263} 264 265inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { 266 if (MI->getOperand(Op).isFI()) return true; 267 return Op+4 <= MI->getNumOperands() && 268 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 269 MI->getOperand(Op+2).isReg() && 270 (MI->getOperand(Op+3).isImm() || 271 MI->getOperand(Op+3).isGlobal() || 272 MI->getOperand(Op+3).isCPI() || 273 MI->getOperand(Op+3).isJTI()); 274} 275 276inline static bool isMem(const MachineInstr *MI, unsigned Op) { 277 if (MI->getOperand(Op).isFI()) return true; 278 return Op+5 <= MI->getNumOperands() && 279 MI->getOperand(Op+4).isReg() && 280 isLeaMem(MI, Op); 281} 282 283class X86InstrInfo : public TargetInstrInfoImpl { 284 X86TargetMachine &TM; 285 const X86RegisterInfo RI; 286 287 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 288 /// RegOp2MemOpTable2 - Load / store folding opcode maps. 289 /// 290 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr; 291 DenseMap<unsigned*, unsigned> RegOp2MemOpTable0; 292 DenseMap<unsigned*, unsigned> RegOp2MemOpTable1; 293 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2; 294 295 /// MemOp2RegOpTable - Load / store unfolding opcode map. 296 /// 297 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 298 299public: 300 explicit X86InstrInfo(X86TargetMachine &tm); 301 302 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 303 /// such, whenever a client has an instance of instruction info, it should 304 /// always be able to get register info as well (through this method). 305 /// 306 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 307 308 /// Return true if the instruction is a register to register move and return 309 /// the source and dest operands and their sub-register indices by reference. 310 virtual bool isMoveInstr(const MachineInstr &MI, 311 unsigned &SrcReg, unsigned &DstReg, 312 unsigned &SrcSubIdx, unsigned &DstSubIdx) const; 313 314 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 315 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; 316 317 bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const; 318 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 319 unsigned DestReg, const MachineInstr *Orig) const; 320 321 bool isInvariantLoad(const MachineInstr *MI) const; 322 323 /// convertToThreeAddress - This method must be implemented by targets that 324 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 325 /// may be able to convert a two-address instruction into a true 326 /// three-address instruction on demand. This allows the X86 target (for 327 /// example) to convert ADD and SHL instructions into LEA instructions if they 328 /// would require register copies due to two-addressness. 329 /// 330 /// This method returns a null pointer if the transformation cannot be 331 /// performed, otherwise it returns the new instruction. 332 /// 333 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 334 MachineBasicBlock::iterator &MBBI, 335 LiveVariables *LV) const; 336 337 /// commuteInstruction - We have a few instructions that must be hacked on to 338 /// commute them. 339 /// 340 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 341 342 // Branch analysis. 343 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 344 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 345 MachineBasicBlock *&FBB, 346 SmallVectorImpl<MachineOperand> &Cond, 347 bool AllowModify) const; 348 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 349 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 350 MachineBasicBlock *FBB, 351 const SmallVectorImpl<MachineOperand> &Cond) const; 352 virtual bool copyRegToReg(MachineBasicBlock &MBB, 353 MachineBasicBlock::iterator MI, 354 unsigned DestReg, unsigned SrcReg, 355 const TargetRegisterClass *DestRC, 356 const TargetRegisterClass *SrcRC) const; 357 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 358 MachineBasicBlock::iterator MI, 359 unsigned SrcReg, bool isKill, int FrameIndex, 360 const TargetRegisterClass *RC) const; 361 362 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 363 SmallVectorImpl<MachineOperand> &Addr, 364 const TargetRegisterClass *RC, 365 SmallVectorImpl<MachineInstr*> &NewMIs) const; 366 367 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 368 MachineBasicBlock::iterator MI, 369 unsigned DestReg, int FrameIndex, 370 const TargetRegisterClass *RC) const; 371 372 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 373 SmallVectorImpl<MachineOperand> &Addr, 374 const TargetRegisterClass *RC, 375 SmallVectorImpl<MachineInstr*> &NewMIs) const; 376 377 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 378 MachineBasicBlock::iterator MI, 379 const std::vector<CalleeSavedInfo> &CSI) const; 380 381 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 382 MachineBasicBlock::iterator MI, 383 const std::vector<CalleeSavedInfo> &CSI) const; 384 385 /// foldMemoryOperand - If this target supports it, fold a load or store of 386 /// the specified stack slot into the specified machine instruction for the 387 /// specified operand(s). If this is possible, the target should perform the 388 /// folding and return true, otherwise it should return false. If it folds 389 /// the instruction, it is likely that the MachineInstruction the iterator 390 /// references has been changed. 391 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 392 MachineInstr* MI, 393 const SmallVectorImpl<unsigned> &Ops, 394 int FrameIndex) const; 395 396 /// foldMemoryOperand - Same as the previous version except it allows folding 397 /// of any load and store from / to any address, not just from a specific 398 /// stack slot. 399 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 400 MachineInstr* MI, 401 const SmallVectorImpl<unsigned> &Ops, 402 MachineInstr* LoadMI) const; 403 404 /// canFoldMemoryOperand - Returns true if the specified load / store is 405 /// folding is possible. 406 virtual bool canFoldMemoryOperand(const MachineInstr*, 407 const SmallVectorImpl<unsigned> &) const; 408 409 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 410 /// a store or a load and a store into two or more instruction. If this is 411 /// possible, returns true as well as the new instructions by reference. 412 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 413 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 414 SmallVectorImpl<MachineInstr*> &NewMIs) const; 415 416 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 417 SmallVectorImpl<SDNode*> &NewNodes) const; 418 419 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 420 /// instruction after load / store are unfolded from an instruction of the 421 /// specified opcode. It returns zero if the specified unfolding is not 422 /// possible. 423 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 424 bool UnfoldLoad, bool UnfoldStore) const; 425 426 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const; 427 virtual 428 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 429 430 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 431 /// instruction that defines the specified register class. 432 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 433 434 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 435 // specified machine instruction. 436 // 437 unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const { 438 return TID->TSFlags >> X86II::OpcodeShift; 439 } 440 unsigned char getBaseOpcodeFor(unsigned Opcode) const { 441 return getBaseOpcodeFor(&get(Opcode)); 442 } 443 444 static bool isX86_64NonExtLowByteReg(unsigned reg) { 445 return (reg == X86::SPL || reg == X86::BPL || 446 reg == X86::SIL || reg == X86::DIL); 447 } 448 449 static unsigned sizeOfImm(const TargetInstrDesc *Desc); 450 static bool isX86_64ExtendedReg(const MachineOperand &MO); 451 static unsigned determineREX(const MachineInstr &MI); 452 453 /// GetInstSize - Returns the size of the specified MachineInstr. 454 /// 455 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 456 457 /// getGlobalBaseReg - Return a virtual register initialized with the 458 /// the global base register value. Output instructions required to 459 /// initialize the register in the function entry block, if necessary. 460 /// 461 unsigned getGlobalBaseReg(MachineFunction *MF) const; 462 463private: 464 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 465 MachineInstr* MI, 466 unsigned OpNum, 467 const SmallVectorImpl<MachineOperand> &MOs) const; 468}; 469 470} // End llvm namespace 471 472#endif 473