X86InstrInfo.h revision c3d57b179c33ef010ebbff003ce8c5d908cf9c01
12a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 22a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// 32a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// The LLVM Compiler Infrastructure 42a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// 52a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// This file is distributed under the University of Illinois Open Source 62a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// License. See LICENSE.TXT for details. 72a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// 8c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)//===----------------------------------------------------------------------===// 92a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// 102a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// This file contains the X86 implementation of the TargetInstrInfo class. 112a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// 122a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)//===----------------------------------------------------------------------===// 132a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 142a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)#ifndef X86INSTRUCTIONINFO_H 15c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#define X86INSTRUCTIONINFO_H 162a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 177d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles)#include "llvm/Target/TargetInstrInfo.h" 18eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch#include "X86.h" 192a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)#include "X86RegisterInfo.h" 202a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)#include "llvm/ADT/DenseMap.h" 212a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 222a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)namespace llvm { 232a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) class X86RegisterInfo; 242a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) class X86TargetMachine; 252a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 262a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)namespace X86 { 272a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // X86 specific condition code. These correspond to X86_*_COND in 282a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // X86InstrInfo.td. They must be kept in synch. 292a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) enum CondCode { 302a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) COND_A = 0, 312a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) COND_AE = 1, 327d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) COND_B = 2, 337d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) COND_BE = 3, 342a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) COND_E = 4, 352a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) COND_G = 5, 367d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) COND_GE = 6, 377d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) COND_L = 7, 382a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) COND_LE = 8, 392a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) COND_NE = 9, 402a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) COND_NO = 10, 412a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) COND_NP = 11, 422a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) COND_NS = 12, 432a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) COND_O = 13, 44c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) COND_P = 14, 452a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) COND_S = 15, 462a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 472a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // Artificial condition codes. These are used by AnalyzeBranch 482a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // to indicate a block terminated with two conditional branches to 492a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 502a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // which can't be represented on x86 with a single condition. These 512a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // are never used in MachineInstrs. 522a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) COND_NE_OR_P, 532a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) COND_NP_OR_E, 542a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 552a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) COND_INVALID 562a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) }; 572a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 582a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // Turn condition code into conditional branch opcode. 597d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) unsigned GetCondBranchFromCond(CondCode CC); 607d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) 617d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) /// GetOppositeBranchCondition - Return the inverse of the specified cond, 627d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) /// e.g. turning COND_E to COND_NE. 637d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) CondCode GetOppositeBranchCondition(X86::CondCode CC); 642a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 652a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)} 662a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 67c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)/// X86II - This namespace holds all of the target specific flags that 68c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)/// instruction info tracks. 69c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)/// 70c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)namespace X86II { 712a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// Target Operand Flag enum. 722a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) enum TOF { 732a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) //===------------------------------------------------------------------===// 742a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // X86 Specific MachineOperand flags. 752a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 762a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MO_NO_FLAG, 772a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 78c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 792a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// relocation of: 802a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// SYMBOL_LABEL + [. - PICBASELABEL] 812a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MO_GOT_ABSOLUTE_ADDRESS, 822a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 832a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 842a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// immediate should get the value of the symbol minus the PIC base label: 857d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) /// SYMBOL_LABEL - PICBASELABEL 867d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) MO_PIC_BASE_OFFSET, 877d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) 887d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) /// MO_GOT - On a symbol operand this indicates that the immediate is the 892a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// offset to the GOT entry for the symbol name from the base of the GOT. 902a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 912a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// See the X86-64 ELF ABI supplement for more details. 922a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// SYMBOL_LABEL @GOT 932a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MO_GOT, 94c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 952a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 962a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// the offset to the location of the symbol name from the base of the GOT. 972a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 982a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// See the X86-64 ELF ABI supplement for more details. 992a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// SYMBOL_LABEL @GOTOFF 1002a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MO_GOTOFF, 1012a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 1022a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 1032a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// offset to the GOT entry for the symbol name from the current code 1042a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// location. 1052a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 1062a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// See the X86-64 ELF ABI supplement for more details. 1072a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// SYMBOL_LABEL @GOTPCREL 1082a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MO_GOTPCREL, 1092a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 1102a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// MO_PLT - On a symbol operand this indicates that the immediate is 1112a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// offset to the PLT entry of symbol name from the current code location. 1122a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 1132a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// See the X86-64 ELF ABI supplement for more details. 1142a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// SYMBOL_LABEL @PLT 1152a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MO_PLT, 1162a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 1172a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// MO_TLSGD - On a symbol operand this indicates that the immediate is 1182a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// some TLS offset. 1192a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 1202a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// See 'ELF Handling for Thread-Local Storage' for more details. 1212a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// SYMBOL_LABEL @TLSGD 1222a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MO_TLSGD, 1232a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 1242a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 1252a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// some TLS offset. 1262a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 1272a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// See 'ELF Handling for Thread-Local Storage' for more details. 1282a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// SYMBOL_LABEL @GOTTPOFF 1292a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MO_GOTTPOFF, 1302a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 1312a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 1322a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// some TLS offset. 1332a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 1342a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// See 'ELF Handling for Thread-Local Storage' for more details. 1352a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// SYMBOL_LABEL @INDNTPOFF 1362a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MO_INDNTPOFF, 1372a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 1382a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// MO_TPOFF - On a symbol operand this indicates that the immediate is 1392a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// some TLS offset. 1402a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 1412a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// See 'ELF Handling for Thread-Local Storage' for more details. 1422a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// SYMBOL_LABEL @TPOFF 1432a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MO_TPOFF, 1442a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 1452a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 1462a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// some TLS offset. 1472a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 1482a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// See 'ELF Handling for Thread-Local Storage' for more details. 1492a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// SYMBOL_LABEL @NTPOFF 1502a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MO_NTPOFF, 1512a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 1522a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 1532a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// reference is actually to the "__imp_FOO" symbol. This is used for 1542a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// dllimport linkage on windows. 1552a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MO_DLLIMPORT, 1562a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 1572a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the 1582a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// reference is actually to the "FOO$stub" symbol. This is used for calls 1592a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// and jumps to external functions on Tiger and before. 1602a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MO_DARWIN_STUB, 1612a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 1622a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 1632a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 1642a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 1652a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MO_DARWIN_NONLAZY, 1662a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 1672a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 1682a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 169eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 1702a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MO_DARWIN_NONLAZY_PIC_BASE, 1712a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 1722a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this 1732a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE", 1742a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// which is a PIC-base-relative reference to a hidden dyld lazy pointer 175c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// stub. 176c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, 177c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 178c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// MO_TLVP - On a symbol operand this indicates that the immediate is 179c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// some TLS offset. 180c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// 181c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// This is the TLS offset for the Darwin TLS mechanism. 182c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) MO_TLVP, 1832a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 1842a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate 1852a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// is some TLS offset from the picbase. 1862a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 1872a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// This is the 32-bit TLS offset for Darwin TLS in PIC mode. 1882a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MO_TLVP_PIC_BASE 1892a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) }; 1902a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)} 1917d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) 1927d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles)/// isGlobalStubReference - Return true if the specified TargetFlag operand is 1932a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)/// a reference to a stub for a global, not the global itself. 1942a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)inline static bool isGlobalStubReference(unsigned char TargetFlag) { 1952a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) switch (TargetFlag) { 1962a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) case X86II::MO_DLLIMPORT: // dllimport stub. 1972a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) case X86II::MO_GOTPCREL: // rip-relative GOT reference. 1982a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) case X86II::MO_GOT: // normal GOT reference. 1992a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. 2002a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. 2012a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref. 2022a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return true; 2032a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) default: 2042a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return false; 2052a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 2062a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)} 207eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch 2082a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)/// isGlobalRelativeToPICBase - Return true if the specified global value 2092a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this 2102a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)/// is true, the addressing mode has the PIC base register added in (e.g. EBX). 2112a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { 212c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) switch (TargetFlag) { 213c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) case X86II::MO_GOTOFF: // isPICStyleGOT: local global. 214c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) case X86II::MO_GOT: // isPICStyleGOT: other global. 215c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. 216c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. 217c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global. 218c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) case X86II::MO_TLVP: // ??? Pretty sure.. 219c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) return true; 220c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) default: 221c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) return false; 222c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) } 223c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)} 2242a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 2252a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)/// X86II - This namespace holds all of the target specific flags that 2262a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)/// instruction info tracks. 227/// 228namespace X86II { 229 enum { 230 //===------------------------------------------------------------------===// 231 // Instruction encodings. These are the standard/most common forms for X86 232 // instructions. 233 // 234 235 // PseudoFrm - This represents an instruction that is a pseudo instruction 236 // or one that has not been implemented yet. It is illegal to code generate 237 // it, but tolerated for intermediate implementation stages. 238 Pseudo = 0, 239 240 /// Raw - This form is for instructions that don't have any operands, so 241 /// they are just a fixed opcode value, like 'leave'. 242 RawFrm = 1, 243 244 /// AddRegFrm - This form is used for instructions like 'push r32' that have 245 /// their one register operand added to their opcode. 246 AddRegFrm = 2, 247 248 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 249 /// to specify a destination, which in this case is a register. 250 /// 251 MRMDestReg = 3, 252 253 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 254 /// to specify a destination, which in this case is memory. 255 /// 256 MRMDestMem = 4, 257 258 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 259 /// to specify a source, which in this case is a register. 260 /// 261 MRMSrcReg = 5, 262 263 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 264 /// to specify a source, which in this case is memory. 265 /// 266 MRMSrcMem = 6, 267 268 /// MRM[0-7][rm] - These forms are used to represent instructions that use 269 /// a Mod/RM byte, and use the middle field to hold extended opcode 270 /// information. In the intel manual these are represented as /0, /1, ... 271 /// 272 273 // First, instructions that operate on a register r/m operand... 274 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 275 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 276 277 // Next, instructions that operate on a memory r/m operand... 278 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 279 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 280 281 // MRMInitReg - This form is used for instructions whose source and 282 // destinations are the same register. 283 MRMInitReg = 32, 284 285 //// MRM_C1 - A mod/rm byte of exactly 0xC1. 286 MRM_C1 = 33, 287 MRM_C2 = 34, 288 MRM_C3 = 35, 289 MRM_C4 = 36, 290 MRM_C8 = 37, 291 MRM_C9 = 38, 292 MRM_E8 = 39, 293 MRM_F0 = 40, 294 MRM_F8 = 41, 295 MRM_F9 = 42, 296 297 FormMask = 63, 298 299 //===------------------------------------------------------------------===// 300 // Actual flags... 301 302 // OpSize - Set if this instruction requires an operand size prefix (0x66), 303 // which most often indicates that the instruction operates on 16 bit data 304 // instead of 32 bit data. 305 OpSize = 1 << 6, 306 307 // AsSize - Set if this instruction requires an operand size prefix (0x67), 308 // which most often indicates that the instruction address 16 bit address 309 // instead of 32 bit address (or 32 bit address in 64 bit mode). 310 AdSize = 1 << 7, 311 312 //===------------------------------------------------------------------===// 313 // Op0Mask - There are several prefix bytes that are used to form two byte 314 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 315 // used to obtain the setting of this field. If no bits in this field is 316 // set, there is no prefix byte for obtaining a multibyte opcode. 317 // 318 Op0Shift = 8, 319 Op0Mask = 0xF << Op0Shift, 320 321 // TB - TwoByte - Set if this instruction has a two byte opcode, which 322 // starts with a 0x0F byte before the real opcode. 323 TB = 1 << Op0Shift, 324 325 // REP - The 0xF3 prefix byte indicating repetition of the following 326 // instruction. 327 REP = 2 << Op0Shift, 328 329 // D8-DF - These escape opcodes are used by the floating point unit. These 330 // values must remain sequential. 331 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 332 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 333 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 334 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 335 336 // XS, XD - These prefix codes are for single and double precision scalar 337 // floating point operations performed in the SSE registers. 338 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 339 340 // T8, TA - Prefix after the 0x0F prefix. 341 T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 342 343 // TF - Prefix before and after 0x0F 344 TF = 15 << Op0Shift, 345 346 //===------------------------------------------------------------------===// 347 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 348 // They are used to specify GPRs and SSE registers, 64-bit operand size, 349 // etc. We only cares about REX.W and REX.R bits and only the former is 350 // statically determined. 351 // 352 REXShift = 12, 353 REX_W = 1 << REXShift, 354 355 //===------------------------------------------------------------------===// 356 // This three-bit field describes the size of an immediate operand. Zero is 357 // unused so that we can tell if we forgot to set a value. 358 ImmShift = 13, 359 ImmMask = 7 << ImmShift, 360 Imm8 = 1 << ImmShift, 361 Imm8PCRel = 2 << ImmShift, 362 Imm16 = 3 << ImmShift, 363 Imm32 = 4 << ImmShift, 364 Imm32PCRel = 5 << ImmShift, 365 Imm64 = 6 << ImmShift, 366 367 //===------------------------------------------------------------------===// 368 // FP Instruction Classification... Zero is non-fp instruction. 369 370 // FPTypeMask - Mask for all of the FP types... 371 FPTypeShift = 16, 372 FPTypeMask = 7 << FPTypeShift, 373 374 // NotFP - The default, set for instructions that do not use FP registers. 375 NotFP = 0 << FPTypeShift, 376 377 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 378 ZeroArgFP = 1 << FPTypeShift, 379 380 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 381 OneArgFP = 2 << FPTypeShift, 382 383 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 384 // result back to ST(0). For example, fcos, fsqrt, etc. 385 // 386 OneArgFPRW = 3 << FPTypeShift, 387 388 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 389 // explicit argument, storing the result to either ST(0) or the implicit 390 // argument. For example: fadd, fsub, fmul, etc... 391 TwoArgFP = 4 << FPTypeShift, 392 393 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 394 // explicit argument, but have no destination. Example: fucom, fucomi, ... 395 CompareFP = 5 << FPTypeShift, 396 397 // CondMovFP - "2 operand" floating point conditional move instructions. 398 CondMovFP = 6 << FPTypeShift, 399 400 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 401 SpecialFP = 7 << FPTypeShift, 402 403 // Lock prefix 404 LOCKShift = 19, 405 LOCK = 1 << LOCKShift, 406 407 // Segment override prefixes. Currently we just need ability to address 408 // stuff in gs and fs segments. 409 SegOvrShift = 20, 410 SegOvrMask = 3 << SegOvrShift, 411 FS = 1 << SegOvrShift, 412 GS = 2 << SegOvrShift, 413 414 // Execution domain for SSE instructions in bits 22, 23. 415 // 0 in bits 22-23 means normal, non-SSE instruction. 416 SSEDomainShift = 22, 417 418 OpcodeShift = 24, 419 OpcodeMask = 0xFF << OpcodeShift 420 421 }; 422 423 // FIXME: The enum opcode space is over and more bits are needed. Anywhere 424 // those enums below are used, TSFlags must be shifted right by 32 first. 425 enum { 426 //===------------------------------------------------------------------===// 427 // VEXPrefix - VEX prefixes are instruction prefixes used in AVX. 428 // VEX_4V is used to specify an additional AVX/SSE register. Several 2 429 // address instructions in SSE are represented as 3 address ones in AVX 430 // and the additional register is encoded in VEX_VVVV prefix. 431 // 432 VEXShift = 0, 433 VEX = 1 << VEXShift, 434 VEX_4V = 2 << VEXShift 435 }; 436 437 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 438 // specified machine instruction. 439 // 440 static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { 441 return TSFlags >> X86II::OpcodeShift; 442 } 443 444 static inline bool hasImm(uint64_t TSFlags) { 445 return (TSFlags & X86II::ImmMask) != 0; 446 } 447 448 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field 449 /// of the specified instruction. 450 static inline unsigned getSizeOfImm(uint64_t TSFlags) { 451 switch (TSFlags & X86II::ImmMask) { 452 default: assert(0 && "Unknown immediate size"); 453 case X86II::Imm8: 454 case X86II::Imm8PCRel: return 1; 455 case X86II::Imm16: return 2; 456 case X86II::Imm32: 457 case X86II::Imm32PCRel: return 4; 458 case X86II::Imm64: return 8; 459 } 460 } 461 462 /// isImmPCRel - Return true if the immediate of the specified instruction's 463 /// TSFlags indicates that it is pc relative. 464 static inline unsigned isImmPCRel(uint64_t TSFlags) { 465 switch (TSFlags & X86II::ImmMask) { 466 default: assert(0 && "Unknown immediate size"); 467 case X86II::Imm8PCRel: 468 case X86II::Imm32PCRel: 469 return true; 470 case X86II::Imm8: 471 case X86II::Imm16: 472 case X86II::Imm32: 473 case X86II::Imm64: 474 return false; 475 } 476 } 477} 478 479const int X86AddrNumOperands = 5; 480 481inline static bool isScale(const MachineOperand &MO) { 482 return MO.isImm() && 483 (MO.getImm() == 1 || MO.getImm() == 2 || 484 MO.getImm() == 4 || MO.getImm() == 8); 485} 486 487inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { 488 if (MI->getOperand(Op).isFI()) return true; 489 return Op+4 <= MI->getNumOperands() && 490 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 491 MI->getOperand(Op+2).isReg() && 492 (MI->getOperand(Op+3).isImm() || 493 MI->getOperand(Op+3).isGlobal() || 494 MI->getOperand(Op+3).isCPI() || 495 MI->getOperand(Op+3).isJTI()); 496} 497 498inline static bool isMem(const MachineInstr *MI, unsigned Op) { 499 if (MI->getOperand(Op).isFI()) return true; 500 return Op+5 <= MI->getNumOperands() && 501 MI->getOperand(Op+4).isReg() && 502 isLeaMem(MI, Op); 503} 504 505class X86InstrInfo : public TargetInstrInfoImpl { 506 X86TargetMachine &TM; 507 const X86RegisterInfo RI; 508 509 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 510 /// RegOp2MemOpTable2 - Load / store folding opcode maps. 511 /// 512 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2Addr; 513 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable0; 514 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable1; 515 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2; 516 517 /// MemOp2RegOpTable - Load / store unfolding opcode map. 518 /// 519 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 520 521public: 522 explicit X86InstrInfo(X86TargetMachine &tm); 523 524 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 525 /// such, whenever a client has an instance of instruction info, it should 526 /// always be able to get register info as well (through this method). 527 /// 528 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 529 530 /// Return true if the instruction is a register to register move and return 531 /// the source and dest operands and their sub-register indices by reference. 532 virtual bool isMoveInstr(const MachineInstr &MI, 533 unsigned &SrcReg, unsigned &DstReg, 534 unsigned &SrcSubIdx, unsigned &DstSubIdx) const; 535 536 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 537 /// extension instruction. That is, it's like a copy where it's legal for the 538 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 539 /// true, then it's expected the pre-extension value is available as a subreg 540 /// of the result register. This also returns the sub-register index in 541 /// SubIdx. 542 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 543 unsigned &SrcReg, unsigned &DstReg, 544 unsigned &SubIdx) const; 545 546 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 547 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 548 /// stack locations as well. This uses a heuristic so it isn't 549 /// reliable for correctness. 550 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 551 int &FrameIndex) const; 552 553 /// hasLoadFromStackSlot - If the specified machine instruction has 554 /// a load from a stack slot, return true along with the FrameIndex 555 /// of the loaded stack slot and the machine mem operand containing 556 /// the reference. If not, return false. Unlike 557 /// isLoadFromStackSlot, this returns true for any instructions that 558 /// loads from the stack. This is a hint only and may not catch all 559 /// cases. 560 bool hasLoadFromStackSlot(const MachineInstr *MI, 561 const MachineMemOperand *&MMO, 562 int &FrameIndex) const; 563 564 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; 565 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 566 /// stack locations as well. This uses a heuristic so it isn't 567 /// reliable for correctness. 568 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 569 int &FrameIndex) const; 570 571 /// hasStoreToStackSlot - If the specified machine instruction has a 572 /// store to a stack slot, return true along with the FrameIndex of 573 /// the loaded stack slot and the machine mem operand containing the 574 /// reference. If not, return false. Unlike isStoreToStackSlot, 575 /// this returns true for any instructions that loads from the 576 /// stack. This is a hint only and may not catch all cases. 577 bool hasStoreToStackSlot(const MachineInstr *MI, 578 const MachineMemOperand *&MMO, 579 int &FrameIndex) const; 580 581 bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 582 AliasAnalysis *AA) const; 583 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 584 unsigned DestReg, unsigned SubIdx, 585 const MachineInstr *Orig, 586 const TargetRegisterInfo &TRI) const; 587 588 /// convertToThreeAddress - This method must be implemented by targets that 589 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 590 /// may be able to convert a two-address instruction into a true 591 /// three-address instruction on demand. This allows the X86 target (for 592 /// example) to convert ADD and SHL instructions into LEA instructions if they 593 /// would require register copies due to two-addressness. 594 /// 595 /// This method returns a null pointer if the transformation cannot be 596 /// performed, otherwise it returns the new instruction. 597 /// 598 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 599 MachineBasicBlock::iterator &MBBI, 600 LiveVariables *LV) const; 601 602 /// commuteInstruction - We have a few instructions that must be hacked on to 603 /// commute them. 604 /// 605 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 606 607 // Branch analysis. 608 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 609 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 610 MachineBasicBlock *&FBB, 611 SmallVectorImpl<MachineOperand> &Cond, 612 bool AllowModify) const; 613 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 614 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 615 MachineBasicBlock *FBB, 616 const SmallVectorImpl<MachineOperand> &Cond, 617 DebugLoc DL) const; 618 virtual bool copyRegToReg(MachineBasicBlock &MBB, 619 MachineBasicBlock::iterator MI, 620 unsigned DestReg, unsigned SrcReg, 621 const TargetRegisterClass *DestRC, 622 const TargetRegisterClass *SrcRC, 623 DebugLoc DL) const; 624 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 625 MachineBasicBlock::iterator MI, 626 unsigned SrcReg, bool isKill, int FrameIndex, 627 const TargetRegisterClass *RC, 628 const TargetRegisterInfo *TRI) const; 629 630 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 631 SmallVectorImpl<MachineOperand> &Addr, 632 const TargetRegisterClass *RC, 633 MachineInstr::mmo_iterator MMOBegin, 634 MachineInstr::mmo_iterator MMOEnd, 635 SmallVectorImpl<MachineInstr*> &NewMIs) const; 636 637 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 638 MachineBasicBlock::iterator MI, 639 unsigned DestReg, int FrameIndex, 640 const TargetRegisterClass *RC, 641 const TargetRegisterInfo *TRI) const; 642 643 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 644 SmallVectorImpl<MachineOperand> &Addr, 645 const TargetRegisterClass *RC, 646 MachineInstr::mmo_iterator MMOBegin, 647 MachineInstr::mmo_iterator MMOEnd, 648 SmallVectorImpl<MachineInstr*> &NewMIs) const; 649 650 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 651 MachineBasicBlock::iterator MI, 652 const std::vector<CalleeSavedInfo> &CSI, 653 const TargetRegisterInfo *TRI) const; 654 655 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 656 MachineBasicBlock::iterator MI, 657 const std::vector<CalleeSavedInfo> &CSI, 658 const TargetRegisterInfo *TRI) const; 659 660 virtual 661 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 662 int FrameIx, uint64_t Offset, 663 const MDNode *MDPtr, 664 DebugLoc DL) const; 665 666 /// foldMemoryOperand - If this target supports it, fold a load or store of 667 /// the specified stack slot into the specified machine instruction for the 668 /// specified operand(s). If this is possible, the target should perform the 669 /// folding and return true, otherwise it should return false. If it folds 670 /// the instruction, it is likely that the MachineInstruction the iterator 671 /// references has been changed. 672 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 673 MachineInstr* MI, 674 const SmallVectorImpl<unsigned> &Ops, 675 int FrameIndex) const; 676 677 /// foldMemoryOperand - Same as the previous version except it allows folding 678 /// of any load and store from / to any address, not just from a specific 679 /// stack slot. 680 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 681 MachineInstr* MI, 682 const SmallVectorImpl<unsigned> &Ops, 683 MachineInstr* LoadMI) const; 684 685 /// canFoldMemoryOperand - Returns true if the specified load / store is 686 /// folding is possible. 687 virtual bool canFoldMemoryOperand(const MachineInstr*, 688 const SmallVectorImpl<unsigned> &) const; 689 690 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 691 /// a store or a load and a store into two or more instruction. If this is 692 /// possible, returns true as well as the new instructions by reference. 693 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 694 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 695 SmallVectorImpl<MachineInstr*> &NewMIs) const; 696 697 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 698 SmallVectorImpl<SDNode*> &NewNodes) const; 699 700 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 701 /// instruction after load / store are unfolded from an instruction of the 702 /// specified opcode. It returns zero if the specified unfolding is not 703 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 704 /// index of the operand which will hold the register holding the loaded 705 /// value. 706 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 707 bool UnfoldLoad, bool UnfoldStore, 708 unsigned *LoadRegIndex = 0) const; 709 710 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 711 /// to determine if two loads are loading from the same base address. It 712 /// should only return true if the base pointers are the same and the 713 /// only differences between the two addresses are the offset. It also returns 714 /// the offsets by reference. 715 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 716 int64_t &Offset1, int64_t &Offset2) const; 717 718 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 719 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 720 /// be scheduled togther. On some targets if two loads are loading from 721 /// addresses in the same cache line, it's better if they are scheduled 722 /// together. This function takes two integers that represent the load offsets 723 /// from the common base address. It returns true if it decides it's desirable 724 /// to schedule the two loads together. "NumLoads" is the number of loads that 725 /// have already been scheduled after Load1. 726 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 727 int64_t Offset1, int64_t Offset2, 728 unsigned NumLoads) const; 729 730 virtual void getNoopForMachoTarget(MCInst &NopInst) const; 731 732 virtual 733 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 734 735 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 736 /// instruction that defines the specified register class. 737 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 738 739 static bool isX86_64NonExtLowByteReg(unsigned reg) { 740 return (reg == X86::SPL || reg == X86::BPL || 741 reg == X86::SIL || reg == X86::DIL); 742 } 743 744 static bool isX86_64ExtendedReg(const MachineOperand &MO) { 745 if (!MO.isReg()) return false; 746 return isX86_64ExtendedReg(MO.getReg()); 747 } 748 static unsigned determineREX(const MachineInstr &MI); 749 750 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or 751 /// higher) register? e.g. r8, xmm8, xmm13, etc. 752 static bool isX86_64ExtendedReg(unsigned RegNo); 753 754 /// GetInstSize - Returns the size of the specified MachineInstr. 755 /// 756 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 757 758 /// getGlobalBaseReg - Return a virtual register initialized with the 759 /// the global base register value. Output instructions required to 760 /// initialize the register in the function entry block, if necessary. 761 /// 762 unsigned getGlobalBaseReg(MachineFunction *MF) const; 763 764 /// GetSSEDomain - Return the SSE execution domain of MI as the first element, 765 /// and a bitmask of possible arguments to SetSSEDomain ase the second. 766 std::pair<uint16_t, uint16_t> GetSSEDomain(const MachineInstr *MI) const; 767 768 /// SetSSEDomain - Set the SSEDomain of MI. 769 void SetSSEDomain(MachineInstr *MI, unsigned Domain) const; 770 771private: 772 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc, 773 MachineFunction::iterator &MFI, 774 MachineBasicBlock::iterator &MBBI, 775 LiveVariables *LV) const; 776 777 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 778 MachineInstr* MI, 779 unsigned OpNum, 780 const SmallVectorImpl<MachineOperand> &MOs, 781 unsigned Size, unsigned Alignment) const; 782 783 /// isFrameOperand - Return true and the FrameIndex if the specified 784 /// operand and follow operands form a reference to the stack frame. 785 bool isFrameOperand(const MachineInstr *MI, unsigned int Op, 786 int &FrameIndex) const; 787}; 788 789} // End llvm namespace 790 791#endif 792