X86InstrInfo.h revision d10fd9791c20fd8368fa0ce94b626b769c6c8ba0 
1//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef X86INSTRUCTIONINFO_H
15#define X86INSTRUCTIONINFO_H
16
17#include "llvm/Target/TargetInstrInfo.h"
18#include "X86RegisterInfo.h"
19#include "llvm/ADT/IndexedMap.h"
20#include "llvm/Target/MRegisterInfo.h"
21
22namespace llvm {
23  class X86RegisterInfo;
24  class X86TargetMachine;
25
26namespace X86 {
27  // X86 specific condition code. These correspond to X86_*_COND in
28  // X86InstrInfo.td. They must be kept in synch.
29  enum CondCode {
30    COND_A  = 0,
31    COND_AE = 1,
32    COND_B  = 2,
33    COND_BE = 3,
34    COND_E  = 4,
35    COND_G  = 5,
36    COND_GE = 6,
37    COND_L  = 7,
38    COND_LE = 8,
39    COND_NE = 9,
40    COND_NO = 10,
41    COND_NP = 11,
42    COND_NS = 12,
43    COND_O  = 13,
44    COND_P  = 14,
45    COND_S  = 15,
46    COND_INVALID
47  };
48
49  // Turn condition code into conditional branch opcode.
50  unsigned GetCondBranchFromCond(CondCode CC);
51
52  /// GetOppositeBranchCondition - Return the inverse of the specified cond,
53  /// e.g. turning COND_E to COND_NE.
54  CondCode GetOppositeBranchCondition(X86::CondCode CC);
55
56}
57
58/// X86II - This namespace holds all of the target specific flags that
59/// instruction info tracks.
60///
61namespace X86II {
62  enum {
63    //===------------------------------------------------------------------===//
64    // Instruction types.  These are the standard/most common forms for X86
65    // instructions.
66    //
67
68    // PseudoFrm - This represents an instruction that is a pseudo instruction
69    // or one that has not been implemented yet.  It is illegal to code generate
70    // it, but tolerated for intermediate implementation stages.
71    Pseudo         = 0,
72
73    /// Raw - This form is for instructions that don't have any operands, so
74    /// they are just a fixed opcode value, like 'leave'.
75    RawFrm         = 1,
76
77    /// AddRegFrm - This form is used for instructions like 'push r32' that have
78    /// their one register operand added to their opcode.
79    AddRegFrm      = 2,
80
81    /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
82    /// to specify a destination, which in this case is a register.
83    ///
84    MRMDestReg     = 3,
85
86    /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
87    /// to specify a destination, which in this case is memory.
88    ///
89    MRMDestMem     = 4,
90
91    /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
92    /// to specify a source, which in this case is a register.
93    ///
94    MRMSrcReg      = 5,
95
96    /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
97    /// to specify a source, which in this case is memory.
98    ///
99    MRMSrcMem      = 6,
100
101    /// MRM[0-7][rm] - These forms are used to represent instructions that use
102    /// a Mod/RM byte, and use the middle field to hold extended opcode
103    /// information.  In the intel manual these are represented as /0, /1, ...
104    ///
105
106    // First, instructions that operate on a register r/m operand...
107    MRM0r = 16,  MRM1r = 17,  MRM2r = 18,  MRM3r = 19, // Format /0 /1 /2 /3
108    MRM4r = 20,  MRM5r = 21,  MRM6r = 22,  MRM7r = 23, // Format /4 /5 /6 /7
109
110    // Next, instructions that operate on a memory r/m operand...
111    MRM0m = 24,  MRM1m = 25,  MRM2m = 26,  MRM3m = 27, // Format /0 /1 /2 /3
112    MRM4m = 28,  MRM5m = 29,  MRM6m = 30,  MRM7m = 31, // Format /4 /5 /6 /7
113
114    // MRMInitReg - This form is used for instructions whose source and
115    // destinations are the same register.
116    MRMInitReg = 32,
117
118    FormMask       = 63,
119
120    //===------------------------------------------------------------------===//
121    // Actual flags...
122
123    // OpSize - Set if this instruction requires an operand size prefix (0x66),
124    // which most often indicates that the instruction operates on 16 bit data
125    // instead of 32 bit data.
126    OpSize      = 1 << 6,
127
128    // AsSize - Set if this instruction requires an operand size prefix (0x67),
129    // which most often indicates that the instruction address 16 bit address
130    // instead of 32 bit address (or 32 bit address in 64 bit mode).
131    AdSize      = 1 << 7,
132
133    //===------------------------------------------------------------------===//
134    // Op0Mask - There are several prefix bytes that are used to form two byte
135    // opcodes.  These are currently 0x0F, 0xF3, and 0xD8-0xDF.  This mask is
136    // used to obtain the setting of this field.  If no bits in this field is
137    // set, there is no prefix byte for obtaining a multibyte opcode.
138    //
139    Op0Shift    = 8,
140    Op0Mask     = 0xF << Op0Shift,
141
142    // TB - TwoByte - Set if this instruction has a two byte opcode, which
143    // starts with a 0x0F byte before the real opcode.
144    TB          = 1 << Op0Shift,
145
146    // REP - The 0xF3 prefix byte indicating repetition of the following
147    // instruction.
148    REP         = 2 << Op0Shift,
149
150    // D8-DF - These escape opcodes are used by the floating point unit.  These
151    // values must remain sequential.
152    D8 = 3 << Op0Shift,   D9 = 4 << Op0Shift,
153    DA = 5 << Op0Shift,   DB = 6 << Op0Shift,
154    DC = 7 << Op0Shift,   DD = 8 << Op0Shift,
155    DE = 9 << Op0Shift,   DF = 10 << Op0Shift,
156
157    // XS, XD - These prefix codes are for single and double precision scalar
158    // floating point operations performed in the SSE registers.
159    XD = 11 << Op0Shift,  XS = 12 << Op0Shift,
160
161    // T8, TA - Prefix after the 0x0F prefix.
162    T8 = 13 << Op0Shift,  TA = 14 << Op0Shift,
163
164    //===------------------------------------------------------------------===//
165    // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
166    // They are used to specify GPRs and SSE registers, 64-bit operand size,
167    // etc. We only cares about REX.W and REX.R bits and only the former is
168    // statically determined.
169    //
170    REXShift    = 12,
171    REX_W       = 1 << REXShift,
172
173    //===------------------------------------------------------------------===//
174    // This three-bit field describes the size of an immediate operand.  Zero is
175    // unused so that we can tell if we forgot to set a value.
176    ImmShift = 13,
177    ImmMask  = 7 << ImmShift,
178    Imm8     = 1 << ImmShift,
179    Imm16    = 2 << ImmShift,
180    Imm32    = 3 << ImmShift,
181    Imm64    = 4 << ImmShift,
182
183    //===------------------------------------------------------------------===//
184    // FP Instruction Classification...  Zero is non-fp instruction.
185
186    // FPTypeMask - Mask for all of the FP types...
187    FPTypeShift = 16,
188    FPTypeMask  = 7 << FPTypeShift,
189
190    // NotFP - The default, set for instructions that do not use FP registers.
191    NotFP      = 0 << FPTypeShift,
192
193    // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
194    ZeroArgFP  = 1 << FPTypeShift,
195
196    // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
197    OneArgFP   = 2 << FPTypeShift,
198
199    // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
200    // result back to ST(0).  For example, fcos, fsqrt, etc.
201    //
202    OneArgFPRW = 3 << FPTypeShift,
203
204    // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
205    // explicit argument, storing the result to either ST(0) or the implicit
206    // argument.  For example: fadd, fsub, fmul, etc...
207    TwoArgFP   = 4 << FPTypeShift,
208
209    // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
210    // explicit argument, but have no destination.  Example: fucom, fucomi, ...
211    CompareFP  = 5 << FPTypeShift,
212
213    // CondMovFP - "2 operand" floating point conditional move instructions.
214    CondMovFP  = 6 << FPTypeShift,
215
216    // SpecialFP - Special instruction forms.  Dispatch by opcode explicitly.
217    SpecialFP  = 7 << FPTypeShift,
218
219    // Bits 19 -> 23 are unused
220    OpcodeShift   = 24,
221    OpcodeMask    = 0xFF << OpcodeShift
222  };
223}
224
225class X86InstrInfo : public TargetInstrInfo {
226  X86TargetMachine &TM;
227  const X86RegisterInfo RI;
228  mutable IndexedMap<const MachineInstr*, VirtReg2IndexFunctor> MachineInstrMap;
229
230  /// isDefinedInEntryBlock - Goes through the entry block to see if the given
231  /// virtual register is indeed defined in the entry block.
232  ///
233  bool isDefinedInEntryBlock(const MachineBasicBlock &Entry,
234                             unsigned VReg) const;
235public:
236  X86InstrInfo(X86TargetMachine &tm);
237
238  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
239  /// such, whenever a client has an instance of instruction info, it should
240  /// always be able to get register info as well (through this method).
241  ///
242  virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
243
244  // Return true if the instruction is a register to register move and
245  // leave the source and dest operands in the passed parameters.
246  //
247  bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg,
248                   unsigned& destReg) const;
249  unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
250  unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
251  bool isReallyTriviallyReMaterializable(MachineInstr *MI) const;
252  bool isReallySideEffectFree(MachineInstr *MI) const;
253
254  /// convertToThreeAddress - This method must be implemented by targets that
255  /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
256  /// may be able to convert a two-address instruction into a true
257  /// three-address instruction on demand.  This allows the X86 target (for
258  /// example) to convert ADD and SHL instructions into LEA instructions if they
259  /// would require register copies due to two-addressness.
260  ///
261  /// This method returns a null pointer if the transformation cannot be
262  /// performed, otherwise it returns the new instruction.
263  ///
264  virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
265                                              MachineBasicBlock::iterator &MBBI,
266                                              LiveVariables &LV) const;
267
268  /// commuteInstruction - We have a few instructions that must be hacked on to
269  /// commute them.
270  ///
271  virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
272
273  // Branch analysis.
274  virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
275  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
276                             MachineBasicBlock *&FBB,
277                             std::vector<MachineOperand> &Cond) const;
278  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
279  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
280                                MachineBasicBlock *FBB,
281                                const std::vector<MachineOperand> &Cond) const;
282  virtual void copyRegToReg(MachineBasicBlock &MBB,
283                            MachineBasicBlock::iterator MI,
284                            unsigned DestReg, unsigned SrcReg,
285                            const TargetRegisterClass *DestRC,
286                            const TargetRegisterClass *SrcRC) const;
287  virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
288  virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
289
290  const TargetRegisterClass *getPointerRegClass() const;
291
292  // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
293  // specified machine instruction.
294  //
295  unsigned char getBaseOpcodeFor(const TargetInstrDescriptor *TID) const {
296    return TID->TSFlags >> X86II::OpcodeShift;
297  }
298  unsigned char getBaseOpcodeFor(MachineOpCode Opcode) const {
299    return getBaseOpcodeFor(&get(Opcode));
300  }
301};
302
303} // End llvm namespace
304
305#endif
306