X86InstrInfo.h revision d74ea2bbd8bb630331f35ead42d385249bd42af8
18bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles)//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 28bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles)// 38bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles)// The LLVM Compiler Infrastructure 48bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles)// 58bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles)// This file was developed by the LLVM research group and is distributed under 68bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles)// the University of Illinois Open Source License. See LICENSE.TXT for details. 78bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles)// 85821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 95821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file contains the X86 implementation of the TargetInstrInfo class. 112a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// 125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 138bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) 148bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles)#ifndef X86INSTRUCTIONINFO_H 158bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles)#define X86INSTRUCTIONINFO_H 168bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) 178bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles)#include "llvm/Target/TargetInstrInfo.h" 188bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles)#include "X86RegisterInfo.h" 198bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) 208bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles)namespace llvm { 218bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) 228bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles)/// X86II - This namespace holds all of the target specific flags that 238bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles)/// instruction info tracks. 248bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles)/// 258bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles)namespace X86II { 268bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) enum { 278bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) //===------------------------------------------------------------------===// 288bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) // Instruction types. These are the standard/most common forms for X86 298bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) // instructions. 308bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) // 318bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) 328bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) // PseudoFrm - This represents an instruction that is a pseudo instruction 338bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) // or one that has not been implemented yet. It is illegal to code generate 348bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) // it, but tolerated for intermediate implementation stages. 358bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) Pseudo = 0, 368bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) 378bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) /// Raw - This form is for instructions that don't have any operands, so 388bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) /// they are just a fixed opcode value, like 'leave'. 398bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) RawFrm = 1, 408bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) 418bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) /// AddRegFrm - This form is used for instructions like 'push r32' that have 428bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) /// their one register operand added to their opcode. 438bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) AddRegFrm = 2, 448bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) 458bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 468bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) /// to specify a destination, which in this case is a register. 478bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) /// 488bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) MRMDestReg = 3, 498bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) 508bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 518bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) /// to specify a destination, which in this case is memory. 528bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) /// 538bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) MRMDestMem = 4, 548bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) 558bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 568bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) /// to specify a source, which in this case is a register. 578bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) /// 588bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) MRMSrcReg = 5, 598bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) 608bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 618bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) /// to specify a source, which in this case is memory. 628bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) /// 638bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) MRMSrcMem = 6, 648bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) 658bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) /// MRM[0-7][rm] - These forms are used to represent instructions that use 668bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) /// a Mod/RM byte, and use the middle field to hold extended opcode 678bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) /// information. In the intel manual these are represented as /0, /1, ... 688bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) /// 698bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) 708bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) // First, instructions that operate on a register r/m operand... 718bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 728bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 738bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) 748bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) // Next, instructions that operate on a memory r/m operand... 758bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 768bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 778bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) 788bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) // MRMInitReg - This form is used for instructions whose source and 798bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) // destinations are the same register. 808bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) MRMInitReg = 32, 818bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) 82 FormMask = 63, 83 84 //===------------------------------------------------------------------===// 85 // Actual flags... 86 87 // OpSize - Set if this instruction requires an operand size prefix (0x66), 88 // which most often indicates that the instruction operates on 16 bit data 89 // instead of 32 bit data. 90 OpSize = 1 << 6, 91 92 // Op0Mask - There are several prefix bytes that are used to form two byte 93 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 94 // used to obtain the setting of this field. If no bits in this field is 95 // set, there is no prefix byte for obtaining a multibyte opcode. 96 // 97 Op0Shift = 7, 98 Op0Mask = 0xF << Op0Shift, 99 100 // TB - TwoByte - Set if this instruction has a two byte opcode, which 101 // starts with a 0x0F byte before the real opcode. 102 TB = 1 << Op0Shift, 103 104 // REP - The 0xF3 prefix byte indicating repetition of the following 105 // instruction. 106 REP = 2 << Op0Shift, 107 108 // D8-DF - These escape opcodes are used by the floating point unit. These 109 // values must remain sequential. 110 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 111 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 112 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 113 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 114 115 // XS, XD - These prefix codes are for single and double precision scalar 116 // floating point operations performed in the SSE registers. 117 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 118 119 //===------------------------------------------------------------------===// 120 // This two-bit field describes the size of an immediate operand. Zero is 121 // unused so that we can tell if we forgot to set a value. 122 ImmShift = 11, 123 ImmMask = 3 << ImmShift, 124 Imm8 = 1 << ImmShift, 125 Imm16 = 2 << ImmShift, 126 Imm32 = 3 << ImmShift, 127 128 //===------------------------------------------------------------------===// 129 // FP Instruction Classification... Zero is non-fp instruction. 130 131 // FPTypeMask - Mask for all of the FP types... 132 FPTypeShift = 13, 133 FPTypeMask = 7 << FPTypeShift, 134 135 // NotFP - The default, set for instructions that do not use FP registers. 136 NotFP = 0 << FPTypeShift, 137 138 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 139 ZeroArgFP = 1 << FPTypeShift, 140 141 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 142 OneArgFP = 2 << FPTypeShift, 143 144 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 145 // result back to ST(0). For example, fcos, fsqrt, etc. 146 // 147 OneArgFPRW = 3 << FPTypeShift, 148 149 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 150 // explicit argument, storing the result to either ST(0) or the implicit 151 // argument. For example: fadd, fsub, fmul, etc... 152 TwoArgFP = 4 << FPTypeShift, 153 154 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 155 // explicit argument, but have no destination. Example: fucom, fucomi, ... 156 CompareFP = 5 << FPTypeShift, 157 158 // CondMovFP - "2 operand" floating point conditional move instructions. 159 CondMovFP = 6 << FPTypeShift, 160 161 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 162 SpecialFP = 7 << FPTypeShift, 163 164 OpcodeShift = 16, 165 OpcodeMask = 0xFF << OpcodeShift 166 // Bits 25 -> 31 are unused 167 }; 168} 169 170class X86InstrInfo : public TargetInstrInfo { 171 const X86RegisterInfo RI; 172public: 173 X86InstrInfo(); 174 175 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 176 /// such, whenever a client has an instance of instruction info, it should 177 /// always be able to get register info as well (through this method). 178 /// 179 virtual const MRegisterInfo &getRegisterInfo() const { return RI; } 180 181 // Return true if the instruction is a register to register move and 182 // leave the source and dest operands in the passed parameters. 183 // 184 bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, 185 unsigned& destReg) const; 186 unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; 187 unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; 188 189 /// convertToThreeAddress - This method must be implemented by targets that 190 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 191 /// may be able to convert a two-address instruction into a true 192 /// three-address instruction on demand. This allows the X86 target (for 193 /// example) to convert ADD and SHL instructions into LEA instructions if they 194 /// would require register copies due to two-addressness. 195 /// 196 /// This method returns a null pointer if the transformation cannot be 197 /// performed, otherwise it returns the new instruction. 198 /// 199 virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const; 200 201 /// commuteInstruction - We have a few instructions that must be hacked on to 202 /// commute them. 203 /// 204 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 205 206 207 /// Insert a goto (unconditional branch) sequence to TMBB, at the 208 /// end of MBB 209 virtual void insertGoto(MachineBasicBlock& MBB, 210 MachineBasicBlock& TMBB) const; 211 212 /// Reverses the branch condition of the MachineInstr pointed by 213 /// MI. The instruction is replaced and the new MI is returned. 214 virtual MachineBasicBlock::iterator 215 reverseBranchCondition(MachineBasicBlock::iterator MI) const; 216 217 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 218 // specified opcode number. 219 // 220 unsigned char getBaseOpcodeFor(unsigned Opcode) const { 221 return get(Opcode).TSFlags >> X86II::OpcodeShift; 222 } 223}; 224 225} // End llvm namespace 226 227#endif 228