X86InstrInfo.h revision d77ddbc0ba4614f4c9ef548e82ba6bc68c586cb5
1//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86INSTRUCTIONINFO_H 15#define X86INSTRUCTIONINFO_H 16 17#include "llvm/Target/TargetInstrInfo.h" 18#include "X86RegisterInfo.h" 19 20namespace llvm { 21 class X86RegisterInfo; 22 class X86TargetMachine; 23 24/// X86II - This namespace holds all of the target specific flags that 25/// instruction info tracks. 26/// 27namespace X86II { 28 enum { 29 //===------------------------------------------------------------------===// 30 // Instruction types. These are the standard/most common forms for X86 31 // instructions. 32 // 33 34 // PseudoFrm - This represents an instruction that is a pseudo instruction 35 // or one that has not been implemented yet. It is illegal to code generate 36 // it, but tolerated for intermediate implementation stages. 37 Pseudo = 0, 38 39 /// Raw - This form is for instructions that don't have any operands, so 40 /// they are just a fixed opcode value, like 'leave'. 41 RawFrm = 1, 42 43 /// AddRegFrm - This form is used for instructions like 'push r32' that have 44 /// their one register operand added to their opcode. 45 AddRegFrm = 2, 46 47 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 48 /// to specify a destination, which in this case is a register. 49 /// 50 MRMDestReg = 3, 51 52 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 53 /// to specify a destination, which in this case is memory. 54 /// 55 MRMDestMem = 4, 56 57 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 58 /// to specify a source, which in this case is a register. 59 /// 60 MRMSrcReg = 5, 61 62 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 63 /// to specify a source, which in this case is memory. 64 /// 65 MRMSrcMem = 6, 66 67 /// MRM[0-7][rm] - These forms are used to represent instructions that use 68 /// a Mod/RM byte, and use the middle field to hold extended opcode 69 /// information. In the intel manual these are represented as /0, /1, ... 70 /// 71 72 // First, instructions that operate on a register r/m operand... 73 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 74 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 75 76 // Next, instructions that operate on a memory r/m operand... 77 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 78 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 79 80 // MRMInitReg - This form is used for instructions whose source and 81 // destinations are the same register. 82 MRMInitReg = 32, 83 84 FormMask = 63, 85 86 //===------------------------------------------------------------------===// 87 // Actual flags... 88 89 // OpSize - Set if this instruction requires an operand size prefix (0x66), 90 // which most often indicates that the instruction operates on 16 bit data 91 // instead of 32 bit data. 92 OpSize = 1 << 6, 93 94 // AsSize - Set if this instruction requires an operand size prefix (0x67), 95 // which most often indicates that the instruction address 16 bit address 96 // instead of 32 bit address (or 32 bit address in 64 bit mode). 97 AdSize = 1 << 7, 98 99 //===------------------------------------------------------------------===// 100 // Op0Mask - There are several prefix bytes that are used to form two byte 101 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 102 // used to obtain the setting of this field. If no bits in this field is 103 // set, there is no prefix byte for obtaining a multibyte opcode. 104 // 105 Op0Shift = 8, 106 Op0Mask = 0xF << Op0Shift, 107 108 // TB - TwoByte - Set if this instruction has a two byte opcode, which 109 // starts with a 0x0F byte before the real opcode. 110 TB = 1 << Op0Shift, 111 112 // REP - The 0xF3 prefix byte indicating repetition of the following 113 // instruction. 114 REP = 2 << Op0Shift, 115 116 // D8-DF - These escape opcodes are used by the floating point unit. These 117 // values must remain sequential. 118 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 119 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 120 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 121 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 122 123 // XS, XD - These prefix codes are for single and double precision scalar 124 // floating point operations performed in the SSE registers. 125 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 126 127 //===------------------------------------------------------------------===// 128 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 129 // They are used to specify GPRs and SSE registers, 64-bit operand size, 130 // etc. We only cares about REX.W and REX.R bits and only the former is 131 // statically determined. 132 // 133 REXShift = 12, 134 REX_W = 1 << REXShift, 135 136 //===------------------------------------------------------------------===// 137 // This three-bit field describes the size of an immediate operand. Zero is 138 // unused so that we can tell if we forgot to set a value. 139 ImmShift = 13, 140 ImmMask = 7 << ImmShift, 141 Imm8 = 1 << ImmShift, 142 Imm16 = 2 << ImmShift, 143 Imm32 = 3 << ImmShift, 144 Imm64 = 4 << ImmShift, 145 146 //===------------------------------------------------------------------===// 147 // FP Instruction Classification... Zero is non-fp instruction. 148 149 // FPTypeMask - Mask for all of the FP types... 150 FPTypeShift = 16, 151 FPTypeMask = 7 << FPTypeShift, 152 153 // NotFP - The default, set for instructions that do not use FP registers. 154 NotFP = 0 << FPTypeShift, 155 156 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 157 ZeroArgFP = 1 << FPTypeShift, 158 159 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 160 OneArgFP = 2 << FPTypeShift, 161 162 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 163 // result back to ST(0). For example, fcos, fsqrt, etc. 164 // 165 OneArgFPRW = 3 << FPTypeShift, 166 167 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 168 // explicit argument, storing the result to either ST(0) or the implicit 169 // argument. For example: fadd, fsub, fmul, etc... 170 TwoArgFP = 4 << FPTypeShift, 171 172 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 173 // explicit argument, but have no destination. Example: fucom, fucomi, ... 174 CompareFP = 5 << FPTypeShift, 175 176 // CondMovFP - "2 operand" floating point conditional move instructions. 177 CondMovFP = 6 << FPTypeShift, 178 179 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 180 SpecialFP = 7 << FPTypeShift, 181 182 // Bits 19 -> 23 are unused 183 OpcodeShift = 24, 184 OpcodeMask = 0xFF << OpcodeShift 185 }; 186} 187 188class X86InstrInfo : public TargetInstrInfo { 189 X86TargetMachine &TM; 190 const X86RegisterInfo RI; 191public: 192 X86InstrInfo(X86TargetMachine &tm); 193 194 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 195 /// such, whenever a client has an instance of instruction info, it should 196 /// always be able to get register info as well (through this method). 197 /// 198 virtual const MRegisterInfo &getRegisterInfo() const { return RI; } 199 200 // Return true if the instruction is a register to register move and 201 // leave the source and dest operands in the passed parameters. 202 // 203 bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, 204 unsigned& destReg) const; 205 unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; 206 unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; 207 208 /// convertToThreeAddress - This method must be implemented by targets that 209 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 210 /// may be able to convert a two-address instruction into a true 211 /// three-address instruction on demand. This allows the X86 target (for 212 /// example) to convert ADD and SHL instructions into LEA instructions if they 213 /// would require register copies due to two-addressness. 214 /// 215 /// This method returns a null pointer if the transformation cannot be 216 /// performed, otherwise it returns the new instruction. 217 /// 218 virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const; 219 220 /// commuteInstruction - We have a few instructions that must be hacked on to 221 /// commute them. 222 /// 223 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 224 225 226 const TargetRegisterClass *getPointerRegClass() const; 227 228 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 229 // specified opcode number. 230 // 231 unsigned char getBaseOpcodeFor(unsigned Opcode) const { 232 return get(Opcode).TSFlags >> X86II::OpcodeShift; 233 } 234}; 235 236} // End llvm namespace 237 238#endif 239