X86InstrInfo.h revision d7d003c2b7b7f657eed364e4ac06f4ab32fc8c2d
15821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===// 25821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 35821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// The LLVM Compiler Infrastructure 45821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 55821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file is distributed under the University of Illinois Open Source 65821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// License. See LICENSE.TXT for details. 75821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 85821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 95821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file contains the X86 implementation of the TargetInstrInfo class. 115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 145821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#ifndef X86INSTRUCTIONINFO_H 155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#define X86INSTRUCTIONINFO_H 165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "X86.h" 185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "X86RegisterInfo.h" 195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/ADT/DenseMap.h" 205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/Target/TargetInstrInfo.h" 215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#define GET_INSTRINFO_HEADER 235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "X86GenInstrInfo.inc" 245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)namespace llvm { 265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) class X86RegisterInfo; 275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) class X86TargetMachine; 285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)namespace X86 { 305821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // X86 specific condition code. These correspond to X86_*_COND in 315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // X86InstrInfo.td. They must be kept in synch. 325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) enum CondCode { 335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_A = 0, 345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_AE = 1, 355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_B = 2, 365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_BE = 3, 375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_E = 4, 385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_G = 5, 395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_GE = 6, 405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_L = 7, 415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_LE = 8, 425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_NE = 9, 435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_NO = 10, 445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_NP = 11, 455821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_NS = 12, 465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_O = 13, 475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_P = 14, 485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_S = 15, 495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Artificial condition codes. These are used by AnalyzeBranch 515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // to indicate a block terminated with two conditional branches to 525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // which can't be represented on x86 with a single condition. These 545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // are never used in MachineInstrs. 555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_NE_OR_P, 565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_NP_OR_E, 575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 585821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) COND_INVALID 595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) }; 605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Turn condition code into conditional branch opcode. 625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned GetCondBranchFromCond(CondCode CC); 635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// GetOppositeBranchCondition - Return the inverse of the specified cond, 655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// e.g. turning COND_E to COND_NE. 665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) CondCode GetOppositeBranchCondition(X86::CondCode CC); 675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} // end namespace X86; 685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// isGlobalStubReference - Return true if the specified TargetFlag operand is 715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// a reference to a stub for a global, not the global itself. 725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)inline static bool isGlobalStubReference(unsigned char TargetFlag) { 735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) switch (TargetFlag) { 745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case X86II::MO_DLLIMPORT: // dllimport stub. 755821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case X86II::MO_GOTPCREL: // rip-relative GOT reference. 765821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case X86II::MO_GOT: // normal GOT reference. 775821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. 785821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. 795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref. 805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return true; 815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) default: 825821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return false; 835821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 845821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 855821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 865821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// isGlobalRelativeToPICBase - Return true if the specified global value 875821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this 885821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// is true, the addressing mode has the PIC base register added in (e.g. EBX). 895821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { 905821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) switch (TargetFlag) { 915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case X86II::MO_GOTOFF: // isPICStyleGOT: local global. 925821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case X86II::MO_GOT: // isPICStyleGOT: other global. 935821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. 945821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. 955821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global. 965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case X86II::MO_TLVP: // ??? Pretty sure.. 975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return true; 985821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) default: 995821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return false; 1005821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1015821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 1025821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)inline static bool isScale(const MachineOperand &MO) { 1045821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return MO.isImm() && 1055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) (MO.getImm() == 1 || MO.getImm() == 2 || 1065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MO.getImm() == 4 || MO.getImm() == 8); 1075821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 1085821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1095821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { 1105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (MI->getOperand(Op).isFI()) return true; 1115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return Op+4 <= MI->getNumOperands() && 1125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 1135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MI->getOperand(Op+2).isReg() && 1145821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) (MI->getOperand(Op+3).isImm() || 1155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MI->getOperand(Op+3).isGlobal() || 1165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MI->getOperand(Op+3).isCPI() || 1175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MI->getOperand(Op+3).isJTI()); 1185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 1195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)inline static bool isMem(const MachineInstr *MI, unsigned Op) { 1215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (MI->getOperand(Op).isFI()) return true; 1225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return Op+5 <= MI->getNumOperands() && 1235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MI->getOperand(Op+4).isReg() && 1245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) isLeaMem(MI, Op); 1255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 1265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)class X86InstrInfo : public X86GenInstrInfo { 1285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) X86TargetMachine &TM; 1295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const X86RegisterInfo RI; 1305821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// RegOp2MemOpTable3Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 1325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// RegOp2MemOpTable2, RegOp2MemOpTable3 - Load / store folding opcode maps. 1335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 1345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) typedef DenseMap<unsigned, 1355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) std::pair<unsigned, unsigned> > RegOp2MemOpTableType; 1365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) RegOp2MemOpTableType RegOp2MemOpTable2Addr; 1375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) RegOp2MemOpTableType RegOp2MemOpTable0; 1385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) RegOp2MemOpTableType RegOp2MemOpTable1; 1395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) RegOp2MemOpTableType RegOp2MemOpTable2; 1405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) RegOp2MemOpTableType RegOp2MemOpTable3; 1415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// MemOp2RegOpTable - Load / store unfolding opcode map. 1435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 1445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) typedef DenseMap<unsigned, 1455821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) std::pair<unsigned, unsigned> > MemOp2RegOpTableType; 1465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MemOp2RegOpTableType MemOp2RegOpTable; 1475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) static void AddTableEntry(RegOp2MemOpTableType &R2MTable, 1495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MemOp2RegOpTableType &M2RTable, 1505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned RegOp, unsigned MemOp, unsigned Flags); 1515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)public: 1535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) explicit X86InstrInfo(X86TargetMachine &tm); 1545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 1565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// such, whenever a client has an instance of instruction info, it should 1575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// always be able to get register info as well (through this method). 1585821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 1595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 1605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 1625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// extension instruction. That is, it's like a copy where it's legal for the 1635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 1645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// true, then it's expected the pre-extension value is available as a subreg 1655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// of the result register. This also returns the sub-register index in 1665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// SubIdx. 1675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual bool isCoalescableExtInstr(const MachineInstr &MI, 1685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned &SrcReg, unsigned &DstReg, 1695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned &SubIdx) const; 1705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 1725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 1735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// stack locations as well. This uses a heuristic so it isn't 1745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// reliable for correctness. 1755821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 1765821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) int &FrameIndex) const; 1775821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1785821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; 1795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 1805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// stack locations as well. This uses a heuristic so it isn't 1815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// reliable for correctness. 1825821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 1835821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) int &FrameIndex) const; 1845821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1855821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 1865821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) AliasAnalysis *AA) const; 1875821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 1885821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned DestReg, unsigned SubIdx, 1895821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const MachineInstr *Orig, 1905821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const TargetRegisterInfo &TRI) const; 1915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1925821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// convertToThreeAddress - This method must be implemented by targets that 1935821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 1945821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// may be able to convert a two-address instruction into a true 1955821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// three-address instruction on demand. This allows the X86 target (for 1965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// example) to convert ADD and SHL instructions into LEA instructions if they 1975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// would require register copies due to two-addressness. 1985821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 1995821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// This method returns a null pointer if the transformation cannot be 2005821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// performed, otherwise it returns the new instruction. 2015821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 2025821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 2035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineBasicBlock::iterator &MBBI, 2045821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) LiveVariables *LV) const; 2055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// commuteInstruction - We have a few instructions that must be hacked on to 2075821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// commute them. 2085821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 2095821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 2105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Branch analysis. 2125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 2135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 2145821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineBasicBlock *&FBB, 2155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) SmallVectorImpl<MachineOperand> &Cond, 2165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool AllowModify) const; 2175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 2185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 2195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineBasicBlock *FBB, 2205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const SmallVectorImpl<MachineOperand> &Cond, 2215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) DebugLoc DL) const; 2225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual bool canInsertSelect(const MachineBasicBlock&, 2235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const SmallVectorImpl<MachineOperand> &Cond, 2245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned, unsigned, int&, int&, int&) const; 2255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual void insertSelect(MachineBasicBlock &MBB, 2265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineBasicBlock::iterator MI, DebugLoc DL, 2275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned DstReg, 2285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const SmallVectorImpl<MachineOperand> &Cond, 2295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned TrueReg, unsigned FalseReg) const; 2305821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual void copyPhysReg(MachineBasicBlock &MBB, 2315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineBasicBlock::iterator MI, DebugLoc DL, 2325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned DestReg, unsigned SrcReg, 2335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool KillSrc) const; 2345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 2355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineBasicBlock::iterator MI, 2365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned SrcReg, bool isKill, int FrameIndex, 2375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const TargetRegisterClass *RC, 2385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const TargetRegisterInfo *TRI) const; 2395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 2415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) SmallVectorImpl<MachineOperand> &Addr, 2425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const TargetRegisterClass *RC, 2435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineInstr::mmo_iterator MMOBegin, 2445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineInstr::mmo_iterator MMOEnd, 2455821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) SmallVectorImpl<MachineInstr*> &NewMIs) const; 2465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 2485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineBasicBlock::iterator MI, 2495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned DestReg, int FrameIndex, 2505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const TargetRegisterClass *RC, 2515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const TargetRegisterInfo *TRI) const; 2525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 2545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) SmallVectorImpl<MachineOperand> &Addr, 2555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const TargetRegisterClass *RC, 2565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineInstr::mmo_iterator MMOBegin, 2575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineInstr::mmo_iterator MMOEnd, 2585821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) SmallVectorImpl<MachineInstr*> &NewMIs) const; 2595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; 2615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual 2635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 2645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) int FrameIx, uint64_t Offset, 2655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const MDNode *MDPtr, 2665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) DebugLoc DL) const; 2675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// foldMemoryOperand - If this target supports it, fold a load or store of 2695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// the specified stack slot into the specified machine instruction for the 2705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// specified operand(s). If this is possible, the target should perform the 2715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// folding and return true, otherwise it should return false. If it folds 2725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// the instruction, it is likely that the MachineInstruction the iterator 2735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// references has been changed. 2745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 2755821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineInstr* MI, 2765821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const SmallVectorImpl<unsigned> &Ops, 2775821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) int FrameIndex) const; 2785821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// foldMemoryOperand - Same as the previous version except it allows folding 2805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// of any load and store from / to any address, not just from a specific 2815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// stack slot. 2825821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 2835821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineInstr* MI, 2845821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const SmallVectorImpl<unsigned> &Ops, 2855821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineInstr* LoadMI) const; 2865821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2875821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// canFoldMemoryOperand - Returns true if the specified load / store is 2885821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// folding is possible. 2895821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual bool canFoldMemoryOperand(const MachineInstr*, 2905821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const SmallVectorImpl<unsigned> &) const; 2915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2925821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// unfoldMemoryOperand - Separate a single instruction which folded a load or 2935821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// a store or a load and a store into two or more instruction. If this is 2945821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// possible, returns true as well as the new instructions by reference. 2955821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 2965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 2975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) SmallVectorImpl<MachineInstr*> &NewMIs) const; 2985821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2995821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 3005821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) SmallVectorImpl<SDNode*> &NewNodes) const; 3015821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3025821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 3035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// instruction after load / store are unfolded from an instruction of the 3045821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// specified opcode. It returns zero if the specified unfolding is not 3055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// possible. If LoadRegIndex is non-null, it is filled in with the operand 3065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// index of the operand which will hold the register holding the loaded 3075821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// value. 3085821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 3095821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool UnfoldLoad, bool UnfoldStore, 3105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned *LoadRegIndex = 0) const; 3115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 3135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// to determine if two loads are loading from the same base address. It 3145821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// should only return true if the base pointers are the same and the 3155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// only differences between the two addresses are the offset. It also returns 3165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// the offsets by reference. 3175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 3185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) int64_t &Offset1, int64_t &Offset2) const; 3195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 3215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 3225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// be scheduled togther. On some targets if two loads are loading from 3235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// addresses in the same cache line, it's better if they are scheduled 3245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// together. This function takes two integers that represent the load offsets 3255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// from the common base address. It returns true if it decides it's desirable 3265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// to schedule the two loads together. "NumLoads" is the number of loads that 3275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// have already been scheduled after Load1. 3285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 3295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) int64_t Offset1, int64_t Offset2, 3305821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned NumLoads) const; 3315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual void getNoopForMachoTarget(MCInst &NopInst) const; 3335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual 3355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 3365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 3385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// instruction that defines the specified register class. 3395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 3405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) static bool isX86_64ExtendedReg(const MachineOperand &MO) { 3425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (!MO.isReg()) return false; 3435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return X86II::isX86_64ExtendedReg(MO.getReg()); 3445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 3455821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getGlobalBaseReg - Return a virtual register initialized with the 3475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// the global base register value. Output instructions required to 3485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// initialize the register in the function entry block, if necessary. 3495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 3505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned getGlobalBaseReg(MachineFunction *MF) const; 3515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) std::pair<uint16_t, uint16_t> 3535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) getExecutionDomain(const MachineInstr *MI) const; 3545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) void setExecutionDomain(MachineInstr *MI, unsigned Domain) const; 3565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, 3585821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const TargetRegisterInfo *TRI) const; 3595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, 3605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const TargetRegisterInfo *TRI) const; 3615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 3635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineInstr* MI, 3645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned OpNum, 3655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const SmallVectorImpl<MachineOperand> &MOs, 3665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned Size, unsigned Alignment) const; 3675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool isHighLatencyDef(int opc) const; 3695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool hasHighOperandLatency(const InstrItineraryData *ItinData, 3715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const MachineRegisterInfo *MRI, 3725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const MachineInstr *DefMI, unsigned DefIdx, 3735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const MachineInstr *UseMI, unsigned UseIdx) const; 3745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3755821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// analyzeCompare - For a comparison instruction, return the source registers 3765821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// in SrcReg and SrcReg2 if having two register operands, and the value it 3775821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// compares against in CmpValue. Return true if the comparison instruction 3785821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// can be analyzed. 3795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, 3805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned &SrcReg2, 3815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) int &CmpMask, int &CmpValue) const; 3825821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3835821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// optimizeCompareInstr - Check if there exists an earlier instruction that 3845821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// operates on the same source operands and sets flags in the same way as 3855821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// Compare; remove Compare if possible. 3865821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, 3875821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned SrcReg2, int CmpMask, int CmpValue, 3885821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const MachineRegisterInfo *MRI) const; 3895821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3905821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// optimizeLoadInstr - Try to remove the load by folding it to a register 3915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// operand at the use. We fold the load instructions if and only if the 3925821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// def and use are in the same BB. 3935821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI, 3945821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const MachineRegisterInfo *MRI, 3955821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned &FoldAsLoadDefReg, 3965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineInstr *&DefMI) const; 3975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3985821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)private: 3995821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc, 4005821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineFunction::iterator &MFI, 4015821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineBasicBlock::iterator &MBBI, 4025821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) LiveVariables *LV) const; 4035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 4045821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// isFrameOperand - Return true and the FrameIndex if the specified 4055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// operand and follow operands form a reference to the stack frame. 4065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool isFrameOperand(const MachineInstr *MI, unsigned int Op, 4075821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) int &FrameIndex) const; 4085821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)}; 4095821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 4105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} // End llvm namespace 4115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 4125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#endif 4135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)