X86InstrInfo.h revision da945e3bb2069c1a7194bcd10579a03ff925a031
18d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 28d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko// 38d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko// The LLVM Compiler Infrastructure 48d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko// 58d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko// This file is distributed under the University of Illinois Open Source 68d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko// License. See LICENSE.TXT for details. 78d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko// 88d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko//===----------------------------------------------------------------------===// 98d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko// 108d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko// This file contains the X86 implementation of the TargetInstrInfo class. 118d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko// 128d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko//===----------------------------------------------------------------------===// 138d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko 148d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko#ifndef X86INSTRUCTIONINFO_H 158d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko#define X86INSTRUCTIONINFO_H 168d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko 1730a2e16f6c27f888dd11eba6bbbae1e980078fcbChandler Carruth#include "llvm/Target/TargetInstrInfo.h" 18a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko#include "X86.h" 198d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko#include "X86RegisterInfo.h" 208d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko#include "llvm/ADT/DenseMap.h" 2196b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko#include "llvm/Target/TargetRegisterInfo.h" 2230a2e16f6c27f888dd11eba6bbbae1e980078fcbChandler Carruth 238d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenkonamespace llvm { 248d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko class X86RegisterInfo; 258d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko class X86TargetMachine; 26a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko 27a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenkonamespace X86 { 281952354bd376062c3ab3d328c0fc6c36530c9309Dmitri Gribenko // X86 specific condition code. These correspond to X86_*_COND in 29a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko // X86InstrInfo.td. They must be kept in synch. 308d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko enum CondCode { 31aa58081902ad31927df02e8537d972eabe29d6dfDmitri Gribenko COND_A = 0, 328d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko COND_AE = 1, 338d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko COND_B = 2, 34da5922f4864b5da254c6676af8833c42adaa6d86Dmitri Gribenko COND_BE = 3, 35da5922f4864b5da254c6676af8833c42adaa6d86Dmitri Gribenko COND_E = 4, 366f36366c85dc81d67d70efdeeea4cfc382053febDmitri Gribenko COND_G = 5, 37a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko COND_GE = 6, 388d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko COND_L = 7, 398d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko COND_LE = 8, 40a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko COND_NE = 9, 41a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko COND_NO = 10, 42a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko COND_NP = 11, 43a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko COND_NS = 12, 44a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko COND_O = 13, 45e4330a302ac20b41b9800267ebd4b5b01f8553f8Dmitri Gribenko COND_P = 14, 46aa58081902ad31927df02e8537d972eabe29d6dfDmitri Gribenko COND_S = 15, 471952354bd376062c3ab3d328c0fc6c36530c9309Dmitri Gribenko 481952354bd376062c3ab3d328c0fc6c36530c9309Dmitri Gribenko // Artificial condition codes. These are used by AnalyzeBranch 491ca7ecc8854ffea215c033a0d8482551bf1b73f0Dmitri Gribenko // to indicate a block terminated with two conditional branches to 501ca7ecc8854ffea215c033a0d8482551bf1b73f0Dmitri Gribenko // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 518487c524fdfcea3da858fd0af850b4784c8096d0Dmitri Gribenko // which can't be represented on x86 with a single condition. These 5296b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko // are never used in MachineInstrs. 5396b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko COND_NE_OR_P, 5496b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko COND_NP_OR_E, 551ca7ecc8854ffea215c033a0d8482551bf1b73f0Dmitri Gribenko 5696b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko COND_INVALID 5796b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko }; 589443c57150e870e308406e1e4e6d9d64712b417eDmitri Gribenko 599443c57150e870e308406e1e4e6d9d64712b417eDmitri Gribenko // Turn condition code into conditional branch opcode. 609443c57150e870e308406e1e4e6d9d64712b417eDmitri Gribenko unsigned GetCondBranchFromCond(CondCode CC); 61f843a580c4a54ca147f22422ee8ccfd2347784fcFariborz Jahanian 62f843a580c4a54ca147f22422ee8ccfd2347784fcFariborz Jahanian /// GetOppositeBranchCondition - Return the inverse of the specified cond, 639443c57150e870e308406e1e4e6d9d64712b417eDmitri Gribenko /// e.g. turning COND_E to COND_NE. 64a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko CondCode GetOppositeBranchCondition(X86::CondCode CC); 65a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko 66a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko} 67a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko 68a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko/// X86II - This namespace holds all of the target specific flags that 69a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko/// instruction info tracks. 703f38bf2d441fac379c427f86153fbb0cb41256c6Dmitri Gribenko/// 71a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenkonamespace X86II { 728d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko enum { 73a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko //===------------------------------------------------------------------===// 741952354bd376062c3ab3d328c0fc6c36530c9309Dmitri Gribenko // Instruction types. These are the standard/most common forms for X86 751952354bd376062c3ab3d328c0fc6c36530c9309Dmitri Gribenko // instructions. 76a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko // 77a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko 788d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko // PseudoFrm - This represents an instruction that is a pseudo instruction 7996b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko // or one that has not been implemented yet. It is illegal to code generate 8096b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko // it, but tolerated for intermediate implementation stages. 8196b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko Pseudo = 0, 8296b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko 8396b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko /// Raw - This form is for instructions that don't have any operands, so 8496b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko /// they are just a fixed opcode value, like 'leave'. 8596b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko RawFrm = 1, 8696b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko 876bcf27bb9a4b5c3f79cb44c0e4654a6d7619ad89Stephen Hines /// AddRegFrm - This form is used for instructions like 'push r32' that have 886bcf27bb9a4b5c3f79cb44c0e4654a6d7619ad89Stephen Hines /// their one register operand added to their opcode. 8996b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko AddRegFrm = 2, 9096b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko 918d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 928d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko /// to specify a destination, which in this case is a register. 938d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko /// 948d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko MRMDestReg = 3, 958d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko 968536fa14ee1048e5e2d62cb3dc11fc640c7dc00dFariborz Jahanian /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 97808383d2d6d58a7c7db85f8c7618fb74d821309fDmitri Gribenko /// to specify a destination, which in this case is memory. 988d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko /// 997d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko MRMDestMem = 4, 1007d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko 1018d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 1027d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko /// to specify a source, which in this case is a register. 1037d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko /// 1048d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko MRMSrcReg = 5, 1058d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko 1068d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 1078536fa14ee1048e5e2d62cb3dc11fc640c7dc00dFariborz Jahanian /// to specify a source, which in this case is memory. 108808383d2d6d58a7c7db85f8c7618fb74d821309fDmitri Gribenko /// 1098d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko MRMSrcMem = 6, 1107d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko 1117d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko /// MRM[0-7][rm] - These forms are used to represent instructions that use 1127d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko /// a Mod/RM byte, and use the middle field to hold extended opcode 1137d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko /// information. In the intel manual these are represented as /0, /1, ... 114a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko /// 1157d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko 1167d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko // First, instructions that operate on a register r/m operand... 1177d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 1187d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 1198d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko 1207d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko // Next, instructions that operate on a memory r/m operand... 1217d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 1228d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 12396b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko 12496b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko // MRMInitReg - This form is used for instructions whose source and 1258536fa14ee1048e5e2d62cb3dc11fc640c7dc00dFariborz Jahanian // destinations are the same register. 126808383d2d6d58a7c7db85f8c7618fb74d821309fDmitri Gribenko MRMInitReg = 32, 12796b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko 1287d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko FormMask = 63, 1297d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko 1307d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko //===------------------------------------------------------------------===// 1317d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko // Actual flags... 13296b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko 1337d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko // OpSize - Set if this instruction requires an operand size prefix (0x66), 1347d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko // which most often indicates that the instruction operates on 16 bit data 13596b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko // instead of 32 bit data. 1368d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko OpSize = 1 << 6, 1378d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko 138e4330a302ac20b41b9800267ebd4b5b01f8553f8Dmitri Gribenko // AsSize - Set if this instruction requires an operand size prefix (0x67), 1398d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko // which most often indicates that the instruction address 16 bit address 1408d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko // instead of 32 bit address (or 32 bit address in 64 bit mode). 1418d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko AdSize = 1 << 7, 142e4330a302ac20b41b9800267ebd4b5b01f8553f8Dmitri Gribenko 1438d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko //===------------------------------------------------------------------===// 1448d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko // Op0Mask - There are several prefix bytes that are used to form two byte 1458d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 1468d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko // used to obtain the setting of this field. If no bits in this field is 1478d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko // set, there is no prefix byte for obtaining a multibyte opcode. 1488d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko // 149b0b8a96df25660cbdbf35d23c3ff5887c33f82f9Dmitri Gribenko Op0Shift = 8, 150b0b8a96df25660cbdbf35d23c3ff5887c33f82f9Dmitri Gribenko Op0Mask = 0xF << Op0Shift, 151b0b8a96df25660cbdbf35d23c3ff5887c33f82f9Dmitri Gribenko 152b0b8a96df25660cbdbf35d23c3ff5887c33f82f9Dmitri Gribenko // TB - TwoByte - Set if this instruction has a two byte opcode, which 153b0b8a96df25660cbdbf35d23c3ff5887c33f82f9Dmitri Gribenko // starts with a 0x0F byte before the real opcode. 1548d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko TB = 1 << Op0Shift, 1558d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko 1568d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko // REP - The 0xF3 prefix byte indicating repetition of the following 1578d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko // instruction. 1588d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko REP = 2 << Op0Shift, 1598d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko 160e4330a302ac20b41b9800267ebd4b5b01f8553f8Dmitri Gribenko // D8-DF - These escape opcodes are used by the floating point unit. These 1618d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko // values must remain sequential. 1628d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 1638d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko DA = 5 << Op0Shift, DB = 6 << Op0Shift, 1648d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko DC = 7 << Op0Shift, DD = 8 << Op0Shift, 1657d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko DE = 9 << Op0Shift, DF = 10 << Op0Shift, 1667d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko 1677d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko // XS, XD - These prefix codes are for single and double precision scalar 1687d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko // floating point operations performed in the SSE registers. 1698d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko XD = 11 << Op0Shift, XS = 12 << Op0Shift, 1708d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko 171e4330a302ac20b41b9800267ebd4b5b01f8553f8Dmitri Gribenko // T8, TA - Prefix after the 0x0F prefix. 1728d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 1738d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko 1748d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko //===------------------------------------------------------------------===// 1753f38bf2d441fac379c427f86153fbb0cb41256c6Dmitri Gribenko // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 1763f38bf2d441fac379c427f86153fbb0cb41256c6Dmitri Gribenko // They are used to specify GPRs and SSE registers, 64-bit operand size, 1778d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko // etc. We only cares about REX.W and REX.R bits and only the former is 1787d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko // statically determined. 1797d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko // 1807d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko REXShift = 12, 1817d9b51107999c1c1fada7319c4687fe570eb2c0bDmitri Gribenko REX_W = 1 << REXShift, 1828d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko 1833f38bf2d441fac379c427f86153fbb0cb41256c6Dmitri Gribenko //===------------------------------------------------------------------===// 1843f38bf2d441fac379c427f86153fbb0cb41256c6Dmitri Gribenko // This three-bit field describes the size of an immediate operand. Zero is 1853f38bf2d441fac379c427f86153fbb0cb41256c6Dmitri Gribenko // unused so that we can tell if we forgot to set a value. 1868d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko ImmShift = 13, 1878d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko ImmMask = 7 << ImmShift, 1888d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko Imm8 = 1 << ImmShift, 189a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko Imm16 = 2 << ImmShift, 190a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko Imm32 = 3 << ImmShift, 19189ab7d0012ffe02a335b765eeb9b48977a5ecd79Dmitri Gribenko Imm64 = 4 << ImmShift, 19289ab7d0012ffe02a335b765eeb9b48977a5ecd79Dmitri Gribenko 1939443c57150e870e308406e1e4e6d9d64712b417eDmitri Gribenko //===------------------------------------------------------------------===// 1949443c57150e870e308406e1e4e6d9d64712b417eDmitri Gribenko // FP Instruction Classification... Zero is non-fp instruction. 1959443c57150e870e308406e1e4e6d9d64712b417eDmitri Gribenko 1969443c57150e870e308406e1e4e6d9d64712b417eDmitri Gribenko // FPTypeMask - Mask for all of the FP types... 1970bd9838751384181ff387f2fb346896792b89617Dmitri Gribenko FPTypeShift = 16, 1982a268f2629b49958427e8eb02f2c3d565be71accFariborz Jahanian FPTypeMask = 7 << FPTypeShift, 1992a268f2629b49958427e8eb02f2c3d565be71accFariborz Jahanian 20028c1cd2138f700742235e1e720c1f7e6dc75a11aFariborz Jahanian // NotFP - The default, set for instructions that do not use FP registers. 20128c1cd2138f700742235e1e720c1f7e6dc75a11aFariborz Jahanian NotFP = 0 << FPTypeShift, 20228c1cd2138f700742235e1e720c1f7e6dc75a11aFariborz Jahanian 20328c1cd2138f700742235e1e720c1f7e6dc75a11aFariborz Jahanian // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 2040bd9838751384181ff387f2fb346896792b89617Dmitri Gribenko ZeroArgFP = 1 << FPTypeShift, 2059edd2c8a2ff6c6326ff2d5b081929e4baaa798edDmitri Gribenko 2069edd2c8a2ff6c6326ff2d5b081929e4baaa798edDmitri Gribenko // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 2079edd2c8a2ff6c6326ff2d5b081929e4baaa798edDmitri Gribenko OneArgFP = 2 << FPTypeShift, 2089edd2c8a2ff6c6326ff2d5b081929e4baaa798edDmitri Gribenko 2098487c524fdfcea3da858fd0af850b4784c8096d0Dmitri Gribenko // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 210eb8f69f094e95d0132e4a6817a2111ad188ab087Fariborz Jahanian // result back to ST(0). For example, fcos, fsqrt, etc. 211a558d2e29817e36798875c96efb62251e53ff024Dmitri Gribenko // 212a558d2e29817e36798875c96efb62251e53ff024Dmitri Gribenko OneArgFPRW = 3 << FPTypeShift, 213a558d2e29817e36798875c96efb62251e53ff024Dmitri Gribenko 21499a7057098c56211e641705e1ff38d4b7c8b309dFariborz Jahanian // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 215c5b0054693b3b3cafe6a13549358c22e07fcd4ffDmitri Gribenko // explicit argument, storing the result to either ST(0) or the implicit 21699a7057098c56211e641705e1ff38d4b7c8b309dFariborz Jahanian // argument. For example: fadd, fsub, fmul, etc... 217664e860beb2550bef24fb8946192f61648a71d7fFariborz Jahanian TwoArgFP = 4 << FPTypeShift, 21804bf29eb1b197e0a103139ab5d63b0b97432f004Dmitri Gribenko 219b421b56d5a83c5bcae576b714ebd9df7b745368dFariborz Jahanian // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 220b421b56d5a83c5bcae576b714ebd9df7b745368dFariborz Jahanian // explicit argument, but have no destination. Example: fucom, fucomi, ... 22128c1cd2138f700742235e1e720c1f7e6dc75a11aFariborz Jahanian CompareFP = 5 << FPTypeShift, 22228c1cd2138f700742235e1e720c1f7e6dc75a11aFariborz Jahanian 22328c1cd2138f700742235e1e720c1f7e6dc75a11aFariborz Jahanian // CondMovFP - "2 operand" floating point conditional move instructions. 2242d588b4bc7127adf1a1c621002dfe452a99fef6fFariborz Jahanian CondMovFP = 6 << FPTypeShift, 2252d588b4bc7127adf1a1c621002dfe452a99fef6fFariborz Jahanian 22696b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 2278487c524fdfcea3da858fd0af850b4784c8096d0Dmitri Gribenko SpecialFP = 7 << FPTypeShift, 2288487c524fdfcea3da858fd0af850b4784c8096d0Dmitri Gribenko 2291ca7ecc8854ffea215c033a0d8482551bf1b73f0Dmitri Gribenko // Lock prefix 2301ca7ecc8854ffea215c033a0d8482551bf1b73f0Dmitri Gribenko LOCKShift = 19, 2318487c524fdfcea3da858fd0af850b4784c8096d0Dmitri Gribenko LOCK = 1 << LOCKShift, 2328487c524fdfcea3da858fd0af850b4784c8096d0Dmitri Gribenko 233a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko // Segment override prefixes. Currently we just need ability to address 234a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko // stuff in gs and fs segments. 2358487c524fdfcea3da858fd0af850b4784c8096d0Dmitri Gribenko SegOvrShift = 20, 236a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko SegOvrMask = 3 << SegOvrShift, 237a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko FS = 1 << SegOvrShift, 238a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko GS = 2 << SegOvrShift, 239a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko 2408487c524fdfcea3da858fd0af850b4784c8096d0Dmitri Gribenko // Bits 22 -> 23 are unused 241a5ef44ff5d93a3be6ca67782828157a71894cf0cDmitri Gribenko OpcodeShift = 24, 24296b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko OpcodeMask = 0xFF << OpcodeShift 24396b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko }; 24496b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko} 24596b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko 24696b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenkoconst int X86AddrNumOperands = 4; 24796b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko 24896b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenkoinline static bool isScale(const MachineOperand &MO) { 24996b098674908eaa59a9128f3305cda6fbbdad563Dmitri Gribenko return MO.isImm() && 2502d66a5016d4aacce362f89290261c8a1a6eef0d3Dmitri Gribenko (MO.getImm() == 1 || MO.getImm() == 2 || 2512d66a5016d4aacce362f89290261c8a1a6eef0d3Dmitri Gribenko MO.getImm() == 4 || MO.getImm() == 8); 2528d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko} 2538d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko 2548d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenkoinline static bool isMem(const MachineInstr *MI, unsigned Op) { 2558d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko if (MI->getOperand(Op).isFI()) return true; 2568d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko return Op+4 <= MI->getNumOperands() && 2578d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 2588d3ba23f2d9e6c87794d059412a0808c9cbacb25Dmitri Gribenko MI->getOperand(Op+2).isReg() && 259 (MI->getOperand(Op+3).isImm() || 260 MI->getOperand(Op+3).isGlobal() || 261 MI->getOperand(Op+3).isCPI() || 262 MI->getOperand(Op+3).isJTI()); 263} 264 265class X86InstrInfo : public TargetInstrInfoImpl { 266 X86TargetMachine &TM; 267 const X86RegisterInfo RI; 268 269 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 270 /// RegOp2MemOpTable2 - Load / store folding opcode maps. 271 /// 272 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr; 273 DenseMap<unsigned*, unsigned> RegOp2MemOpTable0; 274 DenseMap<unsigned*, unsigned> RegOp2MemOpTable1; 275 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2; 276 277 /// MemOp2RegOpTable - Load / store unfolding opcode map. 278 /// 279 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 280 281public: 282 explicit X86InstrInfo(X86TargetMachine &tm); 283 284 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 285 /// such, whenever a client has an instance of instruction info, it should 286 /// always be able to get register info as well (through this method). 287 /// 288 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 289 290 /// Return true if the instruction is a register to register move and return 291 /// the source and dest operands and their sub-register indices by reference. 292 virtual bool isMoveInstr(const MachineInstr &MI, 293 unsigned &SrcReg, unsigned &DstReg, 294 unsigned &SrcSubIdx, unsigned &DstSubIdx) const; 295 296 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 297 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; 298 299 bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const; 300 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 301 unsigned DestReg, const MachineInstr *Orig) const; 302 303 bool isInvariantLoad(const MachineInstr *MI) const; 304 305 /// convertToThreeAddress - This method must be implemented by targets that 306 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 307 /// may be able to convert a two-address instruction into a true 308 /// three-address instruction on demand. This allows the X86 target (for 309 /// example) to convert ADD and SHL instructions into LEA instructions if they 310 /// would require register copies due to two-addressness. 311 /// 312 /// This method returns a null pointer if the transformation cannot be 313 /// performed, otherwise it returns the new instruction. 314 /// 315 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 316 MachineBasicBlock::iterator &MBBI, 317 LiveVariables *LV) const; 318 319 /// commuteInstruction - We have a few instructions that must be hacked on to 320 /// commute them. 321 /// 322 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 323 324 // Branch analysis. 325 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 326 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 327 MachineBasicBlock *&FBB, 328 SmallVectorImpl<MachineOperand> &Cond, 329 bool AllowModify) const; 330 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 331 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 332 MachineBasicBlock *FBB, 333 const SmallVectorImpl<MachineOperand> &Cond) const; 334 virtual bool copyRegToReg(MachineBasicBlock &MBB, 335 MachineBasicBlock::iterator MI, 336 unsigned DestReg, unsigned SrcReg, 337 const TargetRegisterClass *DestRC, 338 const TargetRegisterClass *SrcRC) const; 339 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 340 MachineBasicBlock::iterator MI, 341 unsigned SrcReg, bool isKill, int FrameIndex, 342 const TargetRegisterClass *RC) const; 343 344 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 345 SmallVectorImpl<MachineOperand> &Addr, 346 const TargetRegisterClass *RC, 347 SmallVectorImpl<MachineInstr*> &NewMIs) const; 348 349 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 350 MachineBasicBlock::iterator MI, 351 unsigned DestReg, int FrameIndex, 352 const TargetRegisterClass *RC) const; 353 354 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 355 SmallVectorImpl<MachineOperand> &Addr, 356 const TargetRegisterClass *RC, 357 SmallVectorImpl<MachineInstr*> &NewMIs) const; 358 359 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 360 MachineBasicBlock::iterator MI, 361 const std::vector<CalleeSavedInfo> &CSI) const; 362 363 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 364 MachineBasicBlock::iterator MI, 365 const std::vector<CalleeSavedInfo> &CSI) const; 366 367 /// foldMemoryOperand - If this target supports it, fold a load or store of 368 /// the specified stack slot into the specified machine instruction for the 369 /// specified operand(s). If this is possible, the target should perform the 370 /// folding and return true, otherwise it should return false. If it folds 371 /// the instruction, it is likely that the MachineInstruction the iterator 372 /// references has been changed. 373 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 374 MachineInstr* MI, 375 const SmallVectorImpl<unsigned> &Ops, 376 int FrameIndex) const; 377 378 /// foldMemoryOperand - Same as the previous version except it allows folding 379 /// of any load and store from / to any address, not just from a specific 380 /// stack slot. 381 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 382 MachineInstr* MI, 383 const SmallVectorImpl<unsigned> &Ops, 384 MachineInstr* LoadMI) const; 385 386 /// canFoldMemoryOperand - Returns true if the specified load / store is 387 /// folding is possible. 388 virtual bool canFoldMemoryOperand(const MachineInstr*, 389 const SmallVectorImpl<unsigned> &) const; 390 391 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 392 /// a store or a load and a store into two or more instruction. If this is 393 /// possible, returns true as well as the new instructions by reference. 394 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 395 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 396 SmallVectorImpl<MachineInstr*> &NewMIs) const; 397 398 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 399 SmallVectorImpl<SDNode*> &NewNodes) const; 400 401 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 402 /// instruction after load / store are unfolded from an instruction of the 403 /// specified opcode. It returns zero if the specified unfolding is not 404 /// possible. 405 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 406 bool UnfoldLoad, bool UnfoldStore) const; 407 408 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const; 409 virtual 410 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 411 412 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 413 /// instruction that defines the specified register class. 414 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 415 416 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 417 // specified machine instruction. 418 // 419 unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const { 420 return TID->TSFlags >> X86II::OpcodeShift; 421 } 422 unsigned char getBaseOpcodeFor(unsigned Opcode) const { 423 return getBaseOpcodeFor(&get(Opcode)); 424 } 425 426 static bool isX86_64NonExtLowByteReg(unsigned reg) { 427 return (reg == X86::SPL || reg == X86::BPL || 428 reg == X86::SIL || reg == X86::DIL); 429 } 430 431 static unsigned sizeOfImm(const TargetInstrDesc *Desc); 432 static bool isX86_64ExtendedReg(const MachineOperand &MO); 433 static unsigned determineREX(const MachineInstr &MI); 434 435 /// GetInstSize - Returns the size of the specified MachineInstr. 436 /// 437 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 438 439 /// getGlobalBaseReg - Return a virtual register initialized with the 440 /// the global base register value. Output instructions required to 441 /// initialize the register in the function entry block, if necessary. 442 /// 443 unsigned getGlobalBaseReg(MachineFunction *MF) const; 444 445private: 446 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 447 MachineInstr* MI, 448 unsigned OpNum, 449 const SmallVectorImpl<MachineOperand> &MOs) const; 450}; 451 452} // End llvm namespace 453 454#endif 455