X86InstrInfo.td revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
1//===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 instruction set, defining the instructions, and 11// properties of the instructions which are needed for code generation, machine 12// code emission, and analysis. 13// 14//===----------------------------------------------------------------------===// 15 16//===----------------------------------------------------------------------===// 17// X86 specific DAG Nodes. 18// 19 20def SDTIntShiftDOp: SDTypeProfile<1, 3, 21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 22 SDTCisInt<0>, SDTCisInt<3>]>; 23 24def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; 25 26def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 27//def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 28 29def SDTX86Cmov : SDTypeProfile<1, 4, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; 32 33// Unary and binary operator instructions that set EFLAGS as a side-effect. 34def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, 35 [SDTCisInt<0>, SDTCisVT<1, i32>]>; 36 37def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 38 [SDTCisSameAs<0, 2>, 39 SDTCisSameAs<0, 3>, 40 SDTCisInt<0>, SDTCisVT<1, i32>]>; 41 42// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS 43def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 44 [SDTCisSameAs<0, 2>, 45 SDTCisSameAs<0, 3>, 46 SDTCisInt<0>, 47 SDTCisVT<1, i32>, 48 SDTCisVT<4, i32>]>; 49// RES1, RES2, FLAGS = op LHS, RHS 50def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2, 51 [SDTCisSameAs<0, 1>, 52 SDTCisSameAs<0, 2>, 53 SDTCisSameAs<0, 3>, 54 SDTCisInt<0>, SDTCisVT<1, i32>]>; 55def SDTX86BrCond : SDTypeProfile<0, 3, 56 [SDTCisVT<0, OtherVT>, 57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 58 59def SDTX86SetCC : SDTypeProfile<1, 2, 60 [SDTCisVT<0, i8>, 61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 62def SDTX86SetCC_C : SDTypeProfile<1, 2, 63 [SDTCisInt<0>, 64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 65 66def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>; 67 68def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>; 69 70def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, 71 SDTCisVT<2, i8>]>; 72def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 73 74def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>, 75 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>; 76def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>; 77 78def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 79def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, 80 SDTCisVT<1, i32>]>; 81 82def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 83 84def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, 85 SDTCisVT<1, iPTR>, 86 SDTCisVT<2, iPTR>]>; 87 88def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>, 89 SDTCisPtrTy<1>, 90 SDTCisVT<2, i32>, 91 SDTCisVT<3, i8>, 92 SDTCisVT<4, i32>]>; 93 94def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; 95 96def SDTX86Void : SDTypeProfile<0, 0, []>; 97 98def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 99 100def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 101 102def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 103 104def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 105 106def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 107 108def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>; 109 110def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 111 112def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 113 114def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>; 115 116def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER, 117 [SDNPHasChain,SDNPSideEffect]>; 118def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER, 119 [SDNPHasChain]>; 120def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER, 121 [SDNPHasChain]>; 122def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER, 123 [SDNPHasChain]>; 124 125 126def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; 127def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; 128def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; 129def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; 130 131def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; 132def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; 133 134def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; 135def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, 136 [SDNPHasChain]>; 137def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; 138def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; 139 140def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>; 141 142def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, 143 [SDNPHasChain, SDNPSideEffect]>; 144 145def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand, 146 [SDNPHasChain, SDNPSideEffect]>; 147 148def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, 149 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 150 SDNPMayLoad, SDNPMemOperand]>; 151def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair, 152 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 153 SDNPMayLoad, SDNPMemOperand]>; 154def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair, 155 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 156 SDNPMayLoad, SDNPMemOperand]>; 157 158def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary, 159 [SDNPHasChain, SDNPMayStore, 160 SDNPMayLoad, SDNPMemOperand]>; 161def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary, 162 [SDNPHasChain, SDNPMayStore, 163 SDNPMayLoad, SDNPMemOperand]>; 164def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary, 165 [SDNPHasChain, SDNPMayStore, 166 SDNPMayLoad, SDNPMemOperand]>; 167def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary, 168 [SDNPHasChain, SDNPMayStore, 169 SDNPMayLoad, SDNPMemOperand]>; 170def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary, 171 [SDNPHasChain, SDNPMayStore, 172 SDNPMayLoad, SDNPMemOperand]>; 173def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary, 174 [SDNPHasChain, SDNPMayStore, 175 SDNPMayLoad, SDNPMemOperand]>; 176def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary, 177 [SDNPHasChain, SDNPMayStore, 178 SDNPMayLoad, SDNPMemOperand]>; 179def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, 180 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 181 182def X86vastart_save_xmm_regs : 183 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", 184 SDT_X86VASTART_SAVE_XMM_REGS, 185 [SDNPHasChain, SDNPVariadic]>; 186def X86vaarg64 : 187 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64, 188 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 189 SDNPMemOperand]>; 190def X86callseq_start : 191 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, 192 [SDNPHasChain, SDNPOutGlue]>; 193def X86callseq_end : 194 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, 195 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 196 197def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, 198 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 199 SDNPVariadic]>; 200 201def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, 202 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>; 203def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, 204 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 205 SDNPMayLoad]>; 206 207def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void, 208 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 209def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void, 210 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 211 212def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; 213def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; 214 215def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, 216 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 217 218def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR, 219 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 220 221def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, 222 [SDNPHasChain]>; 223 224def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP", 225 SDTypeProfile<1, 1, [SDTCisInt<0>, 226 SDTCisPtrTy<1>]>, 227 [SDNPHasChain, SDNPSideEffect]>; 228def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP", 229 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 230 [SDNPHasChain, SDNPSideEffect]>; 231 232def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, 233 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 234 235def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, 236 [SDNPCommutative]>; 237def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; 238def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, 239 [SDNPCommutative]>; 240def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags, 241 [SDNPCommutative]>; 242def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>; 243def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>; 244 245def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; 246def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; 247def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, 248 [SDNPCommutative]>; 249def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, 250 [SDNPCommutative]>; 251def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, 252 [SDNPCommutative]>; 253 254def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>; 255 256def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; 257 258def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void, 259 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 260 261def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, 262 [SDNPHasChain]>; 263 264def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, 265 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 266 267def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL, 268 [SDNPHasChain, SDNPOutGlue]>; 269 270//===----------------------------------------------------------------------===// 271// X86 Operand Definitions. 272// 273 274// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for 275// the index operand of an address, to conform to x86 encoding restrictions. 276def ptr_rc_nosp : PointerLikeRegClass<1>; 277 278// *mem - Operand definitions for the funky X86 addressing mode operands. 279// 280def X86MemAsmOperand : AsmOperandClass { 281 let Name = "Mem"; 282} 283def X86Mem8AsmOperand : AsmOperandClass { 284 let Name = "Mem8"; let RenderMethod = "addMemOperands"; 285} 286def X86Mem16AsmOperand : AsmOperandClass { 287 let Name = "Mem16"; let RenderMethod = "addMemOperands"; 288} 289def X86Mem32AsmOperand : AsmOperandClass { 290 let Name = "Mem32"; let RenderMethod = "addMemOperands"; 291} 292def X86Mem64AsmOperand : AsmOperandClass { 293 let Name = "Mem64"; let RenderMethod = "addMemOperands"; 294} 295def X86Mem80AsmOperand : AsmOperandClass { 296 let Name = "Mem80"; let RenderMethod = "addMemOperands"; 297} 298def X86Mem128AsmOperand : AsmOperandClass { 299 let Name = "Mem128"; let RenderMethod = "addMemOperands"; 300} 301def X86Mem256AsmOperand : AsmOperandClass { 302 let Name = "Mem256"; let RenderMethod = "addMemOperands"; 303} 304def X86Mem512AsmOperand : AsmOperandClass { 305 let Name = "Mem512"; let RenderMethod = "addMemOperands"; 306} 307 308// Gather mem operands 309def X86MemVX32Operand : AsmOperandClass { 310 let Name = "MemVX32"; let RenderMethod = "addMemOperands"; 311} 312def X86MemVY32Operand : AsmOperandClass { 313 let Name = "MemVY32"; let RenderMethod = "addMemOperands"; 314} 315def X86MemVZ32Operand : AsmOperandClass { 316 let Name = "MemVZ32"; let RenderMethod = "addMemOperands"; 317} 318def X86MemVX64Operand : AsmOperandClass { 319 let Name = "MemVX64"; let RenderMethod = "addMemOperands"; 320} 321def X86MemVY64Operand : AsmOperandClass { 322 let Name = "MemVY64"; let RenderMethod = "addMemOperands"; 323} 324def X86MemVZ64Operand : AsmOperandClass { 325 let Name = "MemVZ64"; let RenderMethod = "addMemOperands"; 326} 327 328def X86AbsMemAsmOperand : AsmOperandClass { 329 let Name = "AbsMem"; 330 let SuperClasses = [X86MemAsmOperand]; 331} 332class X86MemOperand<string printMethod> : Operand<iPTR> { 333 let PrintMethod = printMethod; 334 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); 335 let ParserMatchClass = X86MemAsmOperand; 336} 337 338let OperandType = "OPERAND_MEMORY" in { 339def opaque32mem : X86MemOperand<"printopaquemem">; 340def opaque48mem : X86MemOperand<"printopaquemem">; 341def opaque80mem : X86MemOperand<"printopaquemem">; 342def opaque512mem : X86MemOperand<"printopaquemem">; 343 344def i8mem : X86MemOperand<"printi8mem"> { 345 let ParserMatchClass = X86Mem8AsmOperand; } 346def i16mem : X86MemOperand<"printi16mem"> { 347 let ParserMatchClass = X86Mem16AsmOperand; } 348def i32mem : X86MemOperand<"printi32mem"> { 349 let ParserMatchClass = X86Mem32AsmOperand; } 350def i64mem : X86MemOperand<"printi64mem"> { 351 let ParserMatchClass = X86Mem64AsmOperand; } 352def i128mem : X86MemOperand<"printi128mem"> { 353 let ParserMatchClass = X86Mem128AsmOperand; } 354def i256mem : X86MemOperand<"printi256mem"> { 355 let ParserMatchClass = X86Mem256AsmOperand; } 356def i512mem : X86MemOperand<"printi512mem"> { 357 let ParserMatchClass = X86Mem512AsmOperand; } 358def f32mem : X86MemOperand<"printf32mem"> { 359 let ParserMatchClass = X86Mem32AsmOperand; } 360def f64mem : X86MemOperand<"printf64mem"> { 361 let ParserMatchClass = X86Mem64AsmOperand; } 362def f80mem : X86MemOperand<"printf80mem"> { 363 let ParserMatchClass = X86Mem80AsmOperand; } 364def f128mem : X86MemOperand<"printf128mem"> { 365 let ParserMatchClass = X86Mem128AsmOperand; } 366def f256mem : X86MemOperand<"printf256mem">{ 367 let ParserMatchClass = X86Mem256AsmOperand; } 368def f512mem : X86MemOperand<"printf512mem">{ 369 let ParserMatchClass = X86Mem512AsmOperand; } 370def v512mem : Operand<iPTR> { 371 let PrintMethod = "printf512mem"; 372 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm); 373 let ParserMatchClass = X86Mem512AsmOperand; } 374 375// Gather mem operands 376def vx32mem : X86MemOperand<"printi32mem">{ 377 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm); 378 let ParserMatchClass = X86MemVX32Operand; } 379def vy32mem : X86MemOperand<"printi32mem">{ 380 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm); 381 let ParserMatchClass = X86MemVY32Operand; } 382def vx64mem : X86MemOperand<"printi64mem">{ 383 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm); 384 let ParserMatchClass = X86MemVX64Operand; } 385def vy64mem : X86MemOperand<"printi64mem">{ 386 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm); 387 let ParserMatchClass = X86MemVY64Operand; } 388def vy64xmem : X86MemOperand<"printi64mem">{ 389 let MIOperandInfo = (ops ptr_rc, i8imm, VR256X, i32imm, i8imm); 390 let ParserMatchClass = X86MemVY64Operand; } 391def vz32mem : X86MemOperand<"printi32mem">{ 392 let MIOperandInfo = (ops ptr_rc, i16imm, VR512, i32imm, i8imm); 393 let ParserMatchClass = X86MemVZ32Operand; } 394def vz64mem : X86MemOperand<"printi64mem">{ 395 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm); 396 let ParserMatchClass = X86MemVZ64Operand; } 397} 398 399// A version of i8mem for use on x86-64 that uses GR64_NOREX instead of 400// plain GR64, so that it doesn't potentially require a REX prefix. 401def i8mem_NOREX : Operand<i64> { 402 let PrintMethod = "printi8mem"; 403 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm); 404 let ParserMatchClass = X86Mem8AsmOperand; 405 let OperandType = "OPERAND_MEMORY"; 406} 407 408// GPRs available for tailcall. 409// It represents GR32_TC, GR64_TC or GR64_TCW64. 410def ptr_rc_tailcall : PointerLikeRegClass<2>; 411 412// Special i32mem for addresses of load folding tail calls. These are not 413// allowed to use callee-saved registers since they must be scheduled 414// after callee-saved register are popped. 415def i32mem_TC : Operand<i32> { 416 let PrintMethod = "printi32mem"; 417 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall, 418 i32imm, i8imm); 419 let ParserMatchClass = X86Mem32AsmOperand; 420 let OperandType = "OPERAND_MEMORY"; 421} 422 423// Special i64mem for addresses of load folding tail calls. These are not 424// allowed to use callee-saved registers since they must be scheduled 425// after callee-saved register are popped. 426def i64mem_TC : Operand<i64> { 427 let PrintMethod = "printi64mem"; 428 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, 429 ptr_rc_tailcall, i32imm, i8imm); 430 let ParserMatchClass = X86Mem64AsmOperand; 431 let OperandType = "OPERAND_MEMORY"; 432} 433 434let OperandType = "OPERAND_PCREL", 435 ParserMatchClass = X86AbsMemAsmOperand, 436 PrintMethod = "printPCRelImm" in { 437def i32imm_pcrel : Operand<i32>; 438def i16imm_pcrel : Operand<i16>; 439 440// Branch targets have OtherVT type and print as pc-relative values. 441def brtarget : Operand<OtherVT>; 442def brtarget8 : Operand<OtherVT>; 443 444} 445 446def X86SrcIdx8Operand : AsmOperandClass { 447 let Name = "SrcIdx8"; 448 let RenderMethod = "addSrcIdxOperands"; 449 let SuperClasses = [X86Mem8AsmOperand]; 450} 451def X86SrcIdx16Operand : AsmOperandClass { 452 let Name = "SrcIdx16"; 453 let RenderMethod = "addSrcIdxOperands"; 454 let SuperClasses = [X86Mem16AsmOperand]; 455} 456def X86SrcIdx32Operand : AsmOperandClass { 457 let Name = "SrcIdx32"; 458 let RenderMethod = "addSrcIdxOperands"; 459 let SuperClasses = [X86Mem32AsmOperand]; 460} 461def X86SrcIdx64Operand : AsmOperandClass { 462 let Name = "SrcIdx64"; 463 let RenderMethod = "addSrcIdxOperands"; 464 let SuperClasses = [X86Mem64AsmOperand]; 465} 466def X86DstIdx8Operand : AsmOperandClass { 467 let Name = "DstIdx8"; 468 let RenderMethod = "addDstIdxOperands"; 469 let SuperClasses = [X86Mem8AsmOperand]; 470} 471def X86DstIdx16Operand : AsmOperandClass { 472 let Name = "DstIdx16"; 473 let RenderMethod = "addDstIdxOperands"; 474 let SuperClasses = [X86Mem16AsmOperand]; 475} 476def X86DstIdx32Operand : AsmOperandClass { 477 let Name = "DstIdx32"; 478 let RenderMethod = "addDstIdxOperands"; 479 let SuperClasses = [X86Mem32AsmOperand]; 480} 481def X86DstIdx64Operand : AsmOperandClass { 482 let Name = "DstIdx64"; 483 let RenderMethod = "addDstIdxOperands"; 484 let SuperClasses = [X86Mem64AsmOperand]; 485} 486def X86MemOffs8AsmOperand : AsmOperandClass { 487 let Name = "MemOffs8"; 488 let RenderMethod = "addMemOffsOperands"; 489 let SuperClasses = [X86Mem8AsmOperand]; 490} 491def X86MemOffs16AsmOperand : AsmOperandClass { 492 let Name = "MemOffs16"; 493 let RenderMethod = "addMemOffsOperands"; 494 let SuperClasses = [X86Mem16AsmOperand]; 495} 496def X86MemOffs32AsmOperand : AsmOperandClass { 497 let Name = "MemOffs32"; 498 let RenderMethod = "addMemOffsOperands"; 499 let SuperClasses = [X86Mem32AsmOperand]; 500} 501def X86MemOffs64AsmOperand : AsmOperandClass { 502 let Name = "MemOffs64"; 503 let RenderMethod = "addMemOffsOperands"; 504 let SuperClasses = [X86Mem64AsmOperand]; 505} 506let OperandType = "OPERAND_MEMORY" in { 507def srcidx8 : Operand<iPTR> { 508 let ParserMatchClass = X86SrcIdx8Operand; 509 let MIOperandInfo = (ops ptr_rc, i8imm); 510 let PrintMethod = "printSrcIdx8"; } 511def srcidx16 : Operand<iPTR> { 512 let ParserMatchClass = X86SrcIdx16Operand; 513 let MIOperandInfo = (ops ptr_rc, i8imm); 514 let PrintMethod = "printSrcIdx16"; } 515def srcidx32 : Operand<iPTR> { 516 let ParserMatchClass = X86SrcIdx32Operand; 517 let MIOperandInfo = (ops ptr_rc, i8imm); 518 let PrintMethod = "printSrcIdx32"; } 519def srcidx64 : Operand<iPTR> { 520 let ParserMatchClass = X86SrcIdx64Operand; 521 let MIOperandInfo = (ops ptr_rc, i8imm); 522 let PrintMethod = "printSrcIdx64"; } 523def dstidx8 : Operand<iPTR> { 524 let ParserMatchClass = X86DstIdx8Operand; 525 let MIOperandInfo = (ops ptr_rc); 526 let PrintMethod = "printDstIdx8"; } 527def dstidx16 : Operand<iPTR> { 528 let ParserMatchClass = X86DstIdx16Operand; 529 let MIOperandInfo = (ops ptr_rc); 530 let PrintMethod = "printDstIdx16"; } 531def dstidx32 : Operand<iPTR> { 532 let ParserMatchClass = X86DstIdx32Operand; 533 let MIOperandInfo = (ops ptr_rc); 534 let PrintMethod = "printDstIdx32"; } 535def dstidx64 : Operand<iPTR> { 536 let ParserMatchClass = X86DstIdx64Operand; 537 let MIOperandInfo = (ops ptr_rc); 538 let PrintMethod = "printDstIdx64"; } 539def offset8 : Operand<iPTR> { 540 let ParserMatchClass = X86MemOffs8AsmOperand; 541 let MIOperandInfo = (ops i64imm, i8imm); 542 let PrintMethod = "printMemOffs8"; } 543def offset16 : Operand<iPTR> { 544 let ParserMatchClass = X86MemOffs16AsmOperand; 545 let MIOperandInfo = (ops i64imm, i8imm); 546 let PrintMethod = "printMemOffs16"; } 547def offset32 : Operand<iPTR> { 548 let ParserMatchClass = X86MemOffs32AsmOperand; 549 let MIOperandInfo = (ops i64imm, i8imm); 550 let PrintMethod = "printMemOffs32"; } 551def offset64 : Operand<iPTR> { 552 let ParserMatchClass = X86MemOffs64AsmOperand; 553 let MIOperandInfo = (ops i64imm, i8imm); 554 let PrintMethod = "printMemOffs64"; } 555} 556 557 558def SSECC : Operand<i8> { 559 let PrintMethod = "printSSECC"; 560 let OperandType = "OPERAND_IMMEDIATE"; 561} 562 563def AVXCC : Operand<i8> { 564 let PrintMethod = "printAVXCC"; 565 let OperandType = "OPERAND_IMMEDIATE"; 566} 567 568class ImmSExtAsmOperandClass : AsmOperandClass { 569 let SuperClasses = [ImmAsmOperand]; 570 let RenderMethod = "addImmOperands"; 571} 572 573class ImmZExtAsmOperandClass : AsmOperandClass { 574 let SuperClasses = [ImmAsmOperand]; 575 let RenderMethod = "addImmOperands"; 576} 577 578def X86GR32orGR64AsmOperand : AsmOperandClass { 579 let Name = "GR32orGR64"; 580} 581 582def GR32orGR64 : RegisterOperand<GR32> { 583 let ParserMatchClass = X86GR32orGR64AsmOperand; 584} 585 586def AVX512RC : Operand<i32> { 587 let PrintMethod = "printRoundingControl"; 588 let OperandType = "OPERAND_IMMEDIATE"; 589} 590// Sign-extended immediate classes. We don't need to define the full lattice 591// here because there is no instruction with an ambiguity between ImmSExti64i32 592// and ImmSExti32i8. 593// 594// The strange ranges come from the fact that the assembler always works with 595// 64-bit immediates, but for a 16-bit target value we want to accept both "-1" 596// (which will be a -1ULL), and "0xFF" (-1 in 16-bits). 597 598// [0, 0x7FFFFFFF] | 599// [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] 600def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { 601 let Name = "ImmSExti64i32"; 602} 603 604// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | 605// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 606def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { 607 let Name = "ImmSExti16i8"; 608 let SuperClasses = [ImmSExti64i32AsmOperand]; 609} 610 611// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | 612// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 613def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { 614 let Name = "ImmSExti32i8"; 615} 616 617// [0, 0x000000FF] 618def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass { 619 let Name = "ImmZExtu32u8"; 620} 621 622 623// [0, 0x0000007F] | 624// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 625def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { 626 let Name = "ImmSExti64i8"; 627 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, 628 ImmSExti64i32AsmOperand]; 629} 630 631// A couple of more descriptive operand definitions. 632// 16-bits but only 8 bits are significant. 633def i16i8imm : Operand<i16> { 634 let ParserMatchClass = ImmSExti16i8AsmOperand; 635 let OperandType = "OPERAND_IMMEDIATE"; 636} 637// 32-bits but only 8 bits are significant. 638def i32i8imm : Operand<i32> { 639 let ParserMatchClass = ImmSExti32i8AsmOperand; 640 let OperandType = "OPERAND_IMMEDIATE"; 641} 642// 32-bits but only 8 bits are significant, and those 8 bits are unsigned. 643def u32u8imm : Operand<i32> { 644 let ParserMatchClass = ImmZExtu32u8AsmOperand; 645 let OperandType = "OPERAND_IMMEDIATE"; 646} 647 648// 64-bits but only 32 bits are significant. 649def i64i32imm : Operand<i64> { 650 let ParserMatchClass = ImmSExti64i32AsmOperand; 651 let OperandType = "OPERAND_IMMEDIATE"; 652} 653 654// 64-bits but only 32 bits are significant, and those bits are treated as being 655// pc relative. 656def i64i32imm_pcrel : Operand<i64> { 657 let PrintMethod = "printPCRelImm"; 658 let ParserMatchClass = X86AbsMemAsmOperand; 659 let OperandType = "OPERAND_PCREL"; 660} 661 662// 64-bits but only 8 bits are significant. 663def i64i8imm : Operand<i64> { 664 let ParserMatchClass = ImmSExti64i8AsmOperand; 665 let OperandType = "OPERAND_IMMEDIATE"; 666} 667 668def lea64_32mem : Operand<i32> { 669 let PrintMethod = "printi32mem"; 670 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm); 671 let ParserMatchClass = X86MemAsmOperand; 672} 673 674// Memory operands that use 64-bit pointers in both ILP32 and LP64. 675def lea64mem : Operand<i64> { 676 let PrintMethod = "printi64mem"; 677 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm); 678 let ParserMatchClass = X86MemAsmOperand; 679} 680 681 682//===----------------------------------------------------------------------===// 683// X86 Complex Pattern Definitions. 684// 685 686// Define X86 specific addressing mode. 687def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>; 688def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr", 689 [add, sub, mul, X86mul_imm, shl, or, frameindex], 690 []>; 691// In 64-bit mode 32-bit LEAs can use RIP-relative addressing. 692def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr", 693 [add, sub, mul, X86mul_imm, shl, or, 694 frameindex, X86WrapperRIP], 695 []>; 696 697def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr", 698 [tglobaltlsaddr], []>; 699 700def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr", 701 [tglobaltlsaddr], []>; 702 703def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr", 704 [add, sub, mul, X86mul_imm, shl, or, frameindex, 705 X86WrapperRIP], []>; 706 707def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", 708 [tglobaltlsaddr], []>; 709 710def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", 711 [tglobaltlsaddr], []>; 712 713//===----------------------------------------------------------------------===// 714// X86 Instruction Predicate Definitions. 715def HasCMov : Predicate<"Subtarget->hasCMov()">; 716def NoCMov : Predicate<"!Subtarget->hasCMov()">; 717 718def HasMMX : Predicate<"Subtarget->hasMMX()">; 719def Has3DNow : Predicate<"Subtarget->has3DNow()">; 720def Has3DNowA : Predicate<"Subtarget->has3DNowA()">; 721def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; 722def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">; 723def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; 724def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">; 725def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; 726def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">; 727def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; 728def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">; 729def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; 730def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">; 731def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; 732def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">; 733def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; 734def HasAVX : Predicate<"Subtarget->hasAVX()">; 735def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; 736def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">; 737def HasAVX512 : Predicate<"Subtarget->hasAVX512()">, 738 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">; 739def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">; 740def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">; 741def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">; 742def HasCDI : Predicate<"Subtarget->hasCDI()">; 743def HasPFI : Predicate<"Subtarget->hasPFI()">; 744def HasERI : Predicate<"Subtarget->hasERI()">; 745 746def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; 747def HasAES : Predicate<"Subtarget->hasAES()">; 748def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">; 749def HasFMA : Predicate<"Subtarget->hasFMA()">; 750def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">; 751def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; 752def HasXOP : Predicate<"Subtarget->hasXOP()">; 753def HasTBM : Predicate<"Subtarget->hasTBM()">; 754def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; 755def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; 756def HasF16C : Predicate<"Subtarget->hasF16C()">; 757def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">; 758def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">; 759def HasBMI : Predicate<"Subtarget->hasBMI()">; 760def HasBMI2 : Predicate<"Subtarget->hasBMI2()">; 761def HasRTM : Predicate<"Subtarget->hasRTM()">; 762def HasHLE : Predicate<"Subtarget->hasHLE()">; 763def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">; 764def HasADX : Predicate<"Subtarget->hasADX()">; 765def HasSHA : Predicate<"Subtarget->hasSHA()">; 766def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">; 767def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">; 768def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">; 769def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; 770def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; 771def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">; 772def Not64BitMode : Predicate<"!Subtarget->is64Bit()">, 773 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">; 774def In64BitMode : Predicate<"Subtarget->is64Bit()">, 775 AssemblerPredicate<"Mode64Bit", "64-bit mode">; 776def In16BitMode : Predicate<"Subtarget->is16Bit()">, 777 AssemblerPredicate<"Mode16Bit", "16-bit mode">; 778def Not16BitMode : Predicate<"!Subtarget->is16Bit()">, 779 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">; 780def In32BitMode : Predicate<"Subtarget->is32Bit()">, 781 AssemblerPredicate<"Mode32Bit", "32-bit mode">; 782def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; 783def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 784def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; 785def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; 786def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; 787def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&" 788 "TM.getCodeModel() != CodeModel::Kernel">; 789def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" 790 "TM.getCodeModel() == CodeModel::Kernel">; 791def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; 792def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">; 793def OptForSize : Predicate<"OptForSize">; 794def OptForSpeed : Predicate<"!OptForSize">; 795def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">; 796def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">; 797def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">; 798 799//===----------------------------------------------------------------------===// 800// X86 Instruction Format Definitions. 801// 802 803include "X86InstrFormats.td" 804 805//===----------------------------------------------------------------------===// 806// Pattern fragments. 807// 808 809// X86 specific condition code. These correspond to CondCode in 810// X86InstrInfo.h. They must be kept in synch. 811def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE 812def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC 813def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C 814def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA 815def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z 816def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE 817def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL 818def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE 819def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG 820def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ 821def X86_COND_NO : PatLeaf<(i8 10)>; 822def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO 823def X86_COND_NS : PatLeaf<(i8 12)>; 824def X86_COND_O : PatLeaf<(i8 13)>; 825def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE 826def X86_COND_S : PatLeaf<(i8 15)>; 827 828let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs. 829 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>; 830 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>; 831 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>; 832} 833 834def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>; 835 836 837// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit 838// unsigned field. 839def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>; 840 841def i64immZExt32SExt8 : ImmLeaf<i64, [{ 842 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm; 843}]>; 844 845// Helper fragments for loads. 846// It's always safe to treat a anyext i16 load as a i32 load if the i16 is 847// known to be 32-bit aligned or better. Ditto for i8 to i16. 848def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ 849 LoadSDNode *LD = cast<LoadSDNode>(N); 850 ISD::LoadExtType ExtType = LD->getExtensionType(); 851 if (ExtType == ISD::NON_EXTLOAD) 852 return true; 853 if (ExtType == ISD::EXTLOAD) 854 return LD->getAlignment() >= 2 && !LD->isVolatile(); 855 return false; 856}]>; 857 858def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{ 859 LoadSDNode *LD = cast<LoadSDNode>(N); 860 ISD::LoadExtType ExtType = LD->getExtensionType(); 861 if (ExtType == ISD::EXTLOAD) 862 return LD->getAlignment() >= 2 && !LD->isVolatile(); 863 return false; 864}]>; 865 866def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ 867 LoadSDNode *LD = cast<LoadSDNode>(N); 868 ISD::LoadExtType ExtType = LD->getExtensionType(); 869 if (ExtType == ISD::NON_EXTLOAD) 870 return true; 871 if (ExtType == ISD::EXTLOAD) 872 return LD->getAlignment() >= 4 && !LD->isVolatile(); 873 return false; 874}]>; 875 876def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>; 877def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; 878def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; 879def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; 880def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; 881 882def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; 883def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; 884def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; 885def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; 886def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; 887def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; 888 889def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; 890def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; 891def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; 892def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; 893def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; 894def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; 895def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; 896def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; 897def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; 898def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; 899 900def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; 901def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; 902def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; 903def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; 904def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; 905def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; 906def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; 907def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; 908def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; 909def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; 910 911 912// An 'and' node with a single use. 913def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 914 return N->hasOneUse(); 915}]>; 916// An 'srl' node with a single use. 917def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ 918 return N->hasOneUse(); 919}]>; 920// An 'trunc' node with a single use. 921def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ 922 return N->hasOneUse(); 923}]>; 924 925//===----------------------------------------------------------------------===// 926// Instruction list. 927// 928 929// Nop 930let neverHasSideEffects = 1, SchedRW = [WriteZero] in { 931 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>; 932 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero), 933 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16; 934 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero), 935 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32; 936} 937 938 939// Constructing a stack frame. 940def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), 941 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>; 942 943let SchedRW = [WriteALU] in { 944let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in 945def LEAVE : I<0xC9, RawFrm, 946 (outs), (ins), "leave", [], IIC_LEAVE>, 947 Requires<[Not64BitMode]>; 948 949let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in 950def LEAVE64 : I<0xC9, RawFrm, 951 (outs), (ins), "leave", [], IIC_LEAVE>, 952 Requires<[In64BitMode]>; 953} // SchedRW 954 955//===----------------------------------------------------------------------===// 956// Miscellaneous Instructions. 957// 958 959let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in { 960let mayLoad = 1, SchedRW = [WriteLoad] in { 961def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [], 962 IIC_POP_REG16>, OpSize16; 963def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [], 964 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>; 965def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [], 966 IIC_POP_REG>, OpSize16; 967def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [], 968 IIC_POP_MEM>, OpSize16; 969def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [], 970 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>; 971def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [], 972 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>; 973 974def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, 975 OpSize16; 976def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>, 977 OpSize32, Requires<[Not64BitMode]>; 978} // mayLoad, SchedRW 979 980let mayStore = 1, SchedRW = [WriteStore] in { 981def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[], 982 IIC_PUSH_REG>, OpSize16; 983def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[], 984 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>; 985def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[], 986 IIC_PUSH_REG>, OpSize16; 987def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[], 988 IIC_PUSH_MEM>, OpSize16; 989def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[], 990 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>; 991def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[], 992 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>; 993 994def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm), 995 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16, 996 Requires<[Not64BitMode]>; 997def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), 998 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32, 999 Requires<[Not64BitMode]>; 1000def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), 1001 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16, 1002 Requires<[Not64BitMode]>; 1003def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), 1004 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32, 1005 Requires<[Not64BitMode]>; 1006 1007def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>, 1008 OpSize16; 1009def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>, 1010 OpSize32, Requires<[Not64BitMode]>; 1011 1012} // mayStore, SchedRW 1013} 1014 1015let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in { 1016let mayLoad = 1, SchedRW = [WriteLoad] in { 1017def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [], 1018 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>; 1019def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [], 1020 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>; 1021def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [], 1022 IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>; 1023} // mayLoad, SchedRW 1024let mayStore = 1, SchedRW = [WriteStore] in { 1025def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [], 1026 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>; 1027def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [], 1028 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>; 1029def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [], 1030 IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>; 1031} // mayStore, SchedRW 1032} 1033 1034let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1, 1035 SchedRW = [WriteStore] in { 1036def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), 1037 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>; 1038def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), 1039 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16, 1040 Requires<[In64BitMode]>; 1041def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm), 1042 "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32, 1043 Requires<[In64BitMode]>; 1044} 1045 1046let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in 1047def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>, 1048 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>; 1049let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in 1050def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>, 1051 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>; 1052 1053let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], 1054 mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in { 1055def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>, 1056 OpSize32, Requires<[Not64BitMode]>; 1057def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>, 1058 OpSize16, Requires<[Not64BitMode]>; 1059} 1060let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], 1061 mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in { 1062def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>, 1063 OpSize32, Requires<[Not64BitMode]>; 1064def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>, 1065 OpSize16, Requires<[Not64BitMode]>; 1066} 1067 1068let Constraints = "$src = $dst", SchedRW = [WriteALU] in { 1069// GR32 = bswap GR32 1070def BSWAP32r : I<0xC8, AddRegFrm, 1071 (outs GR32:$dst), (ins GR32:$src), 1072 "bswap{l}\t$dst", 1073 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB; 1074 1075def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), 1076 "bswap{q}\t$dst", 1077 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB; 1078} // Constraints = "$src = $dst", SchedRW 1079 1080// Bit scan instructions. 1081let Defs = [EFLAGS] in { 1082def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1083 "bsf{w}\t{$src, $dst|$dst, $src}", 1084 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))], 1085 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>; 1086def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1087 "bsf{w}\t{$src, $dst|$dst, $src}", 1088 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))], 1089 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>; 1090def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1091 "bsf{l}\t{$src, $dst|$dst, $src}", 1092 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))], 1093 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>; 1094def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1095 "bsf{l}\t{$src, $dst|$dst, $src}", 1096 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))], 1097 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>; 1098def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1099 "bsf{q}\t{$src, $dst|$dst, $src}", 1100 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))], 1101 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>; 1102def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1103 "bsf{q}\t{$src, $dst|$dst, $src}", 1104 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))], 1105 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>; 1106 1107def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1108 "bsr{w}\t{$src, $dst|$dst, $src}", 1109 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))], 1110 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>; 1111def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1112 "bsr{w}\t{$src, $dst|$dst, $src}", 1113 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))], 1114 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>; 1115def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1116 "bsr{l}\t{$src, $dst|$dst, $src}", 1117 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))], 1118 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>; 1119def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1120 "bsr{l}\t{$src, $dst|$dst, $src}", 1121 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))], 1122 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>; 1123def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1124 "bsr{q}\t{$src, $dst|$dst, $src}", 1125 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], 1126 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>; 1127def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1128 "bsr{q}\t{$src, $dst|$dst, $src}", 1129 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))], 1130 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>; 1131} // Defs = [EFLAGS] 1132 1133let SchedRW = [WriteMicrocoded] in { 1134// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1135let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in { 1136def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src), 1137 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>; 1138def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src), 1139 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16; 1140def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src), 1141 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32; 1142def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src), 1143 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>; 1144} 1145 1146// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1147let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in 1148def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins), 1149 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>; 1150let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in 1151def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins), 1152 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16; 1153let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in 1154def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins), 1155 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32; 1156let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in 1157def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins), 1158 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>; 1159 1160// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1161let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in 1162def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst), 1163 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>; 1164let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in 1165def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst), 1166 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16; 1167let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in 1168def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst), 1169 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32; 1170let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in 1171def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst), 1172 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>; 1173 1174// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1175let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in { 1176def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), 1177 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>; 1178def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), 1179 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16; 1180def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), 1181 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32; 1182def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), 1183 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>; 1184} 1185} // SchedRW 1186 1187//===----------------------------------------------------------------------===// 1188// Move Instructions. 1189// 1190let SchedRW = [WriteMove] in { 1191let neverHasSideEffects = 1 in { 1192def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), 1193 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1194def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1195 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16; 1196def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1197 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32; 1198def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1199 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1200} 1201 1202let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 1203def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), 1204 "mov{b}\t{$src, $dst|$dst, $src}", 1205 [(set GR8:$dst, imm:$src)], IIC_MOV>; 1206def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), 1207 "mov{w}\t{$src, $dst|$dst, $src}", 1208 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16; 1209def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), 1210 "mov{l}\t{$src, $dst|$dst, $src}", 1211 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32; 1212def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), 1213 "mov{q}\t{$src, $dst|$dst, $src}", 1214 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>; 1215} 1216let isReMaterializable = 1 in { 1217def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), 1218 "movabs{q}\t{$src, $dst|$dst, $src}", 1219 [(set GR64:$dst, imm:$src)], IIC_MOV>; 1220} 1221 1222// Longer forms that use a ModR/M byte. Needed for disassembler 1223let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 1224def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src), 1225 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1226def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src), 1227 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16; 1228def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src), 1229 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32; 1230} 1231} // SchedRW 1232 1233let SchedRW = [WriteStore] in { 1234def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), 1235 "mov{b}\t{$src, $dst|$dst, $src}", 1236 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>; 1237def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), 1238 "mov{w}\t{$src, $dst|$dst, $src}", 1239 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16; 1240def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), 1241 "mov{l}\t{$src, $dst|$dst, $src}", 1242 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32; 1243def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), 1244 "mov{q}\t{$src, $dst|$dst, $src}", 1245 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>; 1246} // SchedRW 1247 1248let hasSideEffects = 0 in { 1249 1250/// moffs8, moffs16 and moffs32 versions of moves. The immediate is a 1251/// 32-bit offset from the segment base. These are only valid in x86-32 mode. 1252let SchedRW = [WriteALU] in { 1253let mayLoad = 1 in { 1254let Defs = [AL] in 1255def MOV8o8a : Ii32 <0xA0, RawFrmMemOffs, (outs), (ins offset8:$src), 1256 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, 1257 Requires<[In32BitMode]>; 1258let Defs = [AX] in 1259def MOV16o16a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src), 1260 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, 1261 OpSize16, Requires<[In32BitMode]>; 1262let Defs = [EAX] in 1263def MOV32o32a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src), 1264 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, 1265 OpSize32, Requires<[In32BitMode]>; 1266 1267let Defs = [AL] in 1268def MOV8o8a_16 : Ii16 <0xA0, RawFrmMemOffs, (outs), (ins offset8:$src), 1269 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, 1270 AdSize, Requires<[In16BitMode]>; 1271let Defs = [AX] in 1272def MOV16o16a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src), 1273 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, 1274 OpSize16, AdSize, Requires<[In16BitMode]>; 1275let Defs = [EAX] in 1276def MOV32o32a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src), 1277 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, 1278 AdSize, OpSize32, Requires<[In16BitMode]>; 1279} 1280let mayStore = 1 in { 1281let Uses = [AL] in 1282def MOV8ao8 : Ii32 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins), 1283 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, 1284 Requires<[In32BitMode]>; 1285let Uses = [AX] in 1286def MOV16ao16 : Ii32 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins), 1287 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, 1288 OpSize16, Requires<[In32BitMode]>; 1289let Uses = [EAX] in 1290def MOV32ao32 : Ii32 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins), 1291 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>, 1292 OpSize32, Requires<[In32BitMode]>; 1293 1294let Uses = [AL] in 1295def MOV8ao8_16 : Ii16 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins), 1296 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, 1297 AdSize, Requires<[In16BitMode]>; 1298let Uses = [AX] in 1299def MOV16ao16_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins), 1300 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, 1301 OpSize16, AdSize, Requires<[In16BitMode]>; 1302let Uses = [EAX] in 1303def MOV32ao32_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins), 1304 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>, 1305 OpSize32, AdSize, Requires<[In16BitMode]>; 1306} 1307} 1308 1309// These forms all have full 64-bit absolute addresses in their instructions 1310// and use the movabs mnemonic to indicate this specific form. 1311let mayLoad = 1 in { 1312let Defs = [AL] in 1313def MOV64o8a : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset8:$src), 1314 "movabs{b}\t{$src, %al|al, $src}", []>, 1315 Requires<[In64BitMode]>; 1316let Defs = [AX] in 1317def MOV64o16a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset16:$src), 1318 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, 1319 Requires<[In64BitMode]>; 1320let Defs = [EAX] in 1321def MOV64o32a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset32:$src), 1322 "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32, 1323 Requires<[In64BitMode]>; 1324let Defs = [RAX] in 1325def MOV64o64a : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64:$src), 1326 "movabs{q}\t{$src, %rax|rax, $src}", []>, 1327 Requires<[In64BitMode]>; 1328} 1329 1330let mayStore = 1 in { 1331let Uses = [AL] in 1332def MOV64ao8 : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins), 1333 "movabs{b}\t{%al, $dst|$dst, al}", []>, 1334 Requires<[In64BitMode]>; 1335let Uses = [AX] in 1336def MOV64ao16 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins), 1337 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, 1338 Requires<[In64BitMode]>; 1339let Uses = [EAX] in 1340def MOV64ao32 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins), 1341 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32, 1342 Requires<[In64BitMode]>; 1343let Uses = [RAX] in 1344def MOV64ao64 : RIi64<0xA3, RawFrmMemOffs, (outs offset64:$dst), (ins), 1345 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, 1346 Requires<[In64BitMode]>; 1347} 1348} // hasSideEffects = 0 1349 1350let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, 1351 SchedRW = [WriteMove] in { 1352def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), 1353 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1354def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1355 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16; 1356def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1357 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32; 1358def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1359 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1360} 1361 1362let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in { 1363def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), 1364 "mov{b}\t{$src, $dst|$dst, $src}", 1365 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>; 1366def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1367 "mov{w}\t{$src, $dst|$dst, $src}", 1368 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16; 1369def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1370 "mov{l}\t{$src, $dst|$dst, $src}", 1371 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32; 1372def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1373 "mov{q}\t{$src, $dst|$dst, $src}", 1374 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>; 1375} 1376 1377let SchedRW = [WriteStore] in { 1378def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), 1379 "mov{b}\t{$src, $dst|$dst, $src}", 1380 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>; 1381def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1382 "mov{w}\t{$src, $dst|$dst, $src}", 1383 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16; 1384def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1385 "mov{l}\t{$src, $dst|$dst, $src}", 1386 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32; 1387def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1388 "mov{q}\t{$src, $dst|$dst, $src}", 1389 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>; 1390} // SchedRW 1391 1392// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so 1393// that they can be used for copying and storing h registers, which can't be 1394// encoded when a REX prefix is present. 1395let isCodeGenOnly = 1 in { 1396let neverHasSideEffects = 1 in 1397def MOV8rr_NOREX : I<0x88, MRMDestReg, 1398 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), 1399 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>, 1400 Sched<[WriteMove]>; 1401let mayStore = 1, neverHasSideEffects = 1 in 1402def MOV8mr_NOREX : I<0x88, MRMDestMem, 1403 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), 1404 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], 1405 IIC_MOV_MEM>, Sched<[WriteStore]>; 1406let mayLoad = 1, neverHasSideEffects = 1, 1407 canFoldAsLoad = 1, isReMaterializable = 1 in 1408def MOV8rm_NOREX : I<0x8A, MRMSrcMem, 1409 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), 1410 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], 1411 IIC_MOV_MEM>, Sched<[WriteLoad]>; 1412} 1413 1414 1415// Condition code ops, incl. set if equal/not equal/... 1416let SchedRW = [WriteALU] in { 1417let Defs = [EFLAGS], Uses = [AH] in 1418def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", 1419 [(set EFLAGS, (X86sahf AH))], IIC_AHF>; 1420let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in 1421def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [], 1422 IIC_AHF>; // AH = flags 1423} // SchedRW 1424 1425//===----------------------------------------------------------------------===// 1426// Bit tests instructions: BT, BTS, BTR, BTC. 1427 1428let Defs = [EFLAGS] in { 1429let SchedRW = [WriteALU] in { 1430def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1431 "bt{w}\t{$src2, $src1|$src1, $src2}", 1432 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>, 1433 OpSize16, TB; 1434def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1435 "bt{l}\t{$src2, $src1|$src1, $src2}", 1436 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>, 1437 OpSize32, TB; 1438def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1439 "bt{q}\t{$src2, $src1|$src1, $src2}", 1440 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB; 1441} // SchedRW 1442 1443// Unlike with the register+register form, the memory+register form of the 1444// bt instruction does not ignore the high bits of the index. From ISel's 1445// perspective, this is pretty bizarre. Make these instructions disassembly 1446// only for now. 1447 1448let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in { 1449 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1450 "bt{w}\t{$src2, $src1|$src1, $src2}", 1451 // [(X86bt (loadi16 addr:$src1), GR16:$src2), 1452 // (implicit EFLAGS)] 1453 [], IIC_BT_MR 1454 >, OpSize16, TB, Requires<[FastBTMem]>; 1455 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1456 "bt{l}\t{$src2, $src1|$src1, $src2}", 1457 // [(X86bt (loadi32 addr:$src1), GR32:$src2), 1458 // (implicit EFLAGS)] 1459 [], IIC_BT_MR 1460 >, OpSize32, TB, Requires<[FastBTMem]>; 1461 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1462 "bt{q}\t{$src2, $src1|$src1, $src2}", 1463 // [(X86bt (loadi64 addr:$src1), GR64:$src2), 1464 // (implicit EFLAGS)] 1465 [], IIC_BT_MR 1466 >, TB; 1467} 1468 1469let SchedRW = [WriteALU] in { 1470def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1471 "bt{w}\t{$src2, $src1|$src1, $src2}", 1472 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))], 1473 IIC_BT_RI>, OpSize16, TB; 1474def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1475 "bt{l}\t{$src2, $src1|$src1, $src2}", 1476 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))], 1477 IIC_BT_RI>, OpSize32, TB; 1478def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1479 "bt{q}\t{$src2, $src1|$src1, $src2}", 1480 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))], 1481 IIC_BT_RI>, TB; 1482} // SchedRW 1483 1484// Note that these instructions don't need FastBTMem because that 1485// only applies when the other operand is in a register. When it's 1486// an immediate, bt is still fast. 1487let SchedRW = [WriteALU] in { 1488def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1489 "bt{w}\t{$src2, $src1|$src1, $src2}", 1490 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2)) 1491 ], IIC_BT_MI>, OpSize16, TB; 1492def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1493 "bt{l}\t{$src2, $src1|$src1, $src2}", 1494 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2)) 1495 ], IIC_BT_MI>, OpSize32, TB; 1496def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1497 "bt{q}\t{$src2, $src1|$src1, $src2}", 1498 [(set EFLAGS, (X86bt (loadi64 addr:$src1), 1499 i64immSExt8:$src2))], IIC_BT_MI>, TB; 1500} // SchedRW 1501 1502let hasSideEffects = 0 in { 1503let SchedRW = [WriteALU] in { 1504def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1505 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1506 OpSize16, TB; 1507def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1508 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1509 OpSize32, TB; 1510def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1511 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; 1512} // SchedRW 1513 1514let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1515def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1516 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1517 OpSize16, TB; 1518def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1519 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1520 OpSize32, TB; 1521def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1522 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1523} 1524 1525let SchedRW = [WriteALU] in { 1526def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1527 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1528 OpSize16, TB; 1529def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1530 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1531 OpSize32, TB; 1532def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1533 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1534} // SchedRW 1535 1536let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1537def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1538 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1539 OpSize16, TB; 1540def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1541 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1542 OpSize32, TB; 1543def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1544 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1545} 1546 1547let SchedRW = [WriteALU] in { 1548def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1549 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1550 OpSize16, TB; 1551def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1552 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1553 OpSize32, TB; 1554def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1555 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1556} // SchedRW 1557 1558let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1559def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1560 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1561 OpSize16, TB; 1562def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1563 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1564 OpSize32, TB; 1565def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1566 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1567} 1568 1569let SchedRW = [WriteALU] in { 1570def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1571 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1572 OpSize16, TB; 1573def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1574 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1575 OpSize32, TB; 1576def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1577 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1578} // SchedRW 1579 1580let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1581def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1582 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1583 OpSize16, TB; 1584def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1585 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1586 OpSize32, TB; 1587def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1588 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1589} 1590 1591let SchedRW = [WriteALU] in { 1592def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1593 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1594 OpSize16, TB; 1595def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1596 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1597 OpSize32, TB; 1598def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1599 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; 1600} // SchedRW 1601 1602let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1603def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1604 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1605 OpSize16, TB; 1606def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1607 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1608 OpSize32, TB; 1609def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1610 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1611} 1612 1613let SchedRW = [WriteALU] in { 1614def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1615 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1616 OpSize16, TB; 1617def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1618 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1619 OpSize32, TB; 1620def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1621 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1622} // SchedRW 1623 1624let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1625def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1626 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1627 OpSize16, TB; 1628def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1629 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1630 OpSize32, TB; 1631def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1632 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1633} 1634} // hasSideEffects = 0 1635} // Defs = [EFLAGS] 1636 1637 1638//===----------------------------------------------------------------------===// 1639// Atomic support 1640// 1641 1642// Atomic swap. These are just normal xchg instructions. But since a memory 1643// operand is referenced, the atomicity is ensured. 1644multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag, 1645 InstrItinClass itin> { 1646 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in { 1647 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst), 1648 (ins GR8:$val, i8mem:$ptr), 1649 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 1650 [(set 1651 GR8:$dst, 1652 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))], 1653 itin>; 1654 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst), 1655 (ins GR16:$val, i16mem:$ptr), 1656 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 1657 [(set 1658 GR16:$dst, 1659 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))], 1660 itin>, OpSize16; 1661 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst), 1662 (ins GR32:$val, i32mem:$ptr), 1663 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 1664 [(set 1665 GR32:$dst, 1666 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))], 1667 itin>, OpSize32; 1668 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst), 1669 (ins GR64:$val, i64mem:$ptr), 1670 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 1671 [(set 1672 GR64:$dst, 1673 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))], 1674 itin>; 1675 } 1676} 1677 1678defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>; 1679 1680// Swap between registers. 1681let SchedRW = [WriteALU] in { 1682let Constraints = "$val = $dst" in { 1683def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src), 1684 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>; 1685def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src), 1686 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, 1687 OpSize16; 1688def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src), 1689 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, 1690 OpSize32; 1691def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src), 1692 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>; 1693} 1694 1695// Swap between EAX and other registers. 1696let Uses = [AX], Defs = [AX] in 1697def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src), 1698 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16; 1699let Uses = [EAX], Defs = [EAX] in 1700def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src), 1701 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>, 1702 OpSize32, Requires<[Not64BitMode]>; 1703let Uses = [EAX], Defs = [EAX] in 1704// Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding. 1705// xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP. 1706def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src), 1707 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>, 1708 OpSize32, Requires<[In64BitMode]>; 1709let Uses = [RAX], Defs = [RAX] in 1710def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src), 1711 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>; 1712} // SchedRW 1713 1714let SchedRW = [WriteALU] in { 1715def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 1716 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB; 1717def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1718 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB, 1719 OpSize16; 1720def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1721 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB, 1722 OpSize32; 1723def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1724 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB; 1725} // SchedRW 1726 1727let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1728def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 1729 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB; 1730def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1731 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB, 1732 OpSize16; 1733def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1734 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB, 1735 OpSize32; 1736def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1737 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB; 1738 1739} 1740 1741let SchedRW = [WriteALU] in { 1742def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 1743 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [], 1744 IIC_CMPXCHG_REG8>, TB; 1745def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1746 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [], 1747 IIC_CMPXCHG_REG>, TB, OpSize16; 1748def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1749 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [], 1750 IIC_CMPXCHG_REG>, TB, OpSize32; 1751def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1752 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [], 1753 IIC_CMPXCHG_REG>, TB; 1754} // SchedRW 1755 1756let SchedRW = [WriteALULd, WriteRMW] in { 1757let mayLoad = 1, mayStore = 1 in { 1758def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 1759 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [], 1760 IIC_CMPXCHG_MEM8>, TB; 1761def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1762 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [], 1763 IIC_CMPXCHG_MEM>, TB, OpSize16; 1764def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1765 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [], 1766 IIC_CMPXCHG_MEM>, TB, OpSize32; 1767def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1768 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [], 1769 IIC_CMPXCHG_MEM>, TB; 1770} 1771 1772let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in 1773def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), 1774 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB; 1775 1776let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in 1777def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), 1778 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>, 1779 TB, Requires<[HasCmpxchg16b]>; 1780} // SchedRW 1781 1782 1783// Lock instruction prefix 1784def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>; 1785 1786// Rex64 instruction prefix 1787def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>, 1788 Requires<[In64BitMode]>; 1789 1790// Data16 instruction prefix 1791def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>; 1792 1793// Repeat string operation instruction prefixes 1794// These uses the DF flag in the EFLAGS register to inc or dec ECX 1795let Defs = [ECX], Uses = [ECX,EFLAGS] in { 1796// Repeat (used with INS, OUTS, MOVS, LODS and STOS) 1797def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>; 1798// Repeat while not equal (used with CMPS and SCAS) 1799def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>; 1800} 1801 1802 1803// String manipulation instructions 1804let SchedRW = [WriteMicrocoded] in { 1805// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1806let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in 1807def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src), 1808 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>; 1809let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in 1810def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src), 1811 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16; 1812let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in 1813def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src), 1814 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32; 1815let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in 1816def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src), 1817 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>; 1818} 1819 1820let SchedRW = [WriteSystem] in { 1821// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1822let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in { 1823def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src), 1824 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>; 1825def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src), 1826 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16; 1827def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src), 1828 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32; 1829} 1830 1831// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1832let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in { 1833def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins), 1834 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>; 1835def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins), 1836 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16; 1837def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins), 1838 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32; 1839} 1840} 1841 1842// Flag instructions 1843let SchedRW = [WriteALU] in { 1844def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>; 1845def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>; 1846def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>; 1847def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>; 1848def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>; 1849def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>; 1850def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>; 1851 1852def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB; 1853} 1854 1855// Table lookup instructions 1856def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>, 1857 Sched<[WriteLoad]>; 1858 1859let SchedRW = [WriteMicrocoded] in { 1860// ASCII Adjust After Addition 1861// sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS 1862def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>, 1863 Requires<[Not64BitMode]>; 1864 1865// ASCII Adjust AX Before Division 1866// sets AL, AH and EFLAGS and uses AL and AH 1867def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src), 1868 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>; 1869 1870// ASCII Adjust AX After Multiply 1871// sets AL, AH and EFLAGS and uses AL 1872def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src), 1873 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>; 1874 1875// ASCII Adjust AL After Subtraction - sets 1876// sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS 1877def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>, 1878 Requires<[Not64BitMode]>; 1879 1880// Decimal Adjust AL after Addition 1881// sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS 1882def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>, 1883 Requires<[Not64BitMode]>; 1884 1885// Decimal Adjust AL after Subtraction 1886// sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS 1887def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>, 1888 Requires<[Not64BitMode]>; 1889} // SchedRW 1890 1891let SchedRW = [WriteSystem] in { 1892// Check Array Index Against Bounds 1893def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1894 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16, 1895 Requires<[Not64BitMode]>; 1896def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1897 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32, 1898 Requires<[Not64BitMode]>; 1899 1900// Adjust RPL Field of Segment Selector 1901def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1902 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>, 1903 Requires<[Not64BitMode]>; 1904def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1905 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>, 1906 Requires<[Not64BitMode]>; 1907} // SchedRW 1908 1909//===----------------------------------------------------------------------===// 1910// MOVBE Instructions 1911// 1912let Predicates = [HasMOVBE] in { 1913 let SchedRW = [WriteALULd] in { 1914 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1915 "movbe{w}\t{$src, $dst|$dst, $src}", 1916 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>, 1917 OpSize16, T8PS; 1918 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1919 "movbe{l}\t{$src, $dst|$dst, $src}", 1920 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>, 1921 OpSize32, T8PS; 1922 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1923 "movbe{q}\t{$src, $dst|$dst, $src}", 1924 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>, 1925 T8PS; 1926 } 1927 let SchedRW = [WriteStore] in { 1928 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1929 "movbe{w}\t{$src, $dst|$dst, $src}", 1930 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>, 1931 OpSize16, T8PS; 1932 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1933 "movbe{l}\t{$src, $dst|$dst, $src}", 1934 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>, 1935 OpSize32, T8PS; 1936 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1937 "movbe{q}\t{$src, $dst|$dst, $src}", 1938 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>, 1939 T8PS; 1940 } 1941} 1942 1943//===----------------------------------------------------------------------===// 1944// RDRAND Instruction 1945// 1946let Predicates = [HasRDRAND], Defs = [EFLAGS] in { 1947 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins), 1948 "rdrand{w}\t$dst", 1949 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB; 1950 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins), 1951 "rdrand{l}\t$dst", 1952 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB; 1953 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins), 1954 "rdrand{q}\t$dst", 1955 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB; 1956} 1957 1958//===----------------------------------------------------------------------===// 1959// RDSEED Instruction 1960// 1961let Predicates = [HasRDSEED], Defs = [EFLAGS] in { 1962 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins), 1963 "rdseed{w}\t$dst", 1964 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB; 1965 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins), 1966 "rdseed{l}\t$dst", 1967 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB; 1968 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins), 1969 "rdseed{q}\t$dst", 1970 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB; 1971} 1972 1973//===----------------------------------------------------------------------===// 1974// LZCNT Instruction 1975// 1976let Predicates = [HasLZCNT], Defs = [EFLAGS] in { 1977 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1978 "lzcnt{w}\t{$src, $dst|$dst, $src}", 1979 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS, 1980 OpSize16; 1981 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1982 "lzcnt{w}\t{$src, $dst|$dst, $src}", 1983 [(set GR16:$dst, (ctlz (loadi16 addr:$src))), 1984 (implicit EFLAGS)]>, XS, OpSize16; 1985 1986 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1987 "lzcnt{l}\t{$src, $dst|$dst, $src}", 1988 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS, 1989 OpSize32; 1990 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1991 "lzcnt{l}\t{$src, $dst|$dst, $src}", 1992 [(set GR32:$dst, (ctlz (loadi32 addr:$src))), 1993 (implicit EFLAGS)]>, XS, OpSize32; 1994 1995 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1996 "lzcnt{q}\t{$src, $dst|$dst, $src}", 1997 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>, 1998 XS; 1999 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2000 "lzcnt{q}\t{$src, $dst|$dst, $src}", 2001 [(set GR64:$dst, (ctlz (loadi64 addr:$src))), 2002 (implicit EFLAGS)]>, XS; 2003} 2004 2005let Predicates = [HasLZCNT] in { 2006 def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E), 2007 (X86cmp GR16:$src, (i16 0))), 2008 (LZCNT16rr GR16:$src)>; 2009 def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E), 2010 (X86cmp GR32:$src, (i32 0))), 2011 (LZCNT32rr GR32:$src)>; 2012 def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E), 2013 (X86cmp GR64:$src, (i64 0))), 2014 (LZCNT64rr GR64:$src)>; 2015 def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E), 2016 (X86cmp GR16:$src, (i16 0))), 2017 (LZCNT16rr GR16:$src)>; 2018 def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E), 2019 (X86cmp GR32:$src, (i32 0))), 2020 (LZCNT32rr GR32:$src)>; 2021 def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E), 2022 (X86cmp GR64:$src, (i64 0))), 2023 (LZCNT64rr GR64:$src)>; 2024 2025 def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E), 2026 (X86cmp (loadi16 addr:$src), (i16 0))), 2027 (LZCNT16rm addr:$src)>; 2028 def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E), 2029 (X86cmp (loadi32 addr:$src), (i32 0))), 2030 (LZCNT32rm addr:$src)>; 2031 def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E), 2032 (X86cmp (loadi64 addr:$src), (i64 0))), 2033 (LZCNT64rm addr:$src)>; 2034 def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E), 2035 (X86cmp (loadi16 addr:$src), (i16 0))), 2036 (LZCNT16rm addr:$src)>; 2037 def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E), 2038 (X86cmp (loadi32 addr:$src), (i32 0))), 2039 (LZCNT32rm addr:$src)>; 2040 def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E), 2041 (X86cmp (loadi64 addr:$src), (i64 0))), 2042 (LZCNT64rm addr:$src)>; 2043} 2044 2045//===----------------------------------------------------------------------===// 2046// BMI Instructions 2047// 2048let Predicates = [HasBMI], Defs = [EFLAGS] in { 2049 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 2050 "tzcnt{w}\t{$src, $dst|$dst, $src}", 2051 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS, 2052 OpSize16; 2053 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2054 "tzcnt{w}\t{$src, $dst|$dst, $src}", 2055 [(set GR16:$dst, (cttz (loadi16 addr:$src))), 2056 (implicit EFLAGS)]>, XS, OpSize16; 2057 2058 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 2059 "tzcnt{l}\t{$src, $dst|$dst, $src}", 2060 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS, 2061 OpSize32; 2062 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2063 "tzcnt{l}\t{$src, $dst|$dst, $src}", 2064 [(set GR32:$dst, (cttz (loadi32 addr:$src))), 2065 (implicit EFLAGS)]>, XS, OpSize32; 2066 2067 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 2068 "tzcnt{q}\t{$src, $dst|$dst, $src}", 2069 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>, 2070 XS; 2071 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2072 "tzcnt{q}\t{$src, $dst|$dst, $src}", 2073 [(set GR64:$dst, (cttz (loadi64 addr:$src))), 2074 (implicit EFLAGS)]>, XS; 2075} 2076 2077multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM, 2078 RegisterClass RC, X86MemOperand x86memop> { 2079let hasSideEffects = 0 in { 2080 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src), 2081 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), 2082 []>, T8PS, VEX_4V; 2083 let mayLoad = 1 in 2084 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src), 2085 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), 2086 []>, T8PS, VEX_4V; 2087} 2088} 2089 2090let Predicates = [HasBMI], Defs = [EFLAGS] in { 2091 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>; 2092 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W; 2093 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>; 2094 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W; 2095 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>; 2096 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W; 2097} 2098 2099//===----------------------------------------------------------------------===// 2100// Pattern fragments to auto generate BMI instructions. 2101//===----------------------------------------------------------------------===// 2102 2103let Predicates = [HasBMI] in { 2104 // FIXME: patterns for the load versions are not implemented 2105 def : Pat<(and GR32:$src, (add GR32:$src, -1)), 2106 (BLSR32rr GR32:$src)>; 2107 def : Pat<(and GR64:$src, (add GR64:$src, -1)), 2108 (BLSR64rr GR64:$src)>; 2109 2110 def : Pat<(xor GR32:$src, (add GR32:$src, -1)), 2111 (BLSMSK32rr GR32:$src)>; 2112 def : Pat<(xor GR64:$src, (add GR64:$src, -1)), 2113 (BLSMSK64rr GR64:$src)>; 2114 2115 def : Pat<(and GR32:$src, (ineg GR32:$src)), 2116 (BLSI32rr GR32:$src)>; 2117 def : Pat<(and GR64:$src, (ineg GR64:$src)), 2118 (BLSI64rr GR64:$src)>; 2119} 2120 2121let Predicates = [HasBMI] in { 2122 def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E), 2123 (X86cmp GR16:$src, (i16 0))), 2124 (TZCNT16rr GR16:$src)>; 2125 def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E), 2126 (X86cmp GR32:$src, (i32 0))), 2127 (TZCNT32rr GR32:$src)>; 2128 def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E), 2129 (X86cmp GR64:$src, (i64 0))), 2130 (TZCNT64rr GR64:$src)>; 2131 def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E), 2132 (X86cmp GR16:$src, (i16 0))), 2133 (TZCNT16rr GR16:$src)>; 2134 def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E), 2135 (X86cmp GR32:$src, (i32 0))), 2136 (TZCNT32rr GR32:$src)>; 2137 def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E), 2138 (X86cmp GR64:$src, (i64 0))), 2139 (TZCNT64rr GR64:$src)>; 2140 2141 def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E), 2142 (X86cmp (loadi16 addr:$src), (i16 0))), 2143 (TZCNT16rm addr:$src)>; 2144 def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E), 2145 (X86cmp (loadi32 addr:$src), (i32 0))), 2146 (TZCNT32rm addr:$src)>; 2147 def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E), 2148 (X86cmp (loadi64 addr:$src), (i64 0))), 2149 (TZCNT64rm addr:$src)>; 2150 def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E), 2151 (X86cmp (loadi16 addr:$src), (i16 0))), 2152 (TZCNT16rm addr:$src)>; 2153 def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E), 2154 (X86cmp (loadi32 addr:$src), (i32 0))), 2155 (TZCNT32rm addr:$src)>; 2156 def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E), 2157 (X86cmp (loadi64 addr:$src), (i64 0))), 2158 (TZCNT64rm addr:$src)>; 2159} 2160 2161 2162multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC, 2163 X86MemOperand x86memop, Intrinsic Int, 2164 PatFrag ld_frag> { 2165 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2166 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2167 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>, 2168 T8PS, VEX_4VOp3; 2169 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), 2170 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2171 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)), 2172 (implicit EFLAGS)]>, T8PS, VEX_4VOp3; 2173} 2174 2175let Predicates = [HasBMI], Defs = [EFLAGS] in { 2176 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem, 2177 int_x86_bmi_bextr_32, loadi32>; 2178 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem, 2179 int_x86_bmi_bextr_64, loadi64>, VEX_W; 2180} 2181 2182let Predicates = [HasBMI2], Defs = [EFLAGS] in { 2183 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem, 2184 int_x86_bmi_bzhi_32, loadi32>; 2185 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem, 2186 int_x86_bmi_bzhi_64, loadi64>, VEX_W; 2187} 2188 2189 2190def CountTrailingOnes : SDNodeXForm<imm, [{ 2191 // Count the trailing ones in the immediate. 2192 return getI8Imm(CountTrailingOnes_64(N->getZExtValue())); 2193}]>; 2194 2195def BZHIMask : ImmLeaf<i64, [{ 2196 return isMask_64(Imm) && (CountTrailingOnes_64(Imm) > 32); 2197}]>; 2198 2199let Predicates = [HasBMI2] in { 2200 def : Pat<(and GR64:$src, BZHIMask:$mask), 2201 (BZHI64rr GR64:$src, 2202 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2203 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; 2204 2205 def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)), 2206 (BZHI32rr GR32:$src, 2207 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2208 2209 def : Pat<(and (loadi32 addr:$src), (add (shl 1, GR8:$lz), -1)), 2210 (BZHI32rm addr:$src, 2211 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2212 2213 def : Pat<(and GR64:$src, (add (shl 1, GR8:$lz), -1)), 2214 (BZHI64rr GR64:$src, 2215 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2216 2217 def : Pat<(and (loadi64 addr:$src), (add (shl 1, GR8:$lz), -1)), 2218 (BZHI64rm addr:$src, 2219 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2220} // HasBMI2 2221 2222let Predicates = [HasBMI] in { 2223 def : Pat<(X86bextr GR32:$src1, GR32:$src2), 2224 (BEXTR32rr GR32:$src1, GR32:$src2)>; 2225 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2), 2226 (BEXTR32rm addr:$src1, GR32:$src2)>; 2227 def : Pat<(X86bextr GR64:$src1, GR64:$src2), 2228 (BEXTR64rr GR64:$src1, GR64:$src2)>; 2229 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2), 2230 (BEXTR64rm addr:$src1, GR64:$src2)>; 2231} // HasBMI 2232 2233multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC, 2234 X86MemOperand x86memop, Intrinsic Int, 2235 PatFrag ld_frag> { 2236 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2237 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2238 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>, 2239 VEX_4V; 2240 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), 2241 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2242 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V; 2243} 2244 2245let Predicates = [HasBMI2] in { 2246 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, 2247 int_x86_bmi_pdep_32, loadi32>, T8XD; 2248 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, 2249 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W; 2250 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, 2251 int_x86_bmi_pext_32, loadi32>, T8XS; 2252 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, 2253 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W; 2254} 2255 2256//===----------------------------------------------------------------------===// 2257// TBM Instructions 2258// 2259let Predicates = [HasTBM], Defs = [EFLAGS] in { 2260 2261multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr, 2262 X86MemOperand x86memop, PatFrag ld_frag, 2263 Intrinsic Int, Operand immtype, 2264 SDPatternOperator immoperator> { 2265 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl), 2266 !strconcat(OpcodeStr, 2267 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2268 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>, 2269 XOP, XOPA; 2270 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst), 2271 (ins x86memop:$src1, immtype:$cntl), 2272 !strconcat(OpcodeStr, 2273 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2274 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>, 2275 XOP, XOPA; 2276} 2277 2278defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32, 2279 int_x86_tbm_bextri_u32, i32imm, imm>; 2280let ImmT = Imm32S in 2281defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64, 2282 int_x86_tbm_bextri_u64, i64i32imm, 2283 i64immSExt32>, VEX_W; 2284 2285multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem, 2286 RegisterClass RC, string OpcodeStr, 2287 X86MemOperand x86memop, PatFrag ld_frag> { 2288let hasSideEffects = 0 in { 2289 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src), 2290 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), 2291 []>, XOP_4V, XOP9; 2292 let mayLoad = 1 in 2293 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src), 2294 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), 2295 []>, XOP_4V, XOP9; 2296} 2297} 2298 2299multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr, 2300 Format FormReg, Format FormMem> { 2301 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem, 2302 loadi32>; 2303 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem, 2304 loadi64>, VEX_W; 2305} 2306 2307defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>; 2308defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>; 2309defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>; 2310defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>; 2311defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>; 2312defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>; 2313defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>; 2314defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>; 2315defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>; 2316} // HasTBM, EFLAGS 2317 2318//===----------------------------------------------------------------------===// 2319// Pattern fragments to auto generate TBM instructions. 2320//===----------------------------------------------------------------------===// 2321 2322let Predicates = [HasTBM] in { 2323 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)), 2324 (BEXTRI32ri GR32:$src1, imm:$src2)>; 2325 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)), 2326 (BEXTRI32mi addr:$src1, imm:$src2)>; 2327 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2), 2328 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>; 2329 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2), 2330 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>; 2331 2332 // FIXME: patterns for the load versions are not implemented 2333 def : Pat<(and GR32:$src, (add GR32:$src, 1)), 2334 (BLCFILL32rr GR32:$src)>; 2335 def : Pat<(and GR64:$src, (add GR64:$src, 1)), 2336 (BLCFILL64rr GR64:$src)>; 2337 2338 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))), 2339 (BLCI32rr GR32:$src)>; 2340 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))), 2341 (BLCI64rr GR64:$src)>; 2342 2343 // Extra patterns because opt can optimize the above patterns to this. 2344 def : Pat<(or GR32:$src, (sub -2, GR32:$src)), 2345 (BLCI32rr GR32:$src)>; 2346 def : Pat<(or GR64:$src, (sub -2, GR64:$src)), 2347 (BLCI64rr GR64:$src)>; 2348 2349 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)), 2350 (BLCIC32rr GR32:$src)>; 2351 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)), 2352 (BLCIC64rr GR64:$src)>; 2353 2354 def : Pat<(xor GR32:$src, (add GR32:$src, 1)), 2355 (BLCMSK32rr GR32:$src)>; 2356 def : Pat<(xor GR64:$src, (add GR64:$src, 1)), 2357 (BLCMSK64rr GR64:$src)>; 2358 2359 def : Pat<(or GR32:$src, (add GR32:$src, 1)), 2360 (BLCS32rr GR32:$src)>; 2361 def : Pat<(or GR64:$src, (add GR64:$src, 1)), 2362 (BLCS64rr GR64:$src)>; 2363 2364 def : Pat<(or GR32:$src, (add GR32:$src, -1)), 2365 (BLSFILL32rr GR32:$src)>; 2366 def : Pat<(or GR64:$src, (add GR64:$src, -1)), 2367 (BLSFILL64rr GR64:$src)>; 2368 2369 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)), 2370 (BLSIC32rr GR32:$src)>; 2371 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)), 2372 (BLSIC64rr GR64:$src)>; 2373 2374 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)), 2375 (T1MSKC32rr GR32:$src)>; 2376 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)), 2377 (T1MSKC64rr GR64:$src)>; 2378 2379 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)), 2380 (TZMSK32rr GR32:$src)>; 2381 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)), 2382 (TZMSK64rr GR64:$src)>; 2383} // HasTBM 2384 2385//===----------------------------------------------------------------------===// 2386// Subsystems. 2387//===----------------------------------------------------------------------===// 2388 2389include "X86InstrArithmetic.td" 2390include "X86InstrCMovSetCC.td" 2391include "X86InstrExtension.td" 2392include "X86InstrControl.td" 2393include "X86InstrShiftRotate.td" 2394 2395// X87 Floating Point Stack. 2396include "X86InstrFPStack.td" 2397 2398// SIMD support (SSE, MMX and AVX) 2399include "X86InstrFragmentsSIMD.td" 2400 2401// FMA - Fused Multiply-Add support (requires FMA) 2402include "X86InstrFMA.td" 2403 2404// XOP 2405include "X86InstrXOP.td" 2406 2407// SSE, MMX and 3DNow! vector support. 2408include "X86InstrSSE.td" 2409include "X86InstrAVX512.td" 2410include "X86InstrMMX.td" 2411include "X86Instr3DNow.td" 2412 2413include "X86InstrVMX.td" 2414include "X86InstrSVM.td" 2415 2416include "X86InstrTSX.td" 2417 2418// System instructions. 2419include "X86InstrSystem.td" 2420 2421// Compiler Pseudo Instructions and Pat Patterns 2422include "X86InstrCompiler.td" 2423 2424//===----------------------------------------------------------------------===// 2425// Assembler Mnemonic Aliases 2426//===----------------------------------------------------------------------===// 2427 2428def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>; 2429def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>; 2430def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>; 2431 2432def : MnemonicAlias<"cbw", "cbtw", "att">; 2433def : MnemonicAlias<"cwde", "cwtl", "att">; 2434def : MnemonicAlias<"cwd", "cwtd", "att">; 2435def : MnemonicAlias<"cdq", "cltd", "att">; 2436def : MnemonicAlias<"cdqe", "cltq", "att">; 2437def : MnemonicAlias<"cqo", "cqto", "att">; 2438 2439// In 64-bit mode lret maps to lretl; it is not ambiguous with lretq. 2440def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>; 2441def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>; 2442 2443def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>; 2444def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>; 2445 2446def : MnemonicAlias<"loopz", "loope", "att">; 2447def : MnemonicAlias<"loopnz", "loopne", "att">; 2448 2449def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>; 2450def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>; 2451def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>; 2452def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>; 2453def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>; 2454def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>; 2455def : MnemonicAlias<"popfd", "popfl", "att">; 2456 2457// FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in 2458// all modes. However: "push (addr)" and "push $42" should default to 2459// pushl/pushq depending on the current mode. Similar for "pop %bx" 2460def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>; 2461def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>; 2462def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>; 2463def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>; 2464def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>; 2465def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 2466def : MnemonicAlias<"pushfd", "pushfl", "att">; 2467 2468def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>; 2469def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>; 2470def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>; 2471def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>; 2472def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>; 2473def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>; 2474 2475def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>; 2476def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>; 2477def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>; 2478def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>; 2479 2480def : MnemonicAlias<"repe", "rep", "att">; 2481def : MnemonicAlias<"repz", "rep", "att">; 2482def : MnemonicAlias<"repnz", "repne", "att">; 2483 2484def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>; 2485def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>; 2486def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>; 2487 2488def : MnemonicAlias<"salb", "shlb", "att">; 2489def : MnemonicAlias<"salw", "shlw", "att">; 2490def : MnemonicAlias<"sall", "shll", "att">; 2491def : MnemonicAlias<"salq", "shlq", "att">; 2492 2493def : MnemonicAlias<"smovb", "movsb", "att">; 2494def : MnemonicAlias<"smovw", "movsw", "att">; 2495def : MnemonicAlias<"smovl", "movsl", "att">; 2496def : MnemonicAlias<"smovq", "movsq", "att">; 2497 2498def : MnemonicAlias<"ud2a", "ud2", "att">; 2499def : MnemonicAlias<"verrw", "verr", "att">; 2500 2501// System instruction aliases. 2502def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>; 2503def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>; 2504def : MnemonicAlias<"sysret", "sysretl", "att">; 2505def : MnemonicAlias<"sysexit", "sysexitl", "att">; 2506 2507def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>; 2508def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>; 2509def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>; 2510def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>; 2511def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>; 2512def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>; 2513def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>; 2514def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>; 2515def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>; 2516def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>; 2517def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>; 2518def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>; 2519 2520 2521// Floating point stack aliases. 2522def : MnemonicAlias<"fcmovz", "fcmove", "att">; 2523def : MnemonicAlias<"fcmova", "fcmovnbe", "att">; 2524def : MnemonicAlias<"fcmovnae", "fcmovb", "att">; 2525def : MnemonicAlias<"fcmovna", "fcmovbe", "att">; 2526def : MnemonicAlias<"fcmovae", "fcmovnb", "att">; 2527def : MnemonicAlias<"fcomip", "fcompi", "att">; 2528def : MnemonicAlias<"fildq", "fildll", "att">; 2529def : MnemonicAlias<"fistpq", "fistpll", "att">; 2530def : MnemonicAlias<"fisttpq", "fisttpll", "att">; 2531def : MnemonicAlias<"fldcww", "fldcw", "att">; 2532def : MnemonicAlias<"fnstcww", "fnstcw", "att">; 2533def : MnemonicAlias<"fnstsww", "fnstsw", "att">; 2534def : MnemonicAlias<"fucomip", "fucompi", "att">; 2535def : MnemonicAlias<"fwait", "wait", "att">; 2536 2537 2538class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond, 2539 string VariantName> 2540 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix), 2541 !strconcat(Prefix, NewCond, Suffix), VariantName>; 2542 2543/// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of 2544/// MnemonicAlias's that canonicalize the condition code in a mnemonic, for 2545/// example "setz" -> "sete". 2546multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix, 2547 string V = ""> { 2548 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb 2549 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete 2550 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe 2551 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae 2552 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae 2553 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle 2554 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge 2555 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne 2556 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp 2557 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp 2558 2559 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb 2560 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta 2561 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl 2562 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg 2563} 2564 2565// Aliases for set<CC> 2566defm : IntegerCondCodeMnemonicAlias<"set", "">; 2567// Aliases for j<CC> 2568defm : IntegerCondCodeMnemonicAlias<"j", "">; 2569// Aliases for cmov<CC>{w,l,q} 2570defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">; 2571defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">; 2572defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">; 2573// No size suffix for intel-style asm. 2574defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">; 2575 2576 2577//===----------------------------------------------------------------------===// 2578// Assembler Instruction Aliases 2579//===----------------------------------------------------------------------===// 2580 2581// aad/aam default to base 10 if no operand is specified. 2582def : InstAlias<"aad", (AAD8i8 10)>; 2583def : InstAlias<"aam", (AAM8i8 10)>; 2584 2585// Disambiguate the mem/imm form of bt-without-a-suffix as btl. 2586// Likewise for btc/btr/bts. 2587def : InstAlias<"bt {$imm, $mem|$mem, $imm}", 2588 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2589def : InstAlias<"btc {$imm, $mem|$mem, $imm}", 2590 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2591def : InstAlias<"btr {$imm, $mem|$mem, $imm}", 2592 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2593def : InstAlias<"bts {$imm, $mem|$mem, $imm}", 2594 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2595 2596// clr aliases. 2597def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>; 2598def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>; 2599def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>; 2600def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>; 2601 2602// lods aliases. Accept the destination being omitted because it's implicit 2603// in the mnemonic, or the mnemonic suffix being omitted because it's implicit 2604// in the destination. 2605def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>; 2606def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>; 2607def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>; 2608def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 2609def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>; 2610def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>; 2611def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>; 2612def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 2613 2614// stos aliases. Accept the source being omitted because it's implicit in 2615// the mnemonic, or the mnemonic suffix being omitted because it's implicit 2616// in the source. 2617def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>; 2618def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>; 2619def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>; 2620def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2621def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>; 2622def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>; 2623def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>; 2624def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2625 2626// scas aliases. Accept the destination being omitted because it's implicit 2627// in the mnemonic, or the mnemonic suffix being omitted because it's implicit 2628// in the destination. 2629def : InstAlias<"scasb $dst", (SCASB dstidx8:$dst), 0>; 2630def : InstAlias<"scasw $dst", (SCASW dstidx16:$dst), 0>; 2631def : InstAlias<"scas{l|d} $dst", (SCASL dstidx32:$dst), 0>; 2632def : InstAlias<"scasq $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2633def : InstAlias<"scas {$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>; 2634def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>; 2635def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>; 2636def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2637 2638// div and idiv aliases for explicit A register. 2639def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>; 2640def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>; 2641def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>; 2642def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>; 2643def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>; 2644def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>; 2645def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>; 2646def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>; 2647def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>; 2648def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>; 2649def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>; 2650def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>; 2651def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>; 2652def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>; 2653def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>; 2654def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>; 2655 2656 2657 2658// Various unary fpstack operations default to operating on on ST1. 2659// For example, "fxch" -> "fxch %st(1)" 2660def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; 2661def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>; 2662def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>; 2663def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>; 2664def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>; 2665def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>; 2666def : InstAlias<"fxch", (XCH_F ST1), 0>; 2667def : InstAlias<"fcom", (COM_FST0r ST1), 0>; 2668def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>; 2669def : InstAlias<"fcomi", (COM_FIr ST1), 0>; 2670def : InstAlias<"fcompi", (COM_FIPr ST1), 0>; 2671def : InstAlias<"fucom", (UCOM_Fr ST1), 0>; 2672def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>; 2673def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>; 2674def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>; 2675 2676// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. 2677// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate 2678// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with 2679// gas. 2680multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> { 2681 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"), 2682 (Inst RST:$op), EmitAlias>; 2683 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"), 2684 (Inst ST0), EmitAlias>; 2685} 2686 2687defm : FpUnaryAlias<"fadd", ADD_FST0r>; 2688defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; 2689defm : FpUnaryAlias<"fsub", SUB_FST0r>; 2690defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>; 2691defm : FpUnaryAlias<"fsubr", SUBR_FST0r>; 2692defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>; 2693defm : FpUnaryAlias<"fmul", MUL_FST0r>; 2694defm : FpUnaryAlias<"fmulp", MUL_FPrST0>; 2695defm : FpUnaryAlias<"fdiv", DIV_FST0r>; 2696defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>; 2697defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; 2698defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>; 2699defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; 2700defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; 2701defm : FpUnaryAlias<"fcompi", COM_FIPr>; 2702defm : FpUnaryAlias<"fucompi", UCOM_FIPr>; 2703 2704 2705// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they 2706// commute. We also allow fdiv[r]p/fsubrp even though they don't commute, 2707// solely because gas supports it. 2708def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>; 2709def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>; 2710def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>; 2711def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>; 2712def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>; 2713def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>; 2714 2715// We accept "fnstsw %eax" even though it only writes %ax. 2716def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>; 2717def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>; 2718def : InstAlias<"fnstsw" , (FNSTSW16r)>; 2719 2720// lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but 2721// this is compatible with what GAS does. 2722def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>; 2723def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>; 2724def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>; 2725def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>; 2726def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 2727def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 2728def : InstAlias<"lcall *$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>; 2729def : InstAlias<"ljmp *$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>; 2730 2731def : InstAlias<"call *$dst", (CALL64m i16mem:$dst), 0>, Requires<[In64BitMode]>; 2732def : InstAlias<"jmp *$dst", (JMP64m i16mem:$dst), 0>, Requires<[In64BitMode]>; 2733def : InstAlias<"call *$dst", (CALL32m i16mem:$dst), 0>, Requires<[In32BitMode]>; 2734def : InstAlias<"jmp *$dst", (JMP32m i16mem:$dst), 0>, Requires<[In32BitMode]>; 2735def : InstAlias<"call *$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>; 2736def : InstAlias<"jmp *$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>; 2737 2738 2739// "imul <imm>, B" is an alias for "imul <imm>, B, B". 2740def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>; 2741def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>; 2742def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>; 2743def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>; 2744def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>; 2745def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>; 2746 2747// inb %dx -> inb %al, %dx 2748def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>; 2749def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>; 2750def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>; 2751def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>; 2752def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>; 2753def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>; 2754 2755 2756// jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp 2757def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 2758def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 2759def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>; 2760def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>; 2761def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>; 2762def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>; 2763def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; 2764def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; 2765 2766// Force mov without a suffix with a segment and mem to prefer the 'l' form of 2767// the move. All segment/mem forms are equivalent, this has the shortest 2768// encoding. 2769def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>; 2770def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>; 2771 2772// Match 'movq <largeimm>, <reg>' as an alias for movabsq. 2773def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm), 0>; 2774 2775// Match 'movq GR64, MMX' as an alias for movd. 2776def : InstAlias<"movq $src, $dst", 2777 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; 2778def : InstAlias<"movq $src, $dst", 2779 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; 2780 2781// movsx aliases 2782def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>; 2783def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>; 2784def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>; 2785def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>; 2786def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>; 2787def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>; 2788def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>; 2789 2790// movzx aliases 2791def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>; 2792def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>; 2793def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>; 2794def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>; 2795def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>; 2796def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>; 2797// Note: No GR32->GR64 movzx form. 2798 2799// outb %dx -> outb %al, %dx 2800def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>; 2801def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>; 2802def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>; 2803def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>; 2804def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>; 2805def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>; 2806 2807// 'sldt <mem>' can be encoded with either sldtw or sldtq with the same 2808// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity 2809// errors, since its encoding is the most compact. 2810def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>; 2811 2812// shld/shrd op,op -> shld op, op, CL 2813def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>; 2814def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>; 2815def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>; 2816def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>; 2817def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>; 2818def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>; 2819 2820def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>; 2821def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>; 2822def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>; 2823def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>; 2824def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>; 2825def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>; 2826 2827/* FIXME: This is disabled because the asm matcher is currently incapable of 2828 * matching a fixed immediate like $1. 2829// "shl X, $1" is an alias for "shl X". 2830multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> { 2831 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 2832 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>; 2833 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 2834 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>; 2835 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 2836 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>; 2837 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 2838 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>; 2839 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 2840 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>; 2841 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 2842 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>; 2843 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 2844 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>; 2845 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 2846 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>; 2847} 2848 2849defm : ShiftRotateByOneAlias<"rcl", "RCL">; 2850defm : ShiftRotateByOneAlias<"rcr", "RCR">; 2851defm : ShiftRotateByOneAlias<"rol", "ROL">; 2852defm : ShiftRotateByOneAlias<"ror", "ROR">; 2853FIXME */ 2854 2855// test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms. 2856def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}", 2857 (TEST8rm GR8 :$val, i8mem :$mem), 0>; 2858def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}", 2859 (TEST16rm GR16:$val, i16mem:$mem), 0>; 2860def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}", 2861 (TEST32rm GR32:$val, i32mem:$mem), 0>; 2862def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}", 2863 (TEST64rm GR64:$val, i64mem:$mem), 0>; 2864 2865// xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms. 2866def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", 2867 (XCHG8rm GR8 :$val, i8mem :$mem), 0>; 2868def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", 2869 (XCHG16rm GR16:$val, i16mem:$mem), 0>; 2870def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", 2871 (XCHG32rm GR32:$val, i32mem:$mem), 0>; 2872def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", 2873 (XCHG64rm GR64:$val, i64mem:$mem), 0>; 2874 2875// xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms. 2876def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>; 2877def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", 2878 (XCHG32ar GR32:$src), 0>, Requires<[Not64BitMode]>; 2879def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", 2880 (XCHG32ar64 GR32_NOAX:$src), 0>, Requires<[In64BitMode]>; 2881def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>; 2882