X86InstrSystem.td revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
1//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 instructions that are generally used in 11// privileged modes. These are not typically used by the compiler, but are 12// supported for the assembler and disassembler. 13// 14//===----------------------------------------------------------------------===// 15 16let SchedRW = [WriteSystem] in { 17let Defs = [RAX, RDX] in 18 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>, 19 TB; 20 21let Defs = [RAX, RCX, RDX] in 22 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)]>, TB; 23 24// CPU flow control instructions 25 26let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in { 27 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB; 28 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB; 29} 30 31def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>; 32def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB; 33 34// Interrupt and SysCall Instructions. 35let Uses = [EFLAGS] in 36 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>; 37def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", 38 [(int_x86_int (i8 3))], IIC_INT3>; 39} // SchedRW 40 41def : Pat<(debugtrap), 42 (INT3)>; 43 44// The long form of "int $3" turns into int3 as a size optimization. 45// FIXME: This doesn't work because InstAlias can't match immediate constants. 46//def : InstAlias<"int\t$3", (INT3)>; 47 48let SchedRW = [WriteSystem] in { 49 50def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", 51 [(int_x86_int imm:$trap)], IIC_INT>; 52 53 54def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB; 55def SYSRET : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB; 56def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB, 57 Requires<[In64BitMode]>; 58 59def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", [], 60 IIC_SYS_ENTER_EXIT>, TB; 61 62def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", [], 63 IIC_SYS_ENTER_EXIT>, TB; 64def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", [], 65 IIC_SYS_ENTER_EXIT>, TB, Requires<[In64BitMode]>; 66 67def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize16; 68def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], IIC_IRET>, 69 OpSize32; 70def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", [], IIC_IRET>, 71 Requires<[In64BitMode]>; 72} // SchedRW 73 74 75//===----------------------------------------------------------------------===// 76// Input/Output Instructions. 77// 78let SchedRW = [WriteSystem] in { 79let Defs = [AL], Uses = [DX] in 80def IN8rr : I<0xEC, RawFrm, (outs), (ins), 81 "in{b}\t{%dx, %al|al, dx}", [], IIC_IN_RR>; 82let Defs = [AX], Uses = [DX] in 83def IN16rr : I<0xED, RawFrm, (outs), (ins), 84 "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>, OpSize16; 85let Defs = [EAX], Uses = [DX] in 86def IN32rr : I<0xED, RawFrm, (outs), (ins), 87 "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize32; 88 89let Defs = [AL] in 90def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port), 91 "in{b}\t{$port, %al|al, $port}", [], IIC_IN_RI>; 92let Defs = [AX] in 93def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port), 94 "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize16; 95let Defs = [EAX] in 96def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port), 97 "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize32; 98 99let Uses = [DX, AL] in 100def OUT8rr : I<0xEE, RawFrm, (outs), (ins), 101 "out{b}\t{%al, %dx|dx, al}", [], IIC_OUT_RR>; 102let Uses = [DX, AX] in 103def OUT16rr : I<0xEF, RawFrm, (outs), (ins), 104 "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize16; 105let Uses = [DX, EAX] in 106def OUT32rr : I<0xEF, RawFrm, (outs), (ins), 107 "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize32; 108 109let Uses = [AL] in 110def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port), 111 "out{b}\t{%al, $port|$port, al}", [], IIC_OUT_IR>; 112let Uses = [AX] in 113def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port), 114 "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize16; 115let Uses = [EAX] in 116def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port), 117 "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize32; 118 119} // SchedRW 120 121//===----------------------------------------------------------------------===// 122// Moves to and from debug registers 123 124let SchedRW = [WriteSystem] in { 125def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src), 126 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB, 127 Requires<[Not64BitMode]>; 128def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src), 129 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB, 130 Requires<[In64BitMode]>; 131 132def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src), 133 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB, 134 Requires<[Not64BitMode]>; 135def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src), 136 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB, 137 Requires<[In64BitMode]>; 138} // SchedRW 139 140//===----------------------------------------------------------------------===// 141// Moves to and from control registers 142 143let SchedRW = [WriteSystem] in { 144def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src), 145 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB, 146 Requires<[Not64BitMode]>; 147def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src), 148 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB, 149 Requires<[In64BitMode]>; 150 151def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src), 152 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB, 153 Requires<[Not64BitMode]>; 154def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src), 155 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB, 156 Requires<[In64BitMode]>; 157} // SchedRW 158 159//===----------------------------------------------------------------------===// 160// Segment override instruction prefixes 161 162def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>; 163def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>; 164def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>; 165def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>; 166def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>; 167def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>; 168 169 170//===----------------------------------------------------------------------===// 171// Moves to and from segment registers. 172// 173 174let SchedRW = [WriteMove] in { 175def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src), 176 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16; 177def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src), 178 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize32; 179def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src), 180 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>; 181 182def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src), 183 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize16; 184def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src), 185 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize32; 186def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src), 187 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>; 188 189def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src), 190 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16; 191def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src), 192 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize32; 193def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src), 194 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>; 195 196def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src), 197 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize16; 198def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src), 199 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize32; 200def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src), 201 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>; 202} // SchedRW 203 204//===----------------------------------------------------------------------===// 205// Segmentation support instructions. 206 207let SchedRW = [WriteSystem] in { 208def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB; 209 210def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 211 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB, 212 OpSize16; 213def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 214 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB, 215 OpSize16; 216 217// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo. 218def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), 219 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB, 220 OpSize32; 221def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 222 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB, 223 OpSize32; 224// i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo. 225def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), 226 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB; 227def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), 228 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB; 229 230def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 231 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB, 232 OpSize16; 233def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 234 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB, 235 OpSize16; 236def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 237 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB, 238 OpSize32; 239def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 240 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB, 241 OpSize32; 242def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 243 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB; 244def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 245 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB; 246 247def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", 248 [], IIC_INVLPG>, TB; 249 250def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins), 251 "str{w}\t$dst", [], IIC_STR>, TB, OpSize16; 252def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins), 253 "str{l}\t$dst", [], IIC_STR>, TB, OpSize32; 254def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins), 255 "str{q}\t$dst", [], IIC_STR>, TB; 256def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins), 257 "str{w}\t$dst", [], IIC_STR>, TB; 258 259def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src), 260 "ltr{w}\t$src", [], IIC_LTR>, TB; 261def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src), 262 "ltr{w}\t$src", [], IIC_LTR>, TB; 263 264def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins), 265 "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>, 266 OpSize16, Requires<[Not64BitMode]>; 267def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins), 268 "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>, 269 OpSize32, Requires<[Not64BitMode]>; 270def PUSHSS16 : I<0x16, RawFrm, (outs), (ins), 271 "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>, 272 OpSize16, Requires<[Not64BitMode]>; 273def PUSHSS32 : I<0x16, RawFrm, (outs), (ins), 274 "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>, 275 OpSize32, Requires<[Not64BitMode]>; 276def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins), 277 "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>, 278 OpSize16, Requires<[Not64BitMode]>; 279def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins), 280 "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>, 281 OpSize32, Requires<[Not64BitMode]>; 282def PUSHES16 : I<0x06, RawFrm, (outs), (ins), 283 "push{w}\t{%es|es}", [], IIC_PUSH_SR>, 284 OpSize16, Requires<[Not64BitMode]>; 285def PUSHES32 : I<0x06, RawFrm, (outs), (ins), 286 "push{l}\t{%es|es}", [], IIC_PUSH_SR>, 287 OpSize32, Requires<[Not64BitMode]>; 288def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins), 289 "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize16, TB; 290def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins), 291 "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB, 292 OpSize32, Requires<[Not64BitMode]>; 293def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins), 294 "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize16, TB; 295def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins), 296 "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB, 297 OpSize32, Requires<[Not64BitMode]>; 298def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins), 299 "push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB, 300 OpSize32, Requires<[In64BitMode]>; 301def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins), 302 "push{q}\t{%gs|gs}", [], IIC_PUSH_SR>, TB, 303 OpSize32, Requires<[In64BitMode]>; 304 305// No "pop cs" instruction. 306def POPSS16 : I<0x17, RawFrm, (outs), (ins), 307 "pop{w}\t{%ss|ss}", [], IIC_POP_SR_SS>, 308 OpSize16, Requires<[Not64BitMode]>; 309def POPSS32 : I<0x17, RawFrm, (outs), (ins), 310 "pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>, 311 OpSize32, Requires<[Not64BitMode]>; 312 313def POPDS16 : I<0x1F, RawFrm, (outs), (ins), 314 "pop{w}\t{%ds|ds}", [], IIC_POP_SR>, 315 OpSize16, Requires<[Not64BitMode]>; 316def POPDS32 : I<0x1F, RawFrm, (outs), (ins), 317 "pop{l}\t{%ds|ds}", [], IIC_POP_SR>, 318 OpSize32, Requires<[Not64BitMode]>; 319 320def POPES16 : I<0x07, RawFrm, (outs), (ins), 321 "pop{w}\t{%es|es}", [], IIC_POP_SR>, 322 OpSize16, Requires<[Not64BitMode]>; 323def POPES32 : I<0x07, RawFrm, (outs), (ins), 324 "pop{l}\t{%es|es}", [], IIC_POP_SR>, 325 OpSize32, Requires<[Not64BitMode]>; 326 327def POPFS16 : I<0xa1, RawFrm, (outs), (ins), 328 "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize16, TB; 329def POPFS32 : I<0xa1, RawFrm, (outs), (ins), 330 "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB, 331 OpSize32, Requires<[Not64BitMode]>; 332def POPFS64 : I<0xa1, RawFrm, (outs), (ins), 333 "pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB, 334 OpSize32, Requires<[In64BitMode]>; 335 336def POPGS16 : I<0xa9, RawFrm, (outs), (ins), 337 "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize16, TB; 338def POPGS32 : I<0xa9, RawFrm, (outs), (ins), 339 "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB, 340 OpSize32, Requires<[Not64BitMode]>; 341def POPGS64 : I<0xa9, RawFrm, (outs), (ins), 342 "pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB, 343 OpSize32, Requires<[In64BitMode]>; 344 345 346def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src), 347 "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16; 348def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src), 349 "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32; 350 351def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src), 352 "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16; 353def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src), 354 "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32; 355def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src), 356 "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB; 357 358def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src), 359 "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16; 360def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src), 361 "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32; 362 363def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src), 364 "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16; 365def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src), 366 "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32; 367def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src), 368 "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB; 369 370def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src), 371 "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16; 372def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src), 373 "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32; 374 375def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src), 376 "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB; 377 378 379def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), 380 "verr\t$seg", [], IIC_VERR>, TB; 381def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg), 382 "verr\t$seg", [], IIC_VERR>, TB; 383def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), 384 "verw\t$seg", [], IIC_VERW_MEM>, TB; 385def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg), 386 "verw\t$seg", [], IIC_VERW_REG>, TB; 387} // SchedRW 388 389//===----------------------------------------------------------------------===// 390// Descriptor-table support instructions 391 392let SchedRW = [WriteSystem] in { 393def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins), 394 "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize16, Requires<[Not64BitMode]>; 395def SGDT32m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins), 396 "sgdt{l}\t$dst", [], IIC_SGDT>, OpSize32, TB, Requires <[Not64BitMode]>; 397def SGDT64m : I<0x01, MRM0m, (outs opaque80mem:$dst), (ins), 398 "sgdt{q}\t$dst", [], IIC_SGDT>, TB, Requires <[In64BitMode]>; 399def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins), 400 "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize16, Requires<[Not64BitMode]>; 401def SIDT32m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins), 402 "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>; 403def SIDT64m : I<0x01, MRM1m, (outs opaque80mem:$dst), (ins), 404 "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>; 405def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins), 406 "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize16; 407def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins), 408 "sldt{w}\t$dst", [], IIC_SLDT>, TB; 409def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins), 410 "sldt{l}\t$dst", [], IIC_SLDT>, OpSize32, TB; 411 412// LLDT is not interpreted specially in 64-bit mode because there is no sign 413// extension. 414def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins), 415 "sldt{q}\t$dst", [], IIC_SLDT>, TB; 416def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins), 417 "sldt{q}\t$dst", [], IIC_SLDT>, TB; 418 419def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src), 420 "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize16, Requires<[Not64BitMode]>; 421def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src), 422 "lgdt{l}\t$src", [], IIC_LGDT>, OpSize32, TB, Requires<[Not64BitMode]>; 423def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src), 424 "lgdt{q}\t$src", [], IIC_LGDT>, TB, Requires<[In64BitMode]>; 425def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src), 426 "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize16, Requires<[Not64BitMode]>; 427def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src), 428 "lidt{l}\t$src", [], IIC_LIDT>, OpSize32, TB, Requires<[Not64BitMode]>; 429def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src), 430 "lidt{q}\t$src", [], IIC_LIDT>, TB, Requires<[In64BitMode]>; 431def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src), 432 "lldt{w}\t$src", [], IIC_LLDT_REG>, TB; 433def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src), 434 "lldt{w}\t$src", [], IIC_LLDT_MEM>, TB; 435} // SchedRW 436 437//===----------------------------------------------------------------------===// 438// Specialized register support 439let SchedRW = [WriteSystem] in { 440def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB; 441def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB; 442def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [], IIC_RDPMC>, TB; 443 444def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins), 445 "smsw{w}\t$dst", [], IIC_SMSW>, OpSize16, TB; 446def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins), 447 "smsw{l}\t$dst", [], IIC_SMSW>, OpSize32, TB; 448// no m form encodable; use SMSW16m 449def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins), 450 "smsw{q}\t$dst", [], IIC_SMSW>, TB; 451 452// For memory operands, there is only a 16-bit form 453def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins), 454 "smsw{w}\t$dst", [], IIC_SMSW>, TB; 455 456def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src), 457 "lmsw{w}\t$src", [], IIC_LMSW_MEM>, TB; 458def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src), 459 "lmsw{w}\t$src", [], IIC_LMSW_REG>, TB; 460 461let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in 462 def CPUID32 : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB, 463 Requires<[Not64BitMode]>; 464let Defs = [RAX, RBX, RCX, RDX], Uses = [RAX, RCX] in 465 def CPUID64 : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB, 466 Requires<[In64BitMode]>; 467} // SchedRW 468 469//===----------------------------------------------------------------------===// 470// Cache instructions 471let SchedRW = [WriteSystem] in { 472def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB; 473def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB; 474} // SchedRW 475 476//===----------------------------------------------------------------------===// 477// XSAVE instructions 478let SchedRW = [WriteSystem] in { 479let Defs = [RDX, RAX], Uses = [RCX] in 480 def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB; 481 482let Uses = [RDX, RAX, RCX] in 483 def XSETBV : I<0x01, MRM_D1, (outs), (ins), "xsetbv", []>, TB; 484 485let Uses = [RDX, RAX] in { 486 def XSAVE : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins), 487 "xsave\t$dst", []>, TB; 488 def XSAVE64 : RI<0xAE, MRM4m, (outs opaque512mem:$dst), (ins), 489 "xsave{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>; 490 def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst), 491 "xrstor\t$dst", []>, TB; 492 def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst), 493 "xrstor{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>; 494 def XSAVEOPT : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins), 495 "xsaveopt\t$dst", []>, TB; 496 def XSAVEOPT64 : RI<0xAE, MRM6m, (outs opaque512mem:$dst), (ins), 497 "xsaveopt{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>; 498} 499} // SchedRW 500 501//===----------------------------------------------------------------------===// 502// VIA PadLock crypto instructions 503let Defs = [RAX, RDI], Uses = [RDX, RDI] in 504 def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB; 505 506def : InstAlias<"xstorerng", (XSTORE)>; 507 508let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in { 509 def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB; 510 def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB; 511 def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB; 512 def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB; 513 def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB; 514} 515 516let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in { 517 def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB; 518 def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB; 519} 520let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in 521 def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB; 522 523//===----------------------------------------------------------------------===// 524// FS/GS Base Instructions 525let Predicates = [HasFSGSBase, In64BitMode] in { 526 def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins), 527 "rdfsbase{l}\t$dst", 528 [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS; 529 def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins), 530 "rdfsbase{q}\t$dst", 531 [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS; 532 def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins), 533 "rdgsbase{l}\t$dst", 534 [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS; 535 def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins), 536 "rdgsbase{q}\t$dst", 537 [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS; 538 def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src), 539 "wrfsbase{l}\t$src", 540 [(int_x86_wrfsbase_32 GR32:$src)]>, XS; 541 def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src), 542 "wrfsbase{q}\t$src", 543 [(int_x86_wrfsbase_64 GR64:$src)]>, XS; 544 def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src), 545 "wrgsbase{l}\t$src", 546 [(int_x86_wrgsbase_32 GR32:$src)]>, XS; 547 def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src), 548 "wrgsbase{q}\t$src", 549 [(int_x86_wrgsbase_64 GR64:$src)]>, XS; 550} 551 552//===----------------------------------------------------------------------===// 553// INVPCID Instruction 554def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2), 555 "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD, 556 Requires<[Not64BitMode]>; 557def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), 558 "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD, 559 Requires<[In64BitMode]>; 560 561//===----------------------------------------------------------------------===// 562// SMAP Instruction 563let Defs = [EFLAGS], Uses = [EFLAGS] in { 564 def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB; 565 def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB; 566} 567