X86InstrXOP.td revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- X86InstrXOP.td - XOP Instruction Set ---------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes XOP (eXtended OPerations)
11//
12//===----------------------------------------------------------------------===//
13
14multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> {
15  def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
16           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
17           [(set VR128:$dst, (Int VR128:$src))]>, XOP;
18  def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
19           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
20           [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP;
21}
22
23defm VPHSUBWD  : xop2op<0xE2, "vphsubwd", int_x86_xop_vphsubwd, memopv2i64>;
24defm VPHSUBDQ  : xop2op<0xE3, "vphsubdq", int_x86_xop_vphsubdq, memopv2i64>;
25defm VPHSUBBW  : xop2op<0xE1, "vphsubbw", int_x86_xop_vphsubbw, memopv2i64>;
26defm VPHADDWQ  : xop2op<0xC7, "vphaddwq", int_x86_xop_vphaddwq, memopv2i64>;
27defm VPHADDWD  : xop2op<0xC6, "vphaddwd", int_x86_xop_vphaddwd, memopv2i64>;
28defm VPHADDUWQ : xop2op<0xD7, "vphadduwq", int_x86_xop_vphadduwq, memopv2i64>;
29defm VPHADDUWD : xop2op<0xD6, "vphadduwd", int_x86_xop_vphadduwd, memopv2i64>;
30defm VPHADDUDQ : xop2op<0xDB, "vphaddudq", int_x86_xop_vphaddudq, memopv2i64>;
31defm VPHADDUBW : xop2op<0xD1, "vphaddubw", int_x86_xop_vphaddubw, memopv2i64>;
32defm VPHADDUBQ : xop2op<0xD3, "vphaddubq", int_x86_xop_vphaddubq, memopv2i64>;
33defm VPHADDUBD : xop2op<0xD2, "vphaddubd", int_x86_xop_vphaddubd, memopv2i64>;
34defm VPHADDDQ  : xop2op<0xCB, "vphadddq", int_x86_xop_vphadddq, memopv2i64>;
35defm VPHADDBW  : xop2op<0xC1, "vphaddbw", int_x86_xop_vphaddbw, memopv2i64>;
36defm VPHADDBQ  : xop2op<0xC3, "vphaddbq", int_x86_xop_vphaddbq, memopv2i64>;
37defm VPHADDBD  : xop2op<0xC2, "vphaddbd", int_x86_xop_vphaddbd, memopv2i64>;
38
39// Scalar load 2 addr operand instructions
40multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int,
41                     Operand memop, ComplexPattern mem_cpat> {
42  def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
43           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
44           [(set VR128:$dst, (Int VR128:$src))]>, XOP;
45  def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
46           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
47           [(set VR128:$dst, (Int (bitconvert mem_cpat:$src)))]>, XOP;
48}
49
50defm VFRCZSS   : xop2opsld<0x82, "vfrczss", int_x86_xop_vfrcz_ss,
51                 ssmem, sse_load_f32>;
52defm VFRCZSD   : xop2opsld<0x83, "vfrczsd", int_x86_xop_vfrcz_sd,
53                 sdmem, sse_load_f64>;
54
55multiclass xop2op128<bits<8> opc, string OpcodeStr, Intrinsic Int,
56                     PatFrag memop> {
57  def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
58           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
59           [(set VR128:$dst, (Int VR128:$src))]>, XOP;
60  def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
61           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
62           [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP;
63}
64
65defm VFRCZPS : xop2op128<0x80, "vfrczps", int_x86_xop_vfrcz_ps, memopv4f32>;
66defm VFRCZPD : xop2op128<0x81, "vfrczpd", int_x86_xop_vfrcz_pd, memopv2f64>;
67
68multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int,
69                     PatFrag memop> {
70  def rrY : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
71           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
72           [(set VR256:$dst, (Int VR256:$src))]>, XOP, VEX_L;
73  def rmY : IXOP<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
74           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
75           [(set VR256:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP, VEX_L;
76}
77
78defm VFRCZPS : xop2op256<0x80, "vfrczps", int_x86_xop_vfrcz_ps_256, memopv8f32>;
79defm VFRCZPD : xop2op256<0x81, "vfrczpd", int_x86_xop_vfrcz_pd_256, memopv4f64>;
80
81multiclass xop3op<bits<8> opc, string OpcodeStr, Intrinsic Int> {
82  def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
83           (ins VR128:$src1, VR128:$src2),
84           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
85           [(set VR128:$dst, (Int VR128:$src1, VR128:$src2))]>, XOP_4VOp3;
86  def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
87           (ins VR128:$src1, i128mem:$src2),
88           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
89           [(set VR128:$dst,
90              (Int VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))]>,
91           XOP_4V, VEX_W;
92  def mr : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
93           (ins i128mem:$src1, VR128:$src2),
94           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
95           [(set VR128:$dst,
96              (Int (bitconvert (memopv2i64 addr:$src1)), VR128:$src2))]>,
97             XOP_4VOp3;
98}
99
100defm VPSHLW : xop3op<0x95, "vpshlw", int_x86_xop_vpshlw>;
101defm VPSHLQ : xop3op<0x97, "vpshlq", int_x86_xop_vpshlq>;
102defm VPSHLD : xop3op<0x96, "vpshld", int_x86_xop_vpshld>;
103defm VPSHLB : xop3op<0x94, "vpshlb", int_x86_xop_vpshlb>;
104defm VPSHAW : xop3op<0x99, "vpshaw", int_x86_xop_vpshaw>;
105defm VPSHAQ : xop3op<0x9B, "vpshaq", int_x86_xop_vpshaq>;
106defm VPSHAD : xop3op<0x9A, "vpshad", int_x86_xop_vpshad>;
107defm VPSHAB : xop3op<0x98, "vpshab", int_x86_xop_vpshab>;
108defm VPROTW : xop3op<0x91, "vprotw", int_x86_xop_vprotw>;
109defm VPROTQ : xop3op<0x93, "vprotq", int_x86_xop_vprotq>;
110defm VPROTD : xop3op<0x92, "vprotd", int_x86_xop_vprotd>;
111defm VPROTB : xop3op<0x90, "vprotb", int_x86_xop_vprotb>;
112
113multiclass xop3opimm<bits<8> opc, string OpcodeStr, Intrinsic Int> {
114  def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
115           (ins VR128:$src1, i8imm:$src2),
116           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
117           [(set VR128:$dst, (Int VR128:$src1, imm:$src2))]>, XOP;
118  def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
119           (ins i128mem:$src1, i8imm:$src2),
120           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
121           [(set VR128:$dst,
122             (Int (bitconvert (memopv2i64 addr:$src1)), imm:$src2))]>, XOP;
123}
124
125defm VPROTW : xop3opimm<0xC1, "vprotw", int_x86_xop_vprotwi>;
126defm VPROTQ : xop3opimm<0xC3, "vprotq", int_x86_xop_vprotqi>;
127defm VPROTD : xop3opimm<0xC2, "vprotd", int_x86_xop_vprotdi>;
128defm VPROTB : xop3opimm<0xC0, "vprotb", int_x86_xop_vprotbi>;
129
130// Instruction where second source can be memory, but third must be register
131multiclass xop4opm2<bits<8> opc, string OpcodeStr, Intrinsic Int> {
132  def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
133           (ins VR128:$src1, VR128:$src2, VR128:$src3),
134           !strconcat(OpcodeStr,
135           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
136           [(set VR128:$dst,
137              (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_4V, VEX_I8IMM;
138  def rm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
139           (ins VR128:$src1, i128mem:$src2, VR128:$src3),
140           !strconcat(OpcodeStr,
141           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
142           [(set VR128:$dst,
143              (Int VR128:$src1, (bitconvert (memopv2i64 addr:$src2)),
144              VR128:$src3))]>, XOP_4V, VEX_I8IMM;
145}
146
147defm VPMADCSWD  : xop4opm2<0xB6, "vpmadcswd", int_x86_xop_vpmadcswd>;
148defm VPMADCSSWD : xop4opm2<0xA6, "vpmadcsswd", int_x86_xop_vpmadcsswd>;
149defm VPMACSWW   : xop4opm2<0x95, "vpmacsww", int_x86_xop_vpmacsww>;
150defm VPMACSWD   : xop4opm2<0x96, "vpmacswd", int_x86_xop_vpmacswd>;
151defm VPMACSSWW  : xop4opm2<0x85, "vpmacssww", int_x86_xop_vpmacssww>;
152defm VPMACSSWD  : xop4opm2<0x86, "vpmacsswd", int_x86_xop_vpmacsswd>;
153defm VPMACSSDQL : xop4opm2<0x87, "vpmacssdql", int_x86_xop_vpmacssdql>;
154defm VPMACSSDQH : xop4opm2<0x8F, "vpmacssdqh", int_x86_xop_vpmacssdqh>;
155defm VPMACSSDD  : xop4opm2<0x8E, "vpmacssdd", int_x86_xop_vpmacssdd>;
156defm VPMACSDQL  : xop4opm2<0x97, "vpmacsdql", int_x86_xop_vpmacsdql>;
157defm VPMACSDQH  : xop4opm2<0x9F, "vpmacsdqh", int_x86_xop_vpmacsdqh>;
158defm VPMACSDD   : xop4opm2<0x9E, "vpmacsdd", int_x86_xop_vpmacsdd>;
159
160// Instruction where second source can be memory, third must be imm8
161multiclass xop4opimm<bits<8> opc, string OpcodeStr, Intrinsic Int> {
162  def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
163           (ins VR128:$src1, VR128:$src2, i8imm:$src3),
164           !strconcat(OpcodeStr,
165           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
166           [(set VR128:$dst, (Int VR128:$src1, VR128:$src2, imm:$src3))]>,
167           XOP_4V;
168  def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
169           (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
170           !strconcat(OpcodeStr,
171           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
172           [(set VR128:$dst,
173             (Int VR128:$src1, (bitconvert (memopv2i64 addr:$src2)),
174              imm:$src3))]>, XOP_4V;
175}
176
177defm VPCOMB  : xop4opimm<0xCC, "vpcomb", int_x86_xop_vpcomb>;
178defm VPCOMW  : xop4opimm<0xCD, "vpcomw", int_x86_xop_vpcomw>;
179defm VPCOMD  : xop4opimm<0xCE, "vpcomd", int_x86_xop_vpcomd>;
180defm VPCOMQ  : xop4opimm<0xCF, "vpcomq", int_x86_xop_vpcomq>;
181defm VPCOMUB : xop4opimm<0xEC, "vpcomub", int_x86_xop_vpcomub>;
182defm VPCOMUW : xop4opimm<0xED, "vpcomuw", int_x86_xop_vpcomuw>;
183defm VPCOMUD : xop4opimm<0xEE, "vpcomud", int_x86_xop_vpcomud>;
184defm VPCOMUQ : xop4opimm<0xEF, "vpcomuq", int_x86_xop_vpcomuq>;
185
186// Instruction where either second or third source can be memory
187multiclass xop4op<bits<8> opc, string OpcodeStr, Intrinsic Int> {
188  def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
189           (ins VR128:$src1, VR128:$src2, VR128:$src3),
190           !strconcat(OpcodeStr,
191           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
192           [(set VR128:$dst, (Int VR128:$src1, VR128:$src2, VR128:$src3))]>,
193           XOP_4V, VEX_I8IMM;
194  def rm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
195           (ins VR128:$src1, VR128:$src2, i128mem:$src3),
196           !strconcat(OpcodeStr,
197           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
198           [(set VR128:$dst,
199             (Int VR128:$src1, VR128:$src2,
200              (bitconvert (memopv2i64 addr:$src3))))]>,
201           XOP_4V, VEX_I8IMM, VEX_W, MemOp4;
202  def mr : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
203           (ins VR128:$src1, i128mem:$src2, VR128:$src3),
204           !strconcat(OpcodeStr,
205           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
206           [(set VR128:$dst,
207             (Int VR128:$src1, (bitconvert (memopv2i64 addr:$src2)),
208              VR128:$src3))]>,
209           XOP_4V, VEX_I8IMM;
210}
211
212defm VPPERM : xop4op<0xA3, "vpperm", int_x86_xop_vpperm>;
213defm VPCMOV : xop4op<0xA2, "vpcmov", int_x86_xop_vpcmov>;
214
215multiclass xop4op256<bits<8> opc, string OpcodeStr, Intrinsic Int> {
216  def rrY : IXOPi8<opc, MRMSrcReg, (outs VR256:$dst),
217           (ins VR256:$src1, VR256:$src2, VR256:$src3),
218           !strconcat(OpcodeStr,
219           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
220           [(set VR256:$dst, (Int VR256:$src1, VR256:$src2, VR256:$src3))]>,
221           XOP_4V, VEX_I8IMM, VEX_L;
222  def rmY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
223           (ins VR256:$src1, VR256:$src2, i256mem:$src3),
224           !strconcat(OpcodeStr,
225           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
226           [(set VR256:$dst,
227             (Int VR256:$src1, VR256:$src2,
228              (bitconvert (memopv4i64 addr:$src3))))]>,
229           XOP_4V, VEX_I8IMM, VEX_W, MemOp4, VEX_L;
230  def mrY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
231           (ins VR256:$src1, f256mem:$src2, VR256:$src3),
232           !strconcat(OpcodeStr,
233           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
234           [(set VR256:$dst,
235             (Int VR256:$src1, (bitconvert (memopv4i64 addr:$src2)),
236              VR256:$src3))]>,
237           XOP_4V, VEX_I8IMM, VEX_L;
238}
239
240defm VPCMOV : xop4op256<0xA2, "vpcmov", int_x86_xop_vpcmov_256>;
241
242multiclass xop5op<bits<8> opc, string OpcodeStr, Intrinsic Int128,
243                  Intrinsic Int256, PatFrag ld_128, PatFrag ld_256> {
244  def rr : IXOP5<opc, MRMSrcReg, (outs VR128:$dst),
245        (ins VR128:$src1, VR128:$src2, VR128:$src3, i8imm:$src4),
246        !strconcat(OpcodeStr,
247        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
248        [(set VR128:$dst,
249           (Int128 VR128:$src1, VR128:$src2, VR128:$src3, imm:$src4))]>;
250  def rm : IXOP5<opc, MRMSrcMem, (outs VR128:$dst),
251        (ins VR128:$src1, VR128:$src2, f128mem:$src3, i8imm:$src4),
252        !strconcat(OpcodeStr,
253        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
254        [(set VR128:$dst,
255           (Int128 VR128:$src1, VR128:$src2, (ld_128 addr:$src3), imm:$src4))]>,
256        VEX_W, MemOp4;
257  def mr : IXOP5<opc, MRMSrcMem, (outs VR128:$dst),
258        (ins VR128:$src1, f128mem:$src2, VR128:$src3, i8imm:$src4),
259        !strconcat(OpcodeStr,
260        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
261        [(set VR128:$dst,
262           (Int128 VR128:$src1, (ld_128 addr:$src2), VR128:$src3, imm:$src4))]>;
263  def rrY : IXOP5<opc, MRMSrcReg, (outs VR256:$dst),
264        (ins VR256:$src1, VR256:$src2, VR256:$src3, i8imm:$src4),
265        !strconcat(OpcodeStr,
266        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
267        [(set VR256:$dst,
268          (Int256 VR256:$src1, VR256:$src2, VR256:$src3, imm:$src4))]>, VEX_L;
269  def rmY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst),
270        (ins VR256:$src1, VR256:$src2, f256mem:$src3, i8imm:$src4),
271        !strconcat(OpcodeStr,
272        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
273        [(set VR256:$dst,
274          (Int256 VR256:$src1, VR256:$src2, (ld_256 addr:$src3), imm:$src4))]>,
275        VEX_W, MemOp4, VEX_L;
276  def mrY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst),
277        (ins VR256:$src1, f256mem:$src2, VR256:$src3, i8imm:$src4),
278        !strconcat(OpcodeStr,
279        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
280        [(set VR256:$dst,
281           (Int256 VR256:$src1, (ld_256 addr:$src2), VR256:$src3, imm:$src4))]>,
282        VEX_L;
283}
284
285defm VPERMIL2PD : xop5op<0x49, "vpermil2pd", int_x86_xop_vpermil2pd,
286                         int_x86_xop_vpermil2pd_256, memopv2f64, memopv4f64>;
287defm VPERMIL2PS : xop5op<0x48, "vpermil2ps", int_x86_xop_vpermil2ps,
288                         int_x86_xop_vpermil2ps_256, memopv4f32, memopv8f32>;
289
290