X86MCInstLower.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains code to lower X86 MachineInstrs to their corresponding 11// MCInst records. 12// 13//===----------------------------------------------------------------------===// 14 15#include "X86AsmPrinter.h" 16#include "InstPrinter/X86ATTInstPrinter.h" 17#include "MCTargetDesc/X86BaseInfo.h" 18#include "llvm/ADT/SmallString.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineModuleInfoImpls.h" 21#include "llvm/CodeGen/StackMaps.h" 22#include "llvm/IR/DataLayout.h" 23#include "llvm/IR/GlobalValue.h" 24#include "llvm/IR/Mangler.h" 25#include "llvm/MC/MCAsmInfo.h" 26#include "llvm/MC/MCContext.h" 27#include "llvm/MC/MCExpr.h" 28#include "llvm/MC/MCInst.h" 29#include "llvm/MC/MCInstBuilder.h" 30#include "llvm/MC/MCStreamer.h" 31#include "llvm/MC/MCSymbol.h" 32using namespace llvm; 33 34namespace { 35 36/// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst. 37class X86MCInstLower { 38 MCContext &Ctx; 39 const MachineFunction &MF; 40 const TargetMachine &TM; 41 const MCAsmInfo &MAI; 42 X86AsmPrinter &AsmPrinter; 43public: 44 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter); 45 46 void Lower(const MachineInstr *MI, MCInst &OutMI) const; 47 48 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const; 49 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const; 50 51private: 52 MachineModuleInfoMachO &getMachOMMI() const; 53 Mangler *getMang() const { 54 return AsmPrinter.Mang; 55 } 56}; 57 58} // end anonymous namespace 59 60X86MCInstLower::X86MCInstLower(const MachineFunction &mf, 61 X86AsmPrinter &asmprinter) 62: Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), 63 MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {} 64 65MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const { 66 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>(); 67} 68 69 70/// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol 71/// operand to an MCSymbol. 72MCSymbol *X86MCInstLower:: 73GetSymbolFromOperand(const MachineOperand &MO) const { 74 const DataLayout *DL = TM.getDataLayout(); 75 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference"); 76 77 SmallString<128> Name; 78 StringRef Suffix; 79 80 switch (MO.getTargetFlags()) { 81 case X86II::MO_DLLIMPORT: 82 // Handle dllimport linkage. 83 Name += "__imp_"; 84 break; 85 case X86II::MO_DARWIN_STUB: 86 Suffix = "$stub"; 87 break; 88 case X86II::MO_DARWIN_NONLAZY: 89 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: 90 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: 91 Suffix = "$non_lazy_ptr"; 92 break; 93 } 94 95 if (!Suffix.empty()) 96 Name += DL->getPrivateGlobalPrefix(); 97 98 unsigned PrefixLen = Name.size(); 99 100 if (MO.isGlobal()) { 101 const GlobalValue *GV = MO.getGlobal(); 102 AsmPrinter.getNameWithPrefix(Name, GV); 103 } else if (MO.isSymbol()) { 104 getMang()->getNameWithPrefix(Name, MO.getSymbolName()); 105 } else if (MO.isMBB()) { 106 Name += MO.getMBB()->getSymbol()->getName(); 107 } 108 unsigned OrigLen = Name.size() - PrefixLen; 109 110 Name += Suffix; 111 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name); 112 113 StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen); 114 115 // If the target flags on the operand changes the name of the symbol, do that 116 // before we return the symbol. 117 switch (MO.getTargetFlags()) { 118 default: break; 119 case X86II::MO_DARWIN_NONLAZY: 120 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: { 121 MachineModuleInfoImpl::StubValueTy &StubSym = 122 getMachOMMI().getGVStubEntry(Sym); 123 if (StubSym.getPointer() == 0) { 124 assert(MO.isGlobal() && "Extern symbol not handled yet"); 125 StubSym = 126 MachineModuleInfoImpl:: 127 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()), 128 !MO.getGlobal()->hasInternalLinkage()); 129 } 130 break; 131 } 132 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: { 133 MachineModuleInfoImpl::StubValueTy &StubSym = 134 getMachOMMI().getHiddenGVStubEntry(Sym); 135 if (StubSym.getPointer() == 0) { 136 assert(MO.isGlobal() && "Extern symbol not handled yet"); 137 StubSym = 138 MachineModuleInfoImpl:: 139 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()), 140 !MO.getGlobal()->hasInternalLinkage()); 141 } 142 break; 143 } 144 case X86II::MO_DARWIN_STUB: { 145 MachineModuleInfoImpl::StubValueTy &StubSym = 146 getMachOMMI().getFnStubEntry(Sym); 147 if (StubSym.getPointer()) 148 return Sym; 149 150 if (MO.isGlobal()) { 151 StubSym = 152 MachineModuleInfoImpl:: 153 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()), 154 !MO.getGlobal()->hasInternalLinkage()); 155 } else { 156 StubSym = 157 MachineModuleInfoImpl:: 158 StubValueTy(Ctx.GetOrCreateSymbol(OrigName), false); 159 } 160 break; 161 } 162 } 163 164 return Sym; 165} 166 167MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO, 168 MCSymbol *Sym) const { 169 // FIXME: We would like an efficient form for this, so we don't have to do a 170 // lot of extra uniquing. 171 const MCExpr *Expr = 0; 172 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None; 173 174 switch (MO.getTargetFlags()) { 175 default: llvm_unreachable("Unknown target flag on GV operand"); 176 case X86II::MO_NO_FLAG: // No flag. 177 // These affect the name of the symbol, not any suffix. 178 case X86II::MO_DARWIN_NONLAZY: 179 case X86II::MO_DLLIMPORT: 180 case X86II::MO_DARWIN_STUB: 181 break; 182 183 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break; 184 case X86II::MO_TLVP_PIC_BASE: 185 Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx); 186 // Subtract the pic base. 187 Expr = MCBinaryExpr::CreateSub(Expr, 188 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), 189 Ctx), 190 Ctx); 191 break; 192 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break; 193 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break; 194 case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break; 195 case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break; 196 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break; 197 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break; 198 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break; 199 case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break; 200 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break; 201 case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break; 202 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break; 203 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break; 204 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break; 205 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break; 206 case X86II::MO_PIC_BASE_OFFSET: 207 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: 208 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: 209 Expr = MCSymbolRefExpr::Create(Sym, Ctx); 210 // Subtract the pic base. 211 Expr = MCBinaryExpr::CreateSub(Expr, 212 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx), 213 Ctx); 214 if (MO.isJTI() && MAI.hasSetDirective()) { 215 // If .set directive is supported, use it to reduce the number of 216 // relocations the assembler will generate for differences between 217 // local labels. This is only safe when the symbols are in the same 218 // section so we are restricting it to jumptable references. 219 MCSymbol *Label = Ctx.CreateTempSymbol(); 220 AsmPrinter.OutStreamer.EmitAssignment(Label, Expr); 221 Expr = MCSymbolRefExpr::Create(Label, Ctx); 222 } 223 break; 224 } 225 226 if (Expr == 0) 227 Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx); 228 229 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset()) 230 Expr = MCBinaryExpr::CreateAdd(Expr, 231 MCConstantExpr::Create(MO.getOffset(), Ctx), 232 Ctx); 233 return MCOperand::CreateExpr(Expr); 234} 235 236 237/// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with 238/// a short fixed-register form. 239static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) { 240 unsigned ImmOp = Inst.getNumOperands() - 1; 241 assert(Inst.getOperand(0).isReg() && 242 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && 243 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && 244 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || 245 Inst.getNumOperands() == 2) && "Unexpected instruction!"); 246 247 // Check whether the destination register can be fixed. 248 unsigned Reg = Inst.getOperand(0).getReg(); 249 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 250 return; 251 252 // If so, rewrite the instruction. 253 MCOperand Saved = Inst.getOperand(ImmOp); 254 Inst = MCInst(); 255 Inst.setOpcode(Opcode); 256 Inst.addOperand(Saved); 257} 258 259/// \brief If a movsx instruction has a shorter encoding for the used register 260/// simplify the instruction to use it instead. 261static void SimplifyMOVSX(MCInst &Inst) { 262 unsigned NewOpcode = 0; 263 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg(); 264 switch (Inst.getOpcode()) { 265 default: 266 llvm_unreachable("Unexpected instruction!"); 267 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw 268 if (Op0 == X86::AX && Op1 == X86::AL) 269 NewOpcode = X86::CBW; 270 break; 271 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl 272 if (Op0 == X86::EAX && Op1 == X86::AX) 273 NewOpcode = X86::CWDE; 274 break; 275 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq 276 if (Op0 == X86::RAX && Op1 == X86::EAX) 277 NewOpcode = X86::CDQE; 278 break; 279 } 280 281 if (NewOpcode != 0) { 282 Inst = MCInst(); 283 Inst.setOpcode(NewOpcode); 284 } 285} 286 287/// \brief Simplify things like MOV32rm to MOV32o32a. 288static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, 289 unsigned Opcode) { 290 // Don't make these simplifications in 64-bit mode; other assemblers don't 291 // perform them because they make the code larger. 292 if (Printer.getSubtarget().is64Bit()) 293 return; 294 295 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg(); 296 unsigned AddrBase = IsStore; 297 unsigned RegOp = IsStore ? 0 : 5; 298 unsigned AddrOp = AddrBase + 3; 299 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && 300 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && 301 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && 302 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && 303 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && 304 (Inst.getOperand(AddrOp).isExpr() || 305 Inst.getOperand(AddrOp).isImm()) && 306 "Unexpected instruction!"); 307 308 // Check whether the destination register can be fixed. 309 unsigned Reg = Inst.getOperand(RegOp).getReg(); 310 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 311 return; 312 313 // Check whether this is an absolute address. 314 // FIXME: We know TLVP symbol refs aren't, but there should be a better way 315 // to do this here. 316 bool Absolute = true; 317 if (Inst.getOperand(AddrOp).isExpr()) { 318 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr(); 319 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE)) 320 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP) 321 Absolute = false; 322 } 323 324 if (Absolute && 325 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 || 326 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 || 327 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0)) 328 return; 329 330 // If so, rewrite the instruction. 331 MCOperand Saved = Inst.getOperand(AddrOp); 332 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg); 333 Inst = MCInst(); 334 Inst.setOpcode(Opcode); 335 Inst.addOperand(Saved); 336 Inst.addOperand(Seg); 337} 338 339static unsigned getRetOpcode(const X86Subtarget &Subtarget) 340{ 341 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL; 342} 343 344void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { 345 OutMI.setOpcode(MI->getOpcode()); 346 347 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 348 const MachineOperand &MO = MI->getOperand(i); 349 350 MCOperand MCOp; 351 switch (MO.getType()) { 352 default: 353 MI->dump(); 354 llvm_unreachable("unknown operand type"); 355 case MachineOperand::MO_Register: 356 // Ignore all implicit register operands. 357 if (MO.isImplicit()) continue; 358 MCOp = MCOperand::CreateReg(MO.getReg()); 359 break; 360 case MachineOperand::MO_Immediate: 361 MCOp = MCOperand::CreateImm(MO.getImm()); 362 break; 363 case MachineOperand::MO_MachineBasicBlock: 364 case MachineOperand::MO_GlobalAddress: 365 case MachineOperand::MO_ExternalSymbol: 366 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO)); 367 break; 368 case MachineOperand::MO_JumpTableIndex: 369 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex())); 370 break; 371 case MachineOperand::MO_ConstantPoolIndex: 372 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex())); 373 break; 374 case MachineOperand::MO_BlockAddress: 375 MCOp = LowerSymbolOperand(MO, 376 AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress())); 377 break; 378 case MachineOperand::MO_RegisterMask: 379 // Ignore call clobbers. 380 continue; 381 } 382 383 OutMI.addOperand(MCOp); 384 } 385 386 // Handle a few special cases to eliminate operand modifiers. 387ReSimplify: 388 switch (OutMI.getOpcode()) { 389 case X86::LEA64_32r: 390 case X86::LEA64r: 391 case X86::LEA16r: 392 case X86::LEA32r: 393 // LEA should have a segment register, but it must be empty. 394 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands && 395 "Unexpected # of LEA operands"); 396 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 && 397 "LEA has segment specified!"); 398 break; 399 400 case X86::MOV32ri64: 401 OutMI.setOpcode(X86::MOV32ri); 402 break; 403 404 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B 405 // if one of the registers is extended, but other isn't. 406 case X86::VMOVAPDrr: 407 case X86::VMOVAPDYrr: 408 case X86::VMOVAPSrr: 409 case X86::VMOVAPSYrr: 410 case X86::VMOVDQArr: 411 case X86::VMOVDQAYrr: 412 case X86::VMOVDQUrr: 413 case X86::VMOVDQUYrr: 414 case X86::VMOVUPDrr: 415 case X86::VMOVUPDYrr: 416 case X86::VMOVUPSrr: 417 case X86::VMOVUPSYrr: { 418 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && 419 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) { 420 unsigned NewOpc; 421 switch (OutMI.getOpcode()) { 422 default: llvm_unreachable("Invalid opcode"); 423 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; 424 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; 425 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; 426 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; 427 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; 428 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; 429 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; 430 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break; 431 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break; 432 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break; 433 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break; 434 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break; 435 } 436 OutMI.setOpcode(NewOpc); 437 } 438 break; 439 } 440 case X86::VMOVSDrr: 441 case X86::VMOVSSrr: { 442 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && 443 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) { 444 unsigned NewOpc; 445 switch (OutMI.getOpcode()) { 446 default: llvm_unreachable("Invalid opcode"); 447 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break; 448 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break; 449 } 450 OutMI.setOpcode(NewOpc); 451 } 452 break; 453 } 454 455 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register 456 // inputs modeled as normal uses instead of implicit uses. As such, truncate 457 // off all but the first operand (the callee). FIXME: Change isel. 458 case X86::TAILJMPr64: 459 case X86::CALL64r: 460 case X86::CALL64pcrel32: { 461 unsigned Opcode = OutMI.getOpcode(); 462 MCOperand Saved = OutMI.getOperand(0); 463 OutMI = MCInst(); 464 OutMI.setOpcode(Opcode); 465 OutMI.addOperand(Saved); 466 break; 467 } 468 469 case X86::EH_RETURN: 470 case X86::EH_RETURN64: { 471 OutMI = MCInst(); 472 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); 473 break; 474 } 475 476 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions. 477 case X86::TAILJMPr: 478 case X86::TAILJMPd: 479 case X86::TAILJMPd64: { 480 unsigned Opcode; 481 switch (OutMI.getOpcode()) { 482 default: llvm_unreachable("Invalid opcode"); 483 case X86::TAILJMPr: Opcode = X86::JMP32r; break; 484 case X86::TAILJMPd: 485 case X86::TAILJMPd64: Opcode = X86::JMP_1; break; 486 } 487 488 MCOperand Saved = OutMI.getOperand(0); 489 OutMI = MCInst(); 490 OutMI.setOpcode(Opcode); 491 OutMI.addOperand(Saved); 492 break; 493 } 494 495 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do 496 // this with an ugly goto in case the resultant OR uses EAX and needs the 497 // short form. 498 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify; 499 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify; 500 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify; 501 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify; 502 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify; 503 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify; 504 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify; 505 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify; 506 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify; 507 508 // The assembler backend wants to see branches in their small form and relax 509 // them to their large form. The JIT can only handle the large form because 510 // it does not do relaxation. For now, translate the large form to the 511 // small one here. 512 case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break; 513 case X86::JO_4: OutMI.setOpcode(X86::JO_1); break; 514 case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break; 515 case X86::JB_4: OutMI.setOpcode(X86::JB_1); break; 516 case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break; 517 case X86::JE_4: OutMI.setOpcode(X86::JE_1); break; 518 case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break; 519 case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break; 520 case X86::JA_4: OutMI.setOpcode(X86::JA_1); break; 521 case X86::JS_4: OutMI.setOpcode(X86::JS_1); break; 522 case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break; 523 case X86::JP_4: OutMI.setOpcode(X86::JP_1); break; 524 case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break; 525 case X86::JL_4: OutMI.setOpcode(X86::JL_1); break; 526 case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break; 527 case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break; 528 case X86::JG_4: OutMI.setOpcode(X86::JG_1); break; 529 530 // Atomic load and store require a separate pseudo-inst because Acquire 531 // implies mayStore and Release implies mayLoad; fix these to regular MOV 532 // instructions here 533 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify; 534 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify; 535 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify; 536 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify; 537 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify; 538 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify; 539 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify; 540 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify; 541 542 // We don't currently select the correct instruction form for instructions 543 // which have a short %eax, etc. form. Handle this by custom lowering, for 544 // now. 545 // 546 // Note, we are currently not handling the following instructions: 547 // MOV64ao8, MOV64o8a 548 // XCHG16ar, XCHG32ar, XCHG64ar 549 case X86::MOV8mr_NOREX: 550 case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break; 551 case X86::MOV8rm_NOREX: 552 case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break; 553 case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break; 554 case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break; 555 case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break; 556 case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break; 557 558 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break; 559 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break; 560 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break; 561 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break; 562 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break; 563 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break; 564 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break; 565 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break; 566 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break; 567 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break; 568 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break; 569 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break; 570 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break; 571 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break; 572 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break; 573 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break; 574 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break; 575 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break; 576 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break; 577 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break; 578 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break; 579 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break; 580 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break; 581 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break; 582 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break; 583 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break; 584 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break; 585 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break; 586 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break; 587 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break; 588 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break; 589 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break; 590 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break; 591 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break; 592 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break; 593 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break; 594 595 // Try to shrink some forms of movsx. 596 case X86::MOVSX16rr8: 597 case X86::MOVSX32rr16: 598 case X86::MOVSX64rr32: 599 SimplifyMOVSX(OutMI); 600 break; 601 } 602} 603 604static void LowerTlsAddr(MCStreamer &OutStreamer, 605 X86MCInstLower &MCInstLowering, 606 const MachineInstr &MI, 607 const MCSubtargetInfo& STI) { 608 609 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 || 610 MI.getOpcode() == X86::TLS_base_addr64; 611 612 bool needsPadding = MI.getOpcode() == X86::TLS_addr64; 613 614 MCContext &context = OutStreamer.getContext(); 615 616 if (needsPadding) 617 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI); 618 619 MCSymbolRefExpr::VariantKind SRVK; 620 switch (MI.getOpcode()) { 621 case X86::TLS_addr32: 622 case X86::TLS_addr64: 623 SRVK = MCSymbolRefExpr::VK_TLSGD; 624 break; 625 case X86::TLS_base_addr32: 626 SRVK = MCSymbolRefExpr::VK_TLSLDM; 627 break; 628 case X86::TLS_base_addr64: 629 SRVK = MCSymbolRefExpr::VK_TLSLD; 630 break; 631 default: 632 llvm_unreachable("unexpected opcode"); 633 } 634 635 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3)); 636 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context); 637 638 MCInst LEA; 639 if (is64Bits) { 640 LEA.setOpcode(X86::LEA64r); 641 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest 642 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base 643 LEA.addOperand(MCOperand::CreateImm(1)); // scale 644 LEA.addOperand(MCOperand::CreateReg(0)); // index 645 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp 646 LEA.addOperand(MCOperand::CreateReg(0)); // seg 647 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) { 648 LEA.setOpcode(X86::LEA32r); 649 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest 650 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base 651 LEA.addOperand(MCOperand::CreateImm(1)); // scale 652 LEA.addOperand(MCOperand::CreateReg(0)); // index 653 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp 654 LEA.addOperand(MCOperand::CreateReg(0)); // seg 655 } else { 656 LEA.setOpcode(X86::LEA32r); 657 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest 658 LEA.addOperand(MCOperand::CreateReg(0)); // base 659 LEA.addOperand(MCOperand::CreateImm(1)); // scale 660 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index 661 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp 662 LEA.addOperand(MCOperand::CreateReg(0)); // seg 663 } 664 OutStreamer.EmitInstruction(LEA, STI); 665 666 if (needsPadding) { 667 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI); 668 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI); 669 OutStreamer.EmitInstruction(MCInstBuilder(X86::REX64_PREFIX), STI); 670 } 671 672 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr"; 673 MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name); 674 const MCSymbolRefExpr *tlsRef = 675 MCSymbolRefExpr::Create(tlsGetAddr, 676 MCSymbolRefExpr::VK_PLT, 677 context); 678 679 OutStreamer.EmitInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32 680 : X86::CALLpcrel32) 681 .addExpr(tlsRef), STI); 682} 683 684/// \brief Emit the optimal amount of multi-byte nops on X86. 685static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) { 686 // This works only for 64bit. For 32bit we have to do additional checking if 687 // the CPU supports multi-byte nops. 688 assert(Is64Bit && "EmitNops only supports X86-64"); 689 while (NumBytes) { 690 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; 691 Opc = IndexReg = Displacement = SegmentReg = 0; 692 BaseReg = X86::RAX; ScaleVal = 1; 693 switch (NumBytes) { 694 case 0: llvm_unreachable("Zero nops?"); break; 695 case 1: NumBytes -= 1; Opc = X86::NOOP; break; 696 case 2: NumBytes -= 2; Opc = X86::XCHG16ar; break; 697 case 3: NumBytes -= 3; Opc = X86::NOOPL; break; 698 case 4: NumBytes -= 4; Opc = X86::NOOPL; Displacement = 8; break; 699 case 5: NumBytes -= 5; Opc = X86::NOOPL; Displacement = 8; 700 IndexReg = X86::RAX; break; 701 case 6: NumBytes -= 6; Opc = X86::NOOPW; Displacement = 8; 702 IndexReg = X86::RAX; break; 703 case 7: NumBytes -= 7; Opc = X86::NOOPL; Displacement = 512; break; 704 case 8: NumBytes -= 8; Opc = X86::NOOPL; Displacement = 512; 705 IndexReg = X86::RAX; break; 706 case 9: NumBytes -= 9; Opc = X86::NOOPW; Displacement = 512; 707 IndexReg = X86::RAX; break; 708 default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512; 709 IndexReg = X86::RAX; SegmentReg = X86::CS; break; 710 } 711 712 unsigned NumPrefixes = std::min(NumBytes, 5U); 713 NumBytes -= NumPrefixes; 714 for (unsigned i = 0; i != NumPrefixes; ++i) 715 OS.EmitBytes("\x66"); 716 717 switch (Opc) { 718 default: llvm_unreachable("Unexpected opcode"); break; 719 case X86::NOOP: 720 OS.EmitInstruction(MCInstBuilder(Opc), STI); 721 break; 722 case X86::XCHG16ar: 723 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI); 724 break; 725 case X86::NOOPL: 726 case X86::NOOPW: 727 OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg).addImm(ScaleVal) 728 .addReg(IndexReg) 729 .addImm(Displacement) 730 .addReg(SegmentReg), STI); 731 break; 732 } 733 } // while (NumBytes) 734} 735 736// Lower a stackmap of the form: 737// <id>, <shadowBytes>, ... 738static void LowerSTACKMAP(MCStreamer &OS, StackMaps &SM, 739 const MachineInstr &MI, bool Is64Bit, const MCSubtargetInfo& STI) { 740 unsigned NumBytes = MI.getOperand(1).getImm(); 741 SM.recordStackMap(MI); 742 // Emit padding. 743 // FIXME: These nops ensure that the stackmap's shadow is covered by 744 // instructions from the same basic block, but the nops should not be 745 // necessary if instructions from the same block follow the stackmap. 746 EmitNops(OS, NumBytes, Is64Bit, STI); 747} 748 749// Lower a patchpoint of the form: 750// [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ... 751static void LowerPATCHPOINT(MCStreamer &OS, StackMaps &SM, 752 const MachineInstr &MI, bool Is64Bit, const MCSubtargetInfo& STI) { 753 assert(Is64Bit && "Patchpoint currently only supports X86-64"); 754 SM.recordPatchPoint(MI); 755 756 PatchPointOpers opers(&MI); 757 unsigned ScratchIdx = opers.getNextScratchIdx(); 758 unsigned EncodedBytes = 0; 759 int64_t CallTarget = opers.getMetaOper(PatchPointOpers::TargetPos).getImm(); 760 if (CallTarget) { 761 // Emit MOV to materialize the target address and the CALL to target. 762 // This is encoded with 12-13 bytes, depending on which register is used. 763 unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg(); 764 if (X86II::isX86_64ExtendedReg(ScratchReg)) 765 EncodedBytes = 13; 766 else 767 EncodedBytes = 12; 768 OS.EmitInstruction(MCInstBuilder(X86::MOV64ri).addReg(ScratchReg) 769 .addImm(CallTarget), STI); 770 OS.EmitInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg), STI); 771 } 772 // Emit padding. 773 unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm(); 774 assert(NumBytes >= EncodedBytes && 775 "Patchpoint can't request size less than the length of a call."); 776 777 EmitNops(OS, NumBytes - EncodedBytes, Is64Bit, STI); 778} 779 780void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { 781 X86MCInstLower MCInstLowering(*MF, *this); 782 switch (MI->getOpcode()) { 783 case TargetOpcode::DBG_VALUE: 784 llvm_unreachable("Should be handled target independently"); 785 786 // Emit nothing here but a comment if we can. 787 case X86::Int_MemBarrier: 788 OutStreamer.emitRawComment("MEMBARRIER"); 789 return; 790 791 792 case X86::EH_RETURN: 793 case X86::EH_RETURN64: { 794 // Lower these as normal, but add some comments. 795 unsigned Reg = MI->getOperand(0).getReg(); 796 OutStreamer.AddComment(StringRef("eh_return, addr: %") + 797 X86ATTInstPrinter::getRegisterName(Reg)); 798 break; 799 } 800 case X86::TAILJMPr: 801 case X86::TAILJMPd: 802 case X86::TAILJMPd64: 803 // Lower these as normal, but add some comments. 804 OutStreamer.AddComment("TAILCALL"); 805 break; 806 807 case X86::TLS_addr32: 808 case X86::TLS_addr64: 809 case X86::TLS_base_addr32: 810 case X86::TLS_base_addr64: 811 return LowerTlsAddr(OutStreamer, MCInstLowering, *MI, getSubtargetInfo()); 812 813 case X86::MOVPC32r: { 814 // This is a pseudo op for a two instruction sequence with a label, which 815 // looks like: 816 // call "L1$pb" 817 // "L1$pb": 818 // popl %esi 819 820 // Emit the call. 821 MCSymbol *PICBase = MF->getPICBaseSymbol(); 822 // FIXME: We would like an efficient form for this, so we don't have to do a 823 // lot of extra uniquing. 824 EmitToStreamer(OutStreamer, MCInstBuilder(X86::CALLpcrel32) 825 .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext))); 826 827 // Emit the label. 828 OutStreamer.EmitLabel(PICBase); 829 830 // popl $reg 831 EmitToStreamer(OutStreamer, MCInstBuilder(X86::POP32r) 832 .addReg(MI->getOperand(0).getReg())); 833 return; 834 } 835 836 case X86::ADD32ri: { 837 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri. 838 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS) 839 break; 840 841 // Okay, we have something like: 842 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL) 843 844 // For this, we want to print something like: 845 // MYGLOBAL + (. - PICBASE) 846 // However, we can't generate a ".", so just emit a new label here and refer 847 // to it. 848 MCSymbol *DotSym = OutContext.CreateTempSymbol(); 849 OutStreamer.EmitLabel(DotSym); 850 851 // Now that we have emitted the label, lower the complex operand expression. 852 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2)); 853 854 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext); 855 const MCExpr *PICBase = 856 MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext); 857 DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext); 858 859 DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext), 860 DotExpr, OutContext); 861 862 EmitToStreamer(OutStreamer, MCInstBuilder(X86::ADD32ri) 863 .addReg(MI->getOperand(0).getReg()) 864 .addReg(MI->getOperand(1).getReg()) 865 .addExpr(DotExpr)); 866 return; 867 } 868 869 case TargetOpcode::STACKMAP: 870 return LowerSTACKMAP(OutStreamer, SM, *MI, Subtarget->is64Bit(), getSubtargetInfo()); 871 872 case TargetOpcode::PATCHPOINT: 873 return LowerPATCHPOINT(OutStreamer, SM, *MI, Subtarget->is64Bit(), getSubtargetInfo()); 874 875 case X86::MORESTACK_RET: 876 EmitToStreamer(OutStreamer, MCInstBuilder(getRetOpcode(*Subtarget))); 877 return; 878 879 case X86::MORESTACK_RET_RESTORE_R10: 880 // Return, then restore R10. 881 EmitToStreamer(OutStreamer, MCInstBuilder(getRetOpcode(*Subtarget))); 882 EmitToStreamer(OutStreamer, MCInstBuilder(X86::MOV64rr) 883 .addReg(X86::R10) 884 .addReg(X86::RAX)); 885 return; 886 } 887 888 MCInst TmpInst; 889 MCInstLowering.Lower(MI, TmpInst); 890 EmitToStreamer(OutStreamer, TmpInst); 891} 892