X86MCInstLower.cpp revision 72cf01cc7c8f668a17e7fdfe6aaed50e164cac1b 
1//===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains code to lower X86 MachineInstrs to their corresponding
11// MCInst records.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86AsmPrinter.h"
16#include "InstPrinter/X86ATTInstPrinter.h"
17#include "X86COFFMachineModuleInfo.h"
18#include "llvm/ADT/SmallString.h"
19#include "llvm/CodeGen/MachineModuleInfoImpls.h"
20#include "llvm/CodeGen/StackMaps.h"
21#include "llvm/IR/Type.h"
22#include "llvm/MC/MCAsmInfo.h"
23#include "llvm/MC/MCContext.h"
24#include "llvm/MC/MCExpr.h"
25#include "llvm/MC/MCInst.h"
26#include "llvm/MC/MCInstBuilder.h"
27#include "llvm/MC/MCStreamer.h"
28#include "llvm/MC/MCSymbol.h"
29#include "llvm/Support/FormattedStream.h"
30#include "llvm/Target/Mangler.h"
31using namespace llvm;
32
33namespace {
34
35/// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
36class X86MCInstLower {
37  MCContext &Ctx;
38  const MachineFunction &MF;
39  const TargetMachine &TM;
40  const MCAsmInfo &MAI;
41  X86AsmPrinter &AsmPrinter;
42public:
43  X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
44
45  void Lower(const MachineInstr *MI, MCInst &OutMI) const;
46
47  MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
48  MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
49
50private:
51  MachineModuleInfoMachO &getMachOMMI() const;
52  Mangler *getMang() const {
53    return AsmPrinter.Mang;
54  }
55};
56
57} // end anonymous namespace
58
59X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
60                               X86AsmPrinter &asmprinter)
61: Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()),
62  MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {}
63
64MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
65  return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
66}
67
68
69/// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
70/// operand to an MCSymbol.
71MCSymbol *X86MCInstLower::
72GetSymbolFromOperand(const MachineOperand &MO) const {
73  assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
74
75  SmallString<128> Name;
76
77  if (MO.isGlobal()) {
78    const GlobalValue *GV = MO.getGlobal();
79    bool isImplicitlyPrivate = false;
80    if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB ||
81        MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
82        MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE ||
83        MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
84      isImplicitlyPrivate = true;
85
86    getMang()->getNameWithPrefix(Name, GV, isImplicitlyPrivate);
87  } else if (MO.isSymbol()) {
88    Name += MAI.getGlobalPrefix();
89    Name += MO.getSymbolName();
90  } else if (MO.isMBB()) {
91    Name += MO.getMBB()->getSymbol()->getName();
92  }
93
94  // If the target flags on the operand changes the name of the symbol, do that
95  // before we return the symbol.
96  switch (MO.getTargetFlags()) {
97  default: break;
98  case X86II::MO_DLLIMPORT: {
99    // Handle dllimport linkage.
100    const char *Prefix = "__imp_";
101    Name.insert(Name.begin(), Prefix, Prefix+strlen(Prefix));
102    break;
103  }
104  case X86II::MO_DARWIN_NONLAZY:
105  case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
106    Name += "$non_lazy_ptr";
107    MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
108
109    MachineModuleInfoImpl::StubValueTy &StubSym =
110      getMachOMMI().getGVStubEntry(Sym);
111    if (StubSym.getPointer() == 0) {
112      assert(MO.isGlobal() && "Extern symbol not handled yet");
113      StubSym =
114        MachineModuleInfoImpl::
115        StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
116                    !MO.getGlobal()->hasInternalLinkage());
117    }
118    return Sym;
119  }
120  case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
121    Name += "$non_lazy_ptr";
122    MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
123    MachineModuleInfoImpl::StubValueTy &StubSym =
124      getMachOMMI().getHiddenGVStubEntry(Sym);
125    if (StubSym.getPointer() == 0) {
126      assert(MO.isGlobal() && "Extern symbol not handled yet");
127      StubSym =
128        MachineModuleInfoImpl::
129        StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
130                    !MO.getGlobal()->hasInternalLinkage());
131    }
132    return Sym;
133  }
134  case X86II::MO_DARWIN_STUB: {
135    Name += "$stub";
136    MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
137    MachineModuleInfoImpl::StubValueTy &StubSym =
138      getMachOMMI().getFnStubEntry(Sym);
139    if (StubSym.getPointer())
140      return Sym;
141
142    if (MO.isGlobal()) {
143      StubSym =
144        MachineModuleInfoImpl::
145        StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
146                    !MO.getGlobal()->hasInternalLinkage());
147    } else {
148      Name.erase(Name.end()-5, Name.end());
149      StubSym =
150        MachineModuleInfoImpl::
151        StubValueTy(Ctx.GetOrCreateSymbol(Name.str()), false);
152    }
153    return Sym;
154  }
155  }
156
157  return Ctx.GetOrCreateSymbol(Name.str());
158}
159
160MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
161                                             MCSymbol *Sym) const {
162  // FIXME: We would like an efficient form for this, so we don't have to do a
163  // lot of extra uniquing.
164  const MCExpr *Expr = 0;
165  MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
166
167  switch (MO.getTargetFlags()) {
168  default: llvm_unreachable("Unknown target flag on GV operand");
169  case X86II::MO_NO_FLAG:    // No flag.
170  // These affect the name of the symbol, not any suffix.
171  case X86II::MO_DARWIN_NONLAZY:
172  case X86II::MO_DLLIMPORT:
173  case X86II::MO_DARWIN_STUB:
174    break;
175
176  case X86II::MO_TLVP:      RefKind = MCSymbolRefExpr::VK_TLVP; break;
177  case X86II::MO_TLVP_PIC_BASE:
178    Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
179    // Subtract the pic base.
180    Expr = MCBinaryExpr::CreateSub(Expr,
181                                  MCSymbolRefExpr::Create(MF.getPICBaseSymbol(),
182                                                           Ctx),
183                                   Ctx);
184    break;
185  case X86II::MO_SECREL:    RefKind = MCSymbolRefExpr::VK_SECREL; break;
186  case X86II::MO_TLSGD:     RefKind = MCSymbolRefExpr::VK_TLSGD; break;
187  case X86II::MO_TLSLD:     RefKind = MCSymbolRefExpr::VK_TLSLD; break;
188  case X86II::MO_TLSLDM:    RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
189  case X86II::MO_GOTTPOFF:  RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
190  case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
191  case X86II::MO_TPOFF:     RefKind = MCSymbolRefExpr::VK_TPOFF; break;
192  case X86II::MO_DTPOFF:    RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
193  case X86II::MO_NTPOFF:    RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
194  case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
195  case X86II::MO_GOTPCREL:  RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
196  case X86II::MO_GOT:       RefKind = MCSymbolRefExpr::VK_GOT; break;
197  case X86II::MO_GOTOFF:    RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
198  case X86II::MO_PLT:       RefKind = MCSymbolRefExpr::VK_PLT; break;
199  case X86II::MO_PIC_BASE_OFFSET:
200  case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
201  case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
202    Expr = MCSymbolRefExpr::Create(Sym, Ctx);
203    // Subtract the pic base.
204    Expr = MCBinaryExpr::CreateSub(Expr,
205                            MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx),
206                                   Ctx);
207    if (MO.isJTI() && MAI.hasSetDirective()) {
208      // If .set directive is supported, use it to reduce the number of
209      // relocations the assembler will generate for differences between
210      // local labels. This is only safe when the symbols are in the same
211      // section so we are restricting it to jumptable references.
212      MCSymbol *Label = Ctx.CreateTempSymbol();
213      AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
214      Expr = MCSymbolRefExpr::Create(Label, Ctx);
215    }
216    break;
217  }
218
219  if (Expr == 0)
220    Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
221
222  if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
223    Expr = MCBinaryExpr::CreateAdd(Expr,
224                                   MCConstantExpr::Create(MO.getOffset(), Ctx),
225                                   Ctx);
226  return MCOperand::CreateExpr(Expr);
227}
228
229
230/// LowerUnaryToTwoAddr - R = setb   -> R = sbb R, R
231static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) {
232  OutMI.setOpcode(NewOpc);
233  OutMI.addOperand(OutMI.getOperand(0));
234  OutMI.addOperand(OutMI.getOperand(0));
235}
236
237/// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
238/// a short fixed-register form.
239static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
240  unsigned ImmOp = Inst.getNumOperands() - 1;
241  assert(Inst.getOperand(0).isReg() &&
242         (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
243         ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
244           Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
245          Inst.getNumOperands() == 2) && "Unexpected instruction!");
246
247  // Check whether the destination register can be fixed.
248  unsigned Reg = Inst.getOperand(0).getReg();
249  if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
250    return;
251
252  // If so, rewrite the instruction.
253  MCOperand Saved = Inst.getOperand(ImmOp);
254  Inst = MCInst();
255  Inst.setOpcode(Opcode);
256  Inst.addOperand(Saved);
257}
258
259/// \brief If a movsx instruction has a shorter encoding for the used register
260/// simplify the instruction to use it instead.
261static void SimplifyMOVSX(MCInst &Inst) {
262  unsigned NewOpcode = 0;
263  unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
264  switch (Inst.getOpcode()) {
265  default:
266    llvm_unreachable("Unexpected instruction!");
267  case X86::MOVSX16rr8:  // movsbw %al, %ax   --> cbtw
268    if (Op0 == X86::AX && Op1 == X86::AL)
269      NewOpcode = X86::CBW;
270    break;
271  case X86::MOVSX32rr16: // movswl %ax, %eax  --> cwtl
272    if (Op0 == X86::EAX && Op1 == X86::AX)
273      NewOpcode = X86::CWDE;
274    break;
275  case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
276    if (Op0 == X86::RAX && Op1 == X86::EAX)
277      NewOpcode = X86::CDQE;
278    break;
279  }
280
281  if (NewOpcode != 0) {
282    Inst = MCInst();
283    Inst.setOpcode(NewOpcode);
284  }
285}
286
287/// \brief Simplify things like MOV32rm to MOV32o32a.
288static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
289                                  unsigned Opcode) {
290  // Don't make these simplifications in 64-bit mode; other assemblers don't
291  // perform them because they make the code larger.
292  if (Printer.getSubtarget().is64Bit())
293    return;
294
295  bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
296  unsigned AddrBase = IsStore;
297  unsigned RegOp = IsStore ? 0 : 5;
298  unsigned AddrOp = AddrBase + 3;
299  assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
300         Inst.getOperand(AddrBase + 0).isReg() && // base
301         Inst.getOperand(AddrBase + 1).isImm() && // scale
302         Inst.getOperand(AddrBase + 2).isReg() && // index register
303         (Inst.getOperand(AddrOp).isExpr() ||     // address
304          Inst.getOperand(AddrOp).isImm())&&
305         Inst.getOperand(AddrBase + 4).isReg() && // segment
306         "Unexpected instruction!");
307
308  // Check whether the destination register can be fixed.
309  unsigned Reg = Inst.getOperand(RegOp).getReg();
310  if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
311    return;
312
313  // Check whether this is an absolute address.
314  // FIXME: We know TLVP symbol refs aren't, but there should be a better way
315  // to do this here.
316  bool Absolute = true;
317  if (Inst.getOperand(AddrOp).isExpr()) {
318    const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
319    if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
320      if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
321        Absolute = false;
322  }
323
324  if (Absolute &&
325      (Inst.getOperand(AddrBase + 0).getReg() != 0 ||
326       Inst.getOperand(AddrBase + 2).getReg() != 0 ||
327       Inst.getOperand(AddrBase + 4).getReg() != 0 ||
328       Inst.getOperand(AddrBase + 1).getImm() != 1))
329    return;
330
331  // If so, rewrite the instruction.
332  MCOperand Saved = Inst.getOperand(AddrOp);
333  Inst = MCInst();
334  Inst.setOpcode(Opcode);
335  Inst.addOperand(Saved);
336}
337
338void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
339  OutMI.setOpcode(MI->getOpcode());
340
341  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
342    const MachineOperand &MO = MI->getOperand(i);
343
344    MCOperand MCOp;
345    switch (MO.getType()) {
346    default:
347      MI->dump();
348      llvm_unreachable("unknown operand type");
349    case MachineOperand::MO_Register:
350      // Ignore all implicit register operands.
351      if (MO.isImplicit()) continue;
352      MCOp = MCOperand::CreateReg(MO.getReg());
353      break;
354    case MachineOperand::MO_Immediate:
355      MCOp = MCOperand::CreateImm(MO.getImm());
356      break;
357    case MachineOperand::MO_MachineBasicBlock:
358    case MachineOperand::MO_GlobalAddress:
359    case MachineOperand::MO_ExternalSymbol:
360      MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
361      break;
362    case MachineOperand::MO_JumpTableIndex:
363      MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
364      break;
365    case MachineOperand::MO_ConstantPoolIndex:
366      MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
367      break;
368    case MachineOperand::MO_BlockAddress:
369      MCOp = LowerSymbolOperand(MO,
370                     AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
371      break;
372    case MachineOperand::MO_RegisterMask:
373      // Ignore call clobbers.
374      continue;
375    }
376
377    OutMI.addOperand(MCOp);
378  }
379
380  // Handle a few special cases to eliminate operand modifiers.
381ReSimplify:
382  switch (OutMI.getOpcode()) {
383  case X86::LEA64_32r:
384  case X86::LEA64r:
385  case X86::LEA16r:
386  case X86::LEA32r:
387    // LEA should have a segment register, but it must be empty.
388    assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
389           "Unexpected # of LEA operands");
390    assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
391           "LEA has segment specified!");
392    break;
393  case X86::MOV32r0:      LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
394
395  case X86::MOV32ri64:
396    OutMI.setOpcode(X86::MOV32ri);
397    break;
398
399  // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
400  // if one of the registers is extended, but other isn't.
401  case X86::VMOVAPDrr:
402  case X86::VMOVAPDYrr:
403  case X86::VMOVAPSrr:
404  case X86::VMOVAPSYrr:
405  case X86::VMOVDQArr:
406  case X86::VMOVDQAYrr:
407  case X86::VMOVDQUrr:
408  case X86::VMOVDQUYrr:
409  case X86::VMOVUPDrr:
410  case X86::VMOVUPDYrr:
411  case X86::VMOVUPSrr:
412  case X86::VMOVUPSYrr: {
413    if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
414        X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
415      unsigned NewOpc;
416      switch (OutMI.getOpcode()) {
417      default: llvm_unreachable("Invalid opcode");
418      case X86::VMOVAPDrr:  NewOpc = X86::VMOVAPDrr_REV;  break;
419      case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
420      case X86::VMOVAPSrr:  NewOpc = X86::VMOVAPSrr_REV;  break;
421      case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
422      case X86::VMOVDQArr:  NewOpc = X86::VMOVDQArr_REV;  break;
423      case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
424      case X86::VMOVDQUrr:  NewOpc = X86::VMOVDQUrr_REV;  break;
425      case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
426      case X86::VMOVUPDrr:  NewOpc = X86::VMOVUPDrr_REV;  break;
427      case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
428      case X86::VMOVUPSrr:  NewOpc = X86::VMOVUPSrr_REV;  break;
429      case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
430      }
431      OutMI.setOpcode(NewOpc);
432    }
433    break;
434  }
435  case X86::VMOVSDrr:
436  case X86::VMOVSSrr: {
437    if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
438        X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
439      unsigned NewOpc;
440      switch (OutMI.getOpcode()) {
441      default: llvm_unreachable("Invalid opcode");
442      case X86::VMOVSDrr:   NewOpc = X86::VMOVSDrr_REV;   break;
443      case X86::VMOVSSrr:   NewOpc = X86::VMOVSSrr_REV;   break;
444      }
445      OutMI.setOpcode(NewOpc);
446    }
447    break;
448  }
449
450  // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
451  // inputs modeled as normal uses instead of implicit uses.  As such, truncate
452  // off all but the first operand (the callee).  FIXME: Change isel.
453  case X86::TAILJMPr64:
454  case X86::CALL64r:
455  case X86::CALL64pcrel32: {
456    unsigned Opcode = OutMI.getOpcode();
457    MCOperand Saved = OutMI.getOperand(0);
458    OutMI = MCInst();
459    OutMI.setOpcode(Opcode);
460    OutMI.addOperand(Saved);
461    break;
462  }
463
464  case X86::EH_RETURN:
465  case X86::EH_RETURN64: {
466    OutMI = MCInst();
467    OutMI.setOpcode(X86::RET);
468    break;
469  }
470
471  // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
472  case X86::TAILJMPr:
473  case X86::TAILJMPd:
474  case X86::TAILJMPd64: {
475    unsigned Opcode;
476    switch (OutMI.getOpcode()) {
477    default: llvm_unreachable("Invalid opcode");
478    case X86::TAILJMPr: Opcode = X86::JMP32r; break;
479    case X86::TAILJMPd:
480    case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
481    }
482
483    MCOperand Saved = OutMI.getOperand(0);
484    OutMI = MCInst();
485    OutMI.setOpcode(Opcode);
486    OutMI.addOperand(Saved);
487    break;
488  }
489
490  // These are pseudo-ops for OR to help with the OR->ADD transformation.  We do
491  // this with an ugly goto in case the resultant OR uses EAX and needs the
492  // short form.
493  case X86::ADD16rr_DB:   OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
494  case X86::ADD32rr_DB:   OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
495  case X86::ADD64rr_DB:   OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
496  case X86::ADD16ri_DB:   OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
497  case X86::ADD32ri_DB:   OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
498  case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
499  case X86::ADD16ri8_DB:  OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
500  case X86::ADD32ri8_DB:  OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
501  case X86::ADD64ri8_DB:  OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
502
503  // The assembler backend wants to see branches in their small form and relax
504  // them to their large form.  The JIT can only handle the large form because
505  // it does not do relaxation.  For now, translate the large form to the
506  // small one here.
507  case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
508  case X86::JO_4:  OutMI.setOpcode(X86::JO_1); break;
509  case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
510  case X86::JB_4:  OutMI.setOpcode(X86::JB_1); break;
511  case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
512  case X86::JE_4:  OutMI.setOpcode(X86::JE_1); break;
513  case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
514  case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
515  case X86::JA_4:  OutMI.setOpcode(X86::JA_1); break;
516  case X86::JS_4:  OutMI.setOpcode(X86::JS_1); break;
517  case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
518  case X86::JP_4:  OutMI.setOpcode(X86::JP_1); break;
519  case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
520  case X86::JL_4:  OutMI.setOpcode(X86::JL_1); break;
521  case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
522  case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
523  case X86::JG_4:  OutMI.setOpcode(X86::JG_1); break;
524
525  // Atomic load and store require a separate pseudo-inst because Acquire
526  // implies mayStore and Release implies mayLoad; fix these to regular MOV
527  // instructions here
528  case X86::ACQUIRE_MOV8rm:  OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
529  case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
530  case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
531  case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
532  case X86::RELEASE_MOV8mr:  OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
533  case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
534  case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
535  case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
536
537  // We don't currently select the correct instruction form for instructions
538  // which have a short %eax, etc. form. Handle this by custom lowering, for
539  // now.
540  //
541  // Note, we are currently not handling the following instructions:
542  // MOV64ao8, MOV64o8a
543  // XCHG16ar, XCHG32ar, XCHG64ar
544  case X86::MOV8mr_NOREX:
545  case X86::MOV8mr:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
546  case X86::MOV8rm_NOREX:
547  case X86::MOV8rm:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
548  case X86::MOV16mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
549  case X86::MOV16rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
550  case X86::MOV32mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
551  case X86::MOV32rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
552
553  case X86::ADC8ri:     SimplifyShortImmForm(OutMI, X86::ADC8i8);    break;
554  case X86::ADC16ri:    SimplifyShortImmForm(OutMI, X86::ADC16i16);  break;
555  case X86::ADC32ri:    SimplifyShortImmForm(OutMI, X86::ADC32i32);  break;
556  case X86::ADC64ri32:  SimplifyShortImmForm(OutMI, X86::ADC64i32);  break;
557  case X86::ADD8ri:     SimplifyShortImmForm(OutMI, X86::ADD8i8);    break;
558  case X86::ADD16ri:    SimplifyShortImmForm(OutMI, X86::ADD16i16);  break;
559  case X86::ADD32ri:    SimplifyShortImmForm(OutMI, X86::ADD32i32);  break;
560  case X86::ADD64ri32:  SimplifyShortImmForm(OutMI, X86::ADD64i32);  break;
561  case X86::AND8ri:     SimplifyShortImmForm(OutMI, X86::AND8i8);    break;
562  case X86::AND16ri:    SimplifyShortImmForm(OutMI, X86::AND16i16);  break;
563  case X86::AND32ri:    SimplifyShortImmForm(OutMI, X86::AND32i32);  break;
564  case X86::AND64ri32:  SimplifyShortImmForm(OutMI, X86::AND64i32);  break;
565  case X86::CMP8ri:     SimplifyShortImmForm(OutMI, X86::CMP8i8);    break;
566  case X86::CMP16ri:    SimplifyShortImmForm(OutMI, X86::CMP16i16);  break;
567  case X86::CMP32ri:    SimplifyShortImmForm(OutMI, X86::CMP32i32);  break;
568  case X86::CMP64ri32:  SimplifyShortImmForm(OutMI, X86::CMP64i32);  break;
569  case X86::OR8ri:      SimplifyShortImmForm(OutMI, X86::OR8i8);     break;
570  case X86::OR16ri:     SimplifyShortImmForm(OutMI, X86::OR16i16);   break;
571  case X86::OR32ri:     SimplifyShortImmForm(OutMI, X86::OR32i32);   break;
572  case X86::OR64ri32:   SimplifyShortImmForm(OutMI, X86::OR64i32);   break;
573  case X86::SBB8ri:     SimplifyShortImmForm(OutMI, X86::SBB8i8);    break;
574  case X86::SBB16ri:    SimplifyShortImmForm(OutMI, X86::SBB16i16);  break;
575  case X86::SBB32ri:    SimplifyShortImmForm(OutMI, X86::SBB32i32);  break;
576  case X86::SBB64ri32:  SimplifyShortImmForm(OutMI, X86::SBB64i32);  break;
577  case X86::SUB8ri:     SimplifyShortImmForm(OutMI, X86::SUB8i8);    break;
578  case X86::SUB16ri:    SimplifyShortImmForm(OutMI, X86::SUB16i16);  break;
579  case X86::SUB32ri:    SimplifyShortImmForm(OutMI, X86::SUB32i32);  break;
580  case X86::SUB64ri32:  SimplifyShortImmForm(OutMI, X86::SUB64i32);  break;
581  case X86::TEST8ri:    SimplifyShortImmForm(OutMI, X86::TEST8i8);   break;
582  case X86::TEST16ri:   SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
583  case X86::TEST32ri:   SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
584  case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
585  case X86::XOR8ri:     SimplifyShortImmForm(OutMI, X86::XOR8i8);    break;
586  case X86::XOR16ri:    SimplifyShortImmForm(OutMI, X86::XOR16i16);  break;
587  case X86::XOR32ri:    SimplifyShortImmForm(OutMI, X86::XOR32i32);  break;
588  case X86::XOR64ri32:  SimplifyShortImmForm(OutMI, X86::XOR64i32);  break;
589
590  // Try to shrink some forms of movsx.
591  case X86::MOVSX16rr8:
592  case X86::MOVSX32rr16:
593  case X86::MOVSX64rr32:
594    SimplifyMOVSX(OutMI);
595    break;
596  }
597}
598
599static void LowerTlsAddr(MCStreamer &OutStreamer,
600                         X86MCInstLower &MCInstLowering,
601                         const MachineInstr &MI) {
602
603  bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
604                  MI.getOpcode() == X86::TLS_base_addr64;
605
606  bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
607
608  MCContext &context = OutStreamer.getContext();
609
610  if (needsPadding)
611    OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
612
613  MCSymbolRefExpr::VariantKind SRVK;
614  switch (MI.getOpcode()) {
615    case X86::TLS_addr32:
616    case X86::TLS_addr64:
617      SRVK = MCSymbolRefExpr::VK_TLSGD;
618      break;
619    case X86::TLS_base_addr32:
620      SRVK = MCSymbolRefExpr::VK_TLSLDM;
621      break;
622    case X86::TLS_base_addr64:
623      SRVK = MCSymbolRefExpr::VK_TLSLD;
624      break;
625    default:
626      llvm_unreachable("unexpected opcode");
627  }
628
629  MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
630  const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context);
631
632  MCInst LEA;
633  if (is64Bits) {
634    LEA.setOpcode(X86::LEA64r);
635    LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
636    LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
637    LEA.addOperand(MCOperand::CreateImm(1));        // scale
638    LEA.addOperand(MCOperand::CreateReg(0));        // index
639    LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
640    LEA.addOperand(MCOperand::CreateReg(0));        // seg
641  } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
642    LEA.setOpcode(X86::LEA32r);
643    LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
644    LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
645    LEA.addOperand(MCOperand::CreateImm(1));        // scale
646    LEA.addOperand(MCOperand::CreateReg(0));        // index
647    LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
648    LEA.addOperand(MCOperand::CreateReg(0));        // seg
649  } else {
650    LEA.setOpcode(X86::LEA32r);
651    LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
652    LEA.addOperand(MCOperand::CreateReg(0));        // base
653    LEA.addOperand(MCOperand::CreateImm(1));        // scale
654    LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
655    LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
656    LEA.addOperand(MCOperand::CreateReg(0));        // seg
657  }
658  OutStreamer.EmitInstruction(LEA);
659
660  if (needsPadding) {
661    OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
662    OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
663    OutStreamer.EmitInstruction(MCInstBuilder(X86::REX64_PREFIX));
664  }
665
666  StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
667  MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name);
668  const MCSymbolRefExpr *tlsRef =
669    MCSymbolRefExpr::Create(tlsGetAddr,
670                            MCSymbolRefExpr::VK_PLT,
671                            context);
672
673  OutStreamer.EmitInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
674                                                     : X86::CALLpcrel32)
675    .addExpr(tlsRef));
676}
677
678static std::pair<StackMaps::Location, MachineInstr::const_mop_iterator>
679parseMemoryOperand(StackMaps::Location::LocationType LocTy,
680                   MachineInstr::const_mop_iterator MOI,
681                   MachineInstr::const_mop_iterator MOE) {
682
683  typedef StackMaps::Location Location;
684
685  assert(std::distance(MOI, MOE) >= 5 && "Too few operands to encode mem op.");
686
687  const MachineOperand &Base = *MOI;
688  const MachineOperand &Scale = *(++MOI);
689  const MachineOperand &Index = *(++MOI);
690  const MachineOperand &Disp = *(++MOI);
691  const MachineOperand &ZeroReg = *(++MOI);
692
693  // Sanity check for supported operand format.
694  assert(Base.isReg() &&
695         Scale.isImm() && Scale.getImm() == 1 &&
696         Index.isReg() && Index.getReg() == 0 &&
697         Disp.isImm() && ZeroReg.isReg() && (ZeroReg.getReg() == 0) &&
698         "Unsupported x86 memory operand sequence.");
699  (void)Scale;
700  (void)Index;
701  (void)ZeroReg;
702
703  return std::make_pair(
704           Location(LocTy, Base.getReg(), Disp.getImm()), ++MOI);
705}
706
707std::pair<StackMaps::Location, MachineInstr::const_mop_iterator>
708X86AsmPrinter::stackmapOperandParser(MachineInstr::const_mop_iterator MOI,
709                                     MachineInstr::const_mop_iterator MOE) {
710
711  typedef StackMaps::Location Location;
712
713  const MachineOperand &MOP = *MOI;
714  assert(!MOP.isRegMask() && (!MOP.isReg() || !MOP.isImplicit()) &&
715         "Register mask and implicit operands should not be processed.");
716
717  if (MOP.isImm()) {
718    switch (MOP.getImm()) {
719    default: llvm_unreachable("Unrecognized operand type.");
720    case StackMaps::DirectMemRefOp:
721      return parseMemoryOperand(StackMaps::Location::Direct,
722                                llvm::next(MOI), MOE);
723    case StackMaps::IndirectMemRefOp:
724      return parseMemoryOperand(StackMaps::Location::Indirect,
725                                llvm::next(MOI), MOE);
726    case StackMaps::ConstantOp: {
727      ++MOI;
728      assert(MOI->isImm() && "Expected constant operand.");
729      int64_t Imm = MOI->getImm();
730      return std::make_pair(Location(Location::Constant, 0, Imm), ++MOI);
731    }
732    }
733  }
734
735  // Otherwise this is a reg operand.
736  assert(MOP.isReg() && "Expected register operand here.");
737  assert(TargetRegisterInfo::isPhysicalRegister(MOP.getReg()) &&
738         "Virtreg operands should have been rewritten before now.");
739  return std::make_pair(Location(Location::Register, MOP.getReg(), 0), ++MOI);
740}
741
742static MachineInstr::const_mop_iterator
743getStackMapEndMOP(MachineInstr::const_mop_iterator MOI,
744                  MachineInstr::const_mop_iterator MOE) {
745  for (; MOI != MOE; ++MOI)
746    if (MOI->isRegMask() || (MOI->isReg() && MOI->isImplicit()))
747      break;
748
749  return MOI;
750}
751
752static void LowerSTACKMAP(MCStreamer &OutStreamer,
753                          X86MCInstLower &MCInstLowering,
754                          StackMaps &SM,
755                          const MachineInstr &MI)
756{
757  int64_t ID = MI.getOperand(0).getImm();
758  unsigned NumNOPBytes = MI.getOperand(1).getImm();
759
760  assert((int32_t)ID == ID && "Stack maps hold 32-bit IDs");
761  SM.recordStackMap(MI, ID, llvm::next(MI.operands_begin(), 2),
762                    getStackMapEndMOP(MI.operands_begin(), MI.operands_end()));
763  // Emit padding.
764  for (unsigned i = 0; i < NumNOPBytes; ++i)
765    OutStreamer.EmitInstruction(MCInstBuilder(X86::NOOP));
766}
767
768// Lower a patchpoint of the form:
769// [<def>], <id>, <numBytes>, <target>, <numArgs>
770static void LowerPATCHPOINT(MCStreamer &OutStreamer,
771                            X86MCInstLower &MCInstLowering,
772                            StackMaps &SM,
773                            const MachineInstr &MI) {
774  bool hasDef = MI.getOperand(0).isReg() && MI.getOperand(0).isDef() &&
775                !MI.getOperand(0).isImplicit();
776  unsigned StartIdx = hasDef ? 1 : 0;
777#ifndef NDEBUG
778  {
779  unsigned StartIdx2 = 0, e = MI.getNumOperands();
780  while (StartIdx2 < e && MI.getOperand(StartIdx2).isReg() &&
781         MI.getOperand(StartIdx2).isDef() &&
782         !MI.getOperand(StartIdx2).isImplicit())
783    ++StartIdx2;
784
785  assert(StartIdx == StartIdx2 &&
786         "Unexpected additonal definition in Patchpoint intrinsic.");
787  }
788#endif
789
790  // Find the first scratch register (implicit def and early clobber)
791  unsigned ScratchIdx = StartIdx, e = MI.getNumOperands();
792  while (ScratchIdx < e &&
793         !(MI.getOperand(ScratchIdx).isReg() &&
794           MI.getOperand(ScratchIdx).isDef() &&
795           MI.getOperand(ScratchIdx).isImplicit() &&
796           MI.getOperand(ScratchIdx).isEarlyClobber()))
797    ++ScratchIdx;
798
799  assert(ScratchIdx != e && "No scratch register available");
800
801  int64_t ID = MI.getOperand(StartIdx).getImm();
802  assert((int32_t)ID == ID && "Stack maps hold 32-bit IDs");
803
804  // Get the number of arguments participating in the call. This number was
805  // adjusted during call lowering by subtracting stack args.
806  bool isAnyRegCC = MI.getOperand(StartIdx + 4).getImm() == CallingConv::AnyReg;
807  assert(((hasDef && isAnyRegCC) || !hasDef) &&
808         "Only Patchpoints with AnyReg calling convention may have a result");
809  int64_t StackMapIdx = isAnyRegCC ? StartIdx + 5 :
810    StartIdx + 5 + MI.getOperand(StartIdx + 3).getImm();
811  assert(StackMapIdx <= MI.getNumOperands() &&
812         "Patchpoint intrinsic dropped arguments.");
813
814  SM.recordStackMap(MI, ID, llvm::next(MI.operands_begin(), StackMapIdx),
815                    getStackMapEndMOP(MI.operands_begin(), MI.operands_end()),
816                    isAnyRegCC && hasDef);
817
818  unsigned EncodedBytes = 0;
819  int64_t CallTarget = MI.getOperand(StartIdx + 2).getImm();
820  if (CallTarget) {
821    // Emit MOV to materialize the target address and the CALL to target.
822    // This is encoded with 12-13 bytes, depending on which register is used.
823    // We conservatively assume that it is 12 bytes and emit in worst case one
824    // extra NOP byte.
825    EncodedBytes = 12;
826    OutStreamer.EmitInstruction(MCInstBuilder(X86::MOV64ri)
827                                .addReg(MI.getOperand(ScratchIdx).getReg())
828                                .addImm(CallTarget));
829    OutStreamer.EmitInstruction(MCInstBuilder(X86::CALL64r)
830                                .addReg(MI.getOperand(ScratchIdx).getReg()));
831  }
832  // Emit padding.
833  unsigned NumNOPBytes = MI.getOperand(StartIdx + 1).getImm();
834  assert(NumNOPBytes >= EncodedBytes &&
835         "Patchpoint can't request size less than the length of a call.");
836
837  for (unsigned i = EncodedBytes; i < NumNOPBytes; ++i)
838    OutStreamer.EmitInstruction(MCInstBuilder(X86::NOOP));
839}
840
841void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
842  X86MCInstLower MCInstLowering(*MF, *this);
843  switch (MI->getOpcode()) {
844  case TargetOpcode::DBG_VALUE:
845    llvm_unreachable("Should be handled target independently");
846
847  // Emit nothing here but a comment if we can.
848  case X86::Int_MemBarrier:
849    if (OutStreamer.hasRawTextSupport())
850      OutStreamer.EmitRawText(StringRef("\t#MEMBARRIER"));
851    return;
852
853
854  case X86::EH_RETURN:
855  case X86::EH_RETURN64: {
856    // Lower these as normal, but add some comments.
857    unsigned Reg = MI->getOperand(0).getReg();
858    OutStreamer.AddComment(StringRef("eh_return, addr: %") +
859                           X86ATTInstPrinter::getRegisterName(Reg));
860    break;
861  }
862  case X86::TAILJMPr:
863  case X86::TAILJMPd:
864  case X86::TAILJMPd64:
865    // Lower these as normal, but add some comments.
866    OutStreamer.AddComment("TAILCALL");
867    break;
868
869  case X86::TLS_addr32:
870  case X86::TLS_addr64:
871  case X86::TLS_base_addr32:
872  case X86::TLS_base_addr64:
873    return LowerTlsAddr(OutStreamer, MCInstLowering, *MI);
874
875  case X86::MOVPC32r: {
876    // This is a pseudo op for a two instruction sequence with a label, which
877    // looks like:
878    //     call "L1$pb"
879    // "L1$pb":
880    //     popl %esi
881
882    // Emit the call.
883    MCSymbol *PICBase = MF->getPICBaseSymbol();
884    // FIXME: We would like an efficient form for this, so we don't have to do a
885    // lot of extra uniquing.
886    OutStreamer.EmitInstruction(MCInstBuilder(X86::CALLpcrel32)
887      .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
888
889    // Emit the label.
890    OutStreamer.EmitLabel(PICBase);
891
892    // popl $reg
893    OutStreamer.EmitInstruction(MCInstBuilder(X86::POP32r)
894      .addReg(MI->getOperand(0).getReg()));
895    return;
896  }
897
898  case X86::ADD32ri: {
899    // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
900    if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
901      break;
902
903    // Okay, we have something like:
904    //  EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
905
906    // For this, we want to print something like:
907    //   MYGLOBAL + (. - PICBASE)
908    // However, we can't generate a ".", so just emit a new label here and refer
909    // to it.
910    MCSymbol *DotSym = OutContext.CreateTempSymbol();
911    OutStreamer.EmitLabel(DotSym);
912
913    // Now that we have emitted the label, lower the complex operand expression.
914    MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
915
916    const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
917    const MCExpr *PICBase =
918      MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext);
919    DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
920
921    DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
922                                      DotExpr, OutContext);
923
924    OutStreamer.EmitInstruction(MCInstBuilder(X86::ADD32ri)
925      .addReg(MI->getOperand(0).getReg())
926      .addReg(MI->getOperand(1).getReg())
927      .addExpr(DotExpr));
928    return;
929  }
930
931  case TargetOpcode::STACKMAP:
932    return LowerSTACKMAP(OutStreamer, MCInstLowering, SM, *MI);
933
934  case TargetOpcode::PATCHPOINT:
935    return LowerPATCHPOINT(OutStreamer, MCInstLowering, SM, *MI);
936
937  case X86::MORESTACK_RET:
938    OutStreamer.EmitInstruction(MCInstBuilder(X86::RET));
939    return;
940
941  case X86::MORESTACK_RET_RESTORE_R10:
942    // Return, then restore R10.
943    OutStreamer.EmitInstruction(MCInstBuilder(X86::RET));
944    OutStreamer.EmitInstruction(MCInstBuilder(X86::MOV64rr)
945      .addReg(X86::R10)
946      .addReg(X86::RAX));
947    return;
948  }
949
950  MCInst TmpInst;
951  MCInstLowering.Lower(MI, TmpInst);
952  OutStreamer.EmitInstruction(TmpInst);
953}
954