X86RegisterInfo.h revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- X86RegisterInfo.h - X86 Register Information Impl -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef X86REGISTERINFO_H
15#define X86REGISTERINFO_H
16
17#include "llvm/Target/TargetRegisterInfo.h"
18
19#define GET_REGINFO_HEADER
20#include "X86GenRegisterInfo.inc"
21
22namespace llvm {
23  class Type;
24  class TargetInstrInfo;
25  class X86TargetMachine;
26
27class X86RegisterInfo final : public X86GenRegisterInfo {
28public:
29  X86TargetMachine &TM;
30
31private:
32  /// Is64Bit - Is the target 64-bits.
33  ///
34  bool Is64Bit;
35
36  /// IsWin64 - Is the target on of win64 flavours
37  ///
38  bool IsWin64;
39
40  /// SlotSize - Stack slot size in bytes.
41  ///
42  unsigned SlotSize;
43
44  /// StackPtr - X86 physical register used as stack ptr.
45  ///
46  unsigned StackPtr;
47
48  /// FramePtr - X86 physical register used as frame ptr.
49  ///
50  unsigned FramePtr;
51
52  /// BasePtr - X86 physical register used as a base ptr in complex stack
53  /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
54  /// variable size stack objects.
55  unsigned BasePtr;
56
57public:
58  X86RegisterInfo(X86TargetMachine &tm);
59
60  // FIXME: This should be tablegen'd like getDwarfRegNum is
61  int getSEHRegNum(unsigned i) const;
62
63  /// getCompactUnwindRegNum - This function maps the register to the number for
64  /// compact unwind encoding. Return -1 if the register isn't valid.
65  int getCompactUnwindRegNum(unsigned RegNum, bool isEH) const override;
66
67  /// Code Generation virtual methods...
68  ///
69  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
70
71  /// getMatchingSuperRegClass - Return a subclass of the specified register
72  /// class A so that each register in it has a sub-register of the
73  /// specified sub-register index which is in the specified register class B.
74  const TargetRegisterClass *
75  getMatchingSuperRegClass(const TargetRegisterClass *A,
76                           const TargetRegisterClass *B,
77                           unsigned Idx) const override;
78
79  const TargetRegisterClass *
80  getSubClassWithSubReg(const TargetRegisterClass *RC,
81                        unsigned Idx) const override;
82
83  const TargetRegisterClass*
84  getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
85
86  /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
87  /// values.
88  const TargetRegisterClass *
89  getPointerRegClass(const MachineFunction &MF,
90                     unsigned Kind = 0) const override;
91
92  /// getCrossCopyRegClass - Returns a legal register class to copy a register
93  /// in the specified class to or from. Returns NULL if it is possible to copy
94  /// between a two registers of the specified class.
95  const TargetRegisterClass *
96  getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
97
98  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
99                               MachineFunction &MF) const override;
100
101  /// getCalleeSavedRegs - Return a null-terminated list of all of the
102  /// callee-save registers on this target.
103  const MCPhysReg *
104  getCalleeSavedRegs(const MachineFunction* MF) const override;
105  const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
106  const uint32_t *getNoPreservedMask() const;
107
108  /// getReservedRegs - Returns a bitset indexed by physical register number
109  /// indicating if a register is a special register that has particular uses and
110  /// should be considered unavailable at all times, e.g. SP, RA. This is used by
111  /// register scavenger to determine what registers are free.
112  BitVector getReservedRegs(const MachineFunction &MF) const override;
113
114  bool hasBasePointer(const MachineFunction &MF) const;
115
116  bool canRealignStack(const MachineFunction &MF) const;
117
118  bool needsStackRealignment(const MachineFunction &MF) const override;
119
120  bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
121                            int &FrameIdx) const override;
122
123  void eliminateFrameIndex(MachineBasicBlock::iterator MI,
124                           int SPAdj, unsigned FIOperandNum,
125                           RegScavenger *RS = nullptr) const override;
126
127  // Debug information queries.
128  unsigned getFrameRegister(const MachineFunction &MF) const override;
129  unsigned getStackRegister() const { return StackPtr; }
130  unsigned getBaseRegister() const { return BasePtr; }
131  // FIXME: Move to FrameInfok
132  unsigned getSlotSize() const { return SlotSize; }
133};
134
135// getX86SubSuperRegister - X86 utility function. It returns the sub or super
136// register of a specific X86 register.
137// e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX
138unsigned getX86SubSuperRegister(unsigned, MVT::SimpleValueType, bool High=false);
139
140//get512BitRegister - X86 utility - returns 512-bit super register
141unsigned get512BitSuperRegister(unsigned Reg);
142
143} // End llvm namespace
144
145#endif
146