X86RegisterInfo.h revision dff4b4c5a7cc894d3b4b6c6e779ea8f47fa50630
1//===- X86RegisterInfo.h - X86 Register Information Impl --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86REGISTERINFO_H 15#define X86REGISTERINFO_H 16 17#include "llvm/Target/TargetRegisterInfo.h" 18#include "X86GenRegisterInfo.h.inc" 19 20namespace llvm { 21 class Type; 22 class TargetInstrInfo; 23 class X86TargetMachine; 24 25/// N86 namespace - Native X86 register numbers 26/// 27namespace N86 { 28 enum { 29 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 30 }; 31} 32 33namespace X86 { 34 /// SubregIndex - The index of various sized subregister classes. Note that 35 /// these indices must be kept in sync with the class indices in the 36 /// X86RegisterInfo.td file. 37 enum SubregIndex { 38 SUBREG_8BIT = 1, SUBREG_8BIT_HI = 2, SUBREG_16BIT = 3, SUBREG_32BIT = 4, 39 SUBREG_SS = 1, SUBREG_SD = 2, SUBREG_XMM = 3 40 }; 41} 42 43/// DWARFFlavour - Flavour of dwarf regnumbers 44/// 45namespace DWARFFlavour { 46 enum { 47 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2 48 }; 49} 50 51class X86RegisterInfo : public X86GenRegisterInfo { 52public: 53 X86TargetMachine &TM; 54 const TargetInstrInfo &TII; 55 56private: 57 /// Is64Bit - Is the target 64-bits. 58 /// 59 bool Is64Bit; 60 61 /// IsWin64 - Is the target on of win64 flavours 62 /// 63 bool IsWin64; 64 65 /// SlotSize - Stack slot size in bytes. 66 /// 67 unsigned SlotSize; 68 69 /// StackAlign - Default stack alignment. 70 /// 71 unsigned StackAlign; 72 73 /// StackPtr - X86 physical register used as stack ptr. 74 /// 75 unsigned StackPtr; 76 77 /// FramePtr - X86 physical register used as frame ptr. 78 /// 79 unsigned FramePtr; 80 81public: 82 X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii); 83 84 /// getX86RegNum - Returns the native X86 register number for the given LLVM 85 /// register identifier. 86 static unsigned getX86RegNum(unsigned RegNo); 87 88 unsigned getStackAlignment() const { return StackAlign; } 89 90 /// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum 91 /// (created by TableGen) for target dependencies. 92 int getDwarfRegNum(unsigned RegNum, bool isEH) const; 93 94 /// Code Generation virtual methods... 95 /// 96 97 /// getMatchingSuperRegClass - Return a subclass of the specified register 98 /// class A so that each register in it has a sub-register of the 99 /// specified sub-register index which is in the specified register class B. 100 virtual const TargetRegisterClass * 101 getMatchingSuperRegClass(const TargetRegisterClass *A, 102 const TargetRegisterClass *B, unsigned Idx) const; 103 104 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 105 /// values. 106 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const; 107 108 /// getCrossCopyRegClass - Returns a legal register class to copy a register 109 /// in the specified class to or from. Returns NULL if it is possible to copy 110 /// between a two registers of the specified class. 111 const TargetRegisterClass * 112 getCrossCopyRegClass(const TargetRegisterClass *RC) const; 113 114 /// getCalleeSavedRegs - Return a null-terminated list of all of the 115 /// callee-save registers on this target. 116 const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const; 117 118 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred 119 /// register classes to spill each callee-saved register with. The order and 120 /// length of this list match the getCalleeSavedRegs() list. 121 const TargetRegisterClass* const* 122 getCalleeSavedRegClasses(const MachineFunction *MF = 0) const; 123 124 /// getReservedRegs - Returns a bitset indexed by physical register number 125 /// indicating if a register is a special register that has particular uses and 126 /// should be considered unavailable at all times, e.g. SP, RA. This is used by 127 /// register scavenger to determine what registers are free. 128 BitVector getReservedRegs(const MachineFunction &MF) const; 129 130 bool hasFP(const MachineFunction &MF) const; 131 132 bool canRealignStack(const MachineFunction &MF) const; 133 134 bool needsStackRealignment(const MachineFunction &MF) const; 135 136 bool hasReservedCallFrame(MachineFunction &MF) const; 137 138 bool hasReservedSpillSlot(MachineFunction &MF, unsigned Reg, 139 int &FrameIdx) const; 140 141 void eliminateCallFramePseudoInstr(MachineFunction &MF, 142 MachineBasicBlock &MBB, 143 MachineBasicBlock::iterator MI) const; 144 145 unsigned eliminateFrameIndex(MachineBasicBlock::iterator MI, 146 int SPAdj, FrameIndexValue *Value = NULL, 147 RegScavenger *RS = NULL) const; 148 149 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 150 RegScavenger *RS = NULL) const; 151 152 void emitCalleeSavedFrameMoves(MachineFunction &MF, unsigned LabelId, 153 unsigned FramePtr) const; 154 void emitPrologue(MachineFunction &MF) const; 155 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; 156 157 // Debug information queries. 158 unsigned getRARegister() const; 159 unsigned getFrameRegister(const MachineFunction &MF) const; 160 int getFrameIndexOffset(const MachineFunction &MF, int FI) const; 161 void getInitialFrameState(std::vector<MachineMove> &Moves) const; 162 163 // Exception handling queries. 164 unsigned getEHExceptionRegister() const; 165 unsigned getEHHandlerRegister() const; 166}; 167 168// getX86SubSuperRegister - X86 utility function. It returns the sub or super 169// register of a specific X86 register. 170// e.g. getX86SubSuperRegister(X86::EAX, EVT::i16) return X86:AX 171unsigned getX86SubSuperRegister(unsigned, EVT, bool High=false); 172 173} // End llvm namespace 174 175#endif 176