X86SchedHaswell.td revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the machine model for Haswell to support instruction 11// scheduling and other instruction cost heuristics. 12// 13//===----------------------------------------------------------------------===// 14 15def HaswellModel : SchedMachineModel { 16 // All x86 instructions are modeled as a single micro-op, and HW can decode 4 17 // instructions per cycle. 18 let IssueWidth = 4; 19 let MicroOpBufferSize = 192; // Based on the reorder buffer. 20 let LoadLatency = 4; 21 let MispredictPenalty = 16; 22 23 // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow 24 // the scheduler to assign a default model to unrecognized opcodes. 25 let CompleteModel = 0; 26} 27 28let SchedModel = HaswellModel in { 29 30// Haswell can issue micro-ops to 8 different ports in one cycle. 31 32// Ports 0, 1, 5, and 6 handle all computation. 33// Port 4 gets the data half of stores. Store data can be available later than 34// the store address, but since we don't model the latency of stores, we can 35// ignore that. 36// Ports 2 and 3 are identical. They handle loads and the address half of 37// stores. Port 7 can handle address calculations. 38def HWPort0 : ProcResource<1>; 39def HWPort1 : ProcResource<1>; 40def HWPort2 : ProcResource<1>; 41def HWPort3 : ProcResource<1>; 42def HWPort4 : ProcResource<1>; 43def HWPort5 : ProcResource<1>; 44def HWPort6 : ProcResource<1>; 45def HWPort7 : ProcResource<1>; 46 47// Many micro-ops are capable of issuing on multiple ports. 48def HWPort23 : ProcResGroup<[HWPort2, HWPort3]>; 49def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>; 50def HWPort05 : ProcResGroup<[HWPort0, HWPort5]>; 51def HWPort06 : ProcResGroup<[HWPort0, HWPort6]>; 52def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>; 53def HWPort16 : ProcResGroup<[HWPort1, HWPort6]>; 54def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>; 55def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>; 56 57// 60 Entry Unified Scheduler 58def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4, 59 HWPort5, HWPort6, HWPort7]> { 60 let BufferSize=60; 61} 62 63// Integer division issued on port 0. 64def HWDivider : ProcResource<1>; 65 66// Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4 67// cycles after the memory operand. 68def : ReadAdvance<ReadAfterLd, 4>; 69 70// Many SchedWrites are defined in pairs with and without a folded load. 71// Instructions with folded loads are usually micro-fused, so they only appear 72// as two micro-ops when queued in the reservation station. 73// This multiclass defines the resource usage for variants with and without 74// folded loads. 75multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW, 76 ProcResourceKind ExePort, 77 int Lat> { 78 // Register variant is using a single cycle on ExePort. 79 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; } 80 81 // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the 82 // latency. 83 def : WriteRes<SchedRW.Folded, [HWPort23, ExePort]> { 84 let Latency = !add(Lat, 4); 85 } 86} 87 88// A folded store needs a cycle on port 4 for the store data, but it does not 89// need an extra port 2/3 cycle to recompute the address. 90def : WriteRes<WriteRMW, [HWPort4]>; 91 92// Store_addr on 237. 93// Store_data on 4. 94def : WriteRes<WriteStore, [HWPort237, HWPort4]>; 95def : WriteRes<WriteLoad, [HWPort23]> { let Latency = 4; } 96def : WriteRes<WriteMove, [HWPort0156]>; 97def : WriteRes<WriteZero, []>; 98 99defm : HWWriteResPair<WriteALU, HWPort0156, 1>; 100defm : HWWriteResPair<WriteIMul, HWPort1, 3>; 101def : WriteRes<WriteIMulH, []> { let Latency = 3; } 102defm : HWWriteResPair<WriteShift, HWPort06, 1>; 103defm : HWWriteResPair<WriteJump, HWPort06, 1>; 104 105// This is for simple LEAs with one or two input operands. 106// The complex ones can only execute on port 1, and they require two cycles on 107// the port to read all inputs. We don't model that. 108def : WriteRes<WriteLEA, [HWPort15]>; 109 110// This is quite rough, latency depends on the dividend. 111def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> { 112 let Latency = 25; 113 let ResourceCycles = [1, 10]; 114} 115def : WriteRes<WriteIDivLd, [HWPort23, HWPort0, HWDivider]> { 116 let Latency = 29; 117 let ResourceCycles = [1, 1, 10]; 118} 119 120// Scalar and vector floating point. 121defm : HWWriteResPair<WriteFAdd, HWPort1, 3>; 122defm : HWWriteResPair<WriteFMul, HWPort0, 5>; 123defm : HWWriteResPair<WriteFDiv, HWPort0, 12>; // 10-14 cycles. 124defm : HWWriteResPair<WriteFRcp, HWPort0, 5>; 125defm : HWWriteResPair<WriteFSqrt, HWPort0, 15>; 126defm : HWWriteResPair<WriteCvtF2I, HWPort1, 3>; 127defm : HWWriteResPair<WriteCvtI2F, HWPort1, 4>; 128defm : HWWriteResPair<WriteCvtF2F, HWPort1, 3>; 129defm : HWWriteResPair<WriteFShuffle, HWPort5, 1>; 130defm : HWWriteResPair<WriteFBlend, HWPort015, 1>; 131defm : HWWriteResPair<WriteFShuffle256, HWPort5, 3>; 132 133def : WriteRes<WriteFVarBlend, [HWPort5]> { 134 let Latency = 2; 135 let ResourceCycles = [2]; 136} 137def : WriteRes<WriteFVarBlendLd, [HWPort5, HWPort23]> { 138 let Latency = 6; 139 let ResourceCycles = [2, 1]; 140} 141 142// Vector integer operations. 143defm : HWWriteResPair<WriteVecShift, HWPort0, 1>; 144defm : HWWriteResPair<WriteVecLogic, HWPort015, 1>; 145defm : HWWriteResPair<WriteVecALU, HWPort15, 1>; 146defm : HWWriteResPair<WriteVecIMul, HWPort0, 5>; 147defm : HWWriteResPair<WriteShuffle, HWPort5, 1>; 148defm : HWWriteResPair<WriteBlend, HWPort15, 1>; 149defm : HWWriteResPair<WriteShuffle256, HWPort5, 3>; 150 151def : WriteRes<WriteVarBlend, [HWPort5]> { 152 let Latency = 2; 153 let ResourceCycles = [2]; 154} 155def : WriteRes<WriteVarBlendLd, [HWPort5, HWPort23]> { 156 let Latency = 6; 157 let ResourceCycles = [2, 1]; 158} 159 160def : WriteRes<WriteVarVecShift, [HWPort0, HWPort5]> { 161 let Latency = 2; 162 let ResourceCycles = [2, 1]; 163} 164def : WriteRes<WriteVarVecShiftLd, [HWPort0, HWPort5, HWPort23]> { 165 let Latency = 6; 166 let ResourceCycles = [2, 1, 1]; 167} 168 169def : WriteRes<WriteMPSAD, [HWPort0, HWPort5]> { 170 let Latency = 6; 171 let ResourceCycles = [1, 2]; 172} 173def : WriteRes<WriteMPSADLd, [HWPort23, HWPort0, HWPort5]> { 174 let Latency = 6; 175 let ResourceCycles = [1, 1, 2]; 176} 177 178// String instructions. 179// Packed Compare Implicit Length Strings, Return Mask 180def : WriteRes<WritePCmpIStrM, [HWPort0]> { 181 let Latency = 10; 182 let ResourceCycles = [3]; 183} 184def : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> { 185 let Latency = 10; 186 let ResourceCycles = [3, 1]; 187} 188 189// Packed Compare Explicit Length Strings, Return Mask 190def : WriteRes<WritePCmpEStrM, [HWPort0, HWPort16, HWPort5]> { 191 let Latency = 10; 192 let ResourceCycles = [3, 2, 4]; 193} 194def : WriteRes<WritePCmpEStrMLd, [HWPort05, HWPort16, HWPort23]> { 195 let Latency = 10; 196 let ResourceCycles = [6, 2, 1]; 197} 198 199// Packed Compare Implicit Length Strings, Return Index 200def : WriteRes<WritePCmpIStrI, [HWPort0]> { 201 let Latency = 11; 202 let ResourceCycles = [3]; 203} 204def : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> { 205 let Latency = 11; 206 let ResourceCycles = [3, 1]; 207} 208 209// Packed Compare Explicit Length Strings, Return Index 210def : WriteRes<WritePCmpEStrI, [HWPort05, HWPort16]> { 211 let Latency = 11; 212 let ResourceCycles = [6, 2]; 213} 214def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort16, HWPort5, HWPort23]> { 215 let Latency = 11; 216 let ResourceCycles = [3, 2, 2, 1]; 217} 218 219// AES Instructions. 220def : WriteRes<WriteAESDecEnc, [HWPort5]> { 221 let Latency = 7; 222 let ResourceCycles = [1]; 223} 224def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> { 225 let Latency = 7; 226 let ResourceCycles = [1, 1]; 227} 228 229def : WriteRes<WriteAESIMC, [HWPort5]> { 230 let Latency = 14; 231 let ResourceCycles = [2]; 232} 233def : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> { 234 let Latency = 14; 235 let ResourceCycles = [2, 1]; 236} 237 238def : WriteRes<WriteAESKeyGen, [HWPort0, HWPort5]> { 239 let Latency = 10; 240 let ResourceCycles = [2, 8]; 241} 242def : WriteRes<WriteAESKeyGenLd, [HWPort0, HWPort5, HWPort23]> { 243 let Latency = 10; 244 let ResourceCycles = [2, 7, 1]; 245} 246 247// Carry-less multiplication instructions. 248def : WriteRes<WriteCLMul, [HWPort0, HWPort5]> { 249 let Latency = 7; 250 let ResourceCycles = [2, 1]; 251} 252def : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> { 253 let Latency = 7; 254 let ResourceCycles = [2, 1, 1]; 255} 256 257def : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; } 258def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; } 259def : WriteRes<WriteFence, [HWPort23, HWPort4]>; 260def : WriteRes<WriteNop, []>; 261} // SchedModel 262