X86Subtarget.cpp revision fb5e6804f3aca40c78d88d6810ad22853816ae06 
1//===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the X86 specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "subtarget"
15#include "X86Subtarget.h"
16#include "X86InstrInfo.h"
17#include "llvm/IR/Attributes.h"
18#include "llvm/IR/Function.h"
19#include "llvm/IR/GlobalValue.h"
20#include "llvm/Support/Debug.h"
21#include "llvm/Support/ErrorHandling.h"
22#include "llvm/Support/Host.h"
23#include "llvm/Support/raw_ostream.h"
24#include "llvm/Target/TargetMachine.h"
25#include "llvm/Target/TargetOptions.h"
26
27#define GET_SUBTARGETINFO_TARGET_DESC
28#define GET_SUBTARGETINFO_CTOR
29#include "X86GenSubtargetInfo.inc"
30
31using namespace llvm;
32
33#if defined(_MSC_VER)
34#include <intrin.h>
35#endif
36
37/// ClassifyBlockAddressReference - Classify a blockaddress reference for the
38/// current subtarget according to how we should reference it in a non-pcrel
39/// context.
40unsigned char X86Subtarget::ClassifyBlockAddressReference() const {
41  if (isPICStyleGOT())    // 32-bit ELF targets.
42    return X86II::MO_GOTOFF;
43
44  if (isPICStyleStubPIC())   // Darwin/32 in PIC mode.
45    return X86II::MO_PIC_BASE_OFFSET;
46
47  // Direct static reference to label.
48  return X86II::MO_NO_FLAG;
49}
50
51/// ClassifyGlobalReference - Classify a global variable reference for the
52/// current subtarget according to how we should reference it in a non-pcrel
53/// context.
54unsigned char X86Subtarget::
55ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
56  // DLLImport only exists on windows, it is implemented as a load from a
57  // DLLIMPORT stub.
58  if (GV->hasDLLImportLinkage())
59    return X86II::MO_DLLIMPORT;
60
61  // Determine whether this is a reference to a definition or a declaration.
62  // Materializable GVs (in JIT lazy compilation mode) do not require an extra
63  // load from stub.
64  bool isDecl = GV->hasAvailableExternallyLinkage();
65  if (GV->isDeclaration() && !GV->isMaterializable())
66    isDecl = true;
67
68  // X86-64 in PIC mode.
69  if (isPICStyleRIPRel()) {
70    // Large model never uses stubs.
71    if (TM.getCodeModel() == CodeModel::Large)
72      return X86II::MO_NO_FLAG;
73
74    if (isTargetDarwin()) {
75      // If symbol visibility is hidden, the extra load is not needed if
76      // target is x86-64 or the symbol is definitely defined in the current
77      // translation unit.
78      if (GV->hasDefaultVisibility() &&
79          (isDecl || GV->isWeakForLinker()))
80        return X86II::MO_GOTPCREL;
81    } else if (!isTargetWin64()) {
82      assert(isTargetELF() && "Unknown rip-relative target");
83
84      // Extra load is needed for all externally visible.
85      if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
86        return X86II::MO_GOTPCREL;
87    }
88
89    return X86II::MO_NO_FLAG;
90  }
91
92  if (isPICStyleGOT()) {   // 32-bit ELF targets.
93    // Extra load is needed for all externally visible.
94    if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
95      return X86II::MO_GOTOFF;
96    return X86II::MO_GOT;
97  }
98
99  if (isPICStyleStubPIC()) {  // Darwin/32 in PIC mode.
100    // Determine whether we have a stub reference and/or whether the reference
101    // is relative to the PIC base or not.
102
103    // If this is a strong reference to a definition, it is definitely not
104    // through a stub.
105    if (!isDecl && !GV->isWeakForLinker())
106      return X86II::MO_PIC_BASE_OFFSET;
107
108    // Unless we have a symbol with hidden visibility, we have to go through a
109    // normal $non_lazy_ptr stub because this symbol might be resolved late.
110    if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
111      return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
112
113    // If symbol visibility is hidden, we have a stub for common symbol
114    // references and external declarations.
115    if (isDecl || GV->hasCommonLinkage()) {
116      // Hidden $non_lazy_ptr reference.
117      return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
118    }
119
120    // Otherwise, no stub.
121    return X86II::MO_PIC_BASE_OFFSET;
122  }
123
124  if (isPICStyleStubNoDynamic()) {  // Darwin/32 in -mdynamic-no-pic mode.
125    // Determine whether we have a stub reference.
126
127    // If this is a strong reference to a definition, it is definitely not
128    // through a stub.
129    if (!isDecl && !GV->isWeakForLinker())
130      return X86II::MO_NO_FLAG;
131
132    // Unless we have a symbol with hidden visibility, we have to go through a
133    // normal $non_lazy_ptr stub because this symbol might be resolved late.
134    if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
135      return X86II::MO_DARWIN_NONLAZY;
136
137    // Otherwise, no stub.
138    return X86II::MO_NO_FLAG;
139  }
140
141  // Direct static reference to global.
142  return X86II::MO_NO_FLAG;
143}
144
145
146/// getBZeroEntry - This function returns the name of a function which has an
147/// interface like the non-standard bzero function, if such a function exists on
148/// the current subtarget and it is considered prefereable over memset with zero
149/// passed as the second argument. Otherwise it returns null.
150const char *X86Subtarget::getBZeroEntry() const {
151  // Darwin 10 has a __bzero entry point for this purpose.
152  if (getTargetTriple().isMacOSX() &&
153      !getTargetTriple().isMacOSXVersionLT(10, 6))
154    return "__bzero";
155
156  return 0;
157}
158
159bool X86Subtarget::hasSinCos() const {
160  return getTargetTriple().isMacOSX() &&
161    !getTargetTriple().isMacOSXVersionLT(10, 9) &&
162    is64Bit();
163}
164
165/// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
166/// to immediate address.
167bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
168  if (In64BitMode)
169    return false;
170  return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
171}
172
173static bool OSHasAVXSupport() {
174#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
175    || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
176#if defined(__GNUC__)
177  // Check xgetbv; this uses a .byte sequence instead of the instruction
178  // directly because older assemblers do not include support for xgetbv and
179  // there is no easy way to conditionally compile based on the assembler used.
180  int rEAX, rEDX;
181  __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
182#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
183  unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
184#else
185  int rEAX = 0; // Ensures we return false
186#endif
187  return (rEAX & 6) == 6;
188#else
189  return false;
190#endif
191}
192
193void X86Subtarget::AutoDetectSubtargetFeatures() {
194  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
195  unsigned MaxLevel;
196  union {
197    unsigned u[3];
198    char     c[12];
199  } text;
200
201  if (X86_MC::GetCpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
202      MaxLevel < 1)
203    return;
204
205  X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
206
207  if ((EDX >> 15) & 1) { HasCMov = true;      ToggleFeature(X86::FeatureCMOV); }
208  if ((EDX >> 23) & 1) { X86SSELevel = MMX;   ToggleFeature(X86::FeatureMMX);  }
209  if ((EDX >> 25) & 1) { X86SSELevel = SSE1;  ToggleFeature(X86::FeatureSSE1); }
210  if ((EDX >> 26) & 1) { X86SSELevel = SSE2;  ToggleFeature(X86::FeatureSSE2); }
211  if (ECX & 0x1)       { X86SSELevel = SSE3;  ToggleFeature(X86::FeatureSSE3); }
212  if ((ECX >> 9)  & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
213  if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
214  if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
215  if (((ECX >> 27) & 1) && ((ECX >> 28) & 1) && OSHasAVXSupport()) {
216    X86SSELevel = AVX;   ToggleFeature(X86::FeatureAVX);
217  }
218
219  bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
220  bool IsAMD   = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
221
222  if ((ECX >> 1) & 0x1) {
223    HasPCLMUL = true;
224    ToggleFeature(X86::FeaturePCLMUL);
225  }
226  if ((ECX >> 12) & 0x1) {
227    HasFMA = true;
228    ToggleFeature(X86::FeatureFMA);
229  }
230  if (IsIntel && ((ECX >> 22) & 0x1)) {
231    HasMOVBE = true;
232    ToggleFeature(X86::FeatureMOVBE);
233  }
234  if ((ECX >> 23) & 0x1) {
235    HasPOPCNT = true;
236    ToggleFeature(X86::FeaturePOPCNT);
237  }
238  if ((ECX >> 25) & 0x1) {
239    HasAES = true;
240    ToggleFeature(X86::FeatureAES);
241  }
242  if ((ECX >> 29) & 0x1) {
243    HasF16C = true;
244    ToggleFeature(X86::FeatureF16C);
245  }
246  if (IsIntel && ((ECX >> 30) & 0x1)) {
247    HasRDRAND = true;
248    ToggleFeature(X86::FeatureRDRAND);
249  }
250
251  if ((ECX >> 13) & 0x1) {
252    HasCmpxchg16b = true;
253    ToggleFeature(X86::FeatureCMPXCHG16B);
254  }
255
256  if (IsIntel || IsAMD) {
257    // Determine if bit test memory instructions are slow.
258    unsigned Family = 0;
259    unsigned Model  = 0;
260    X86_MC::DetectFamilyModel(EAX, Family, Model);
261    if (IsAMD || (Family == 6 && Model >= 13)) {
262      IsBTMemSlow = true;
263      ToggleFeature(X86::FeatureSlowBTMem);
264    }
265
266    // If it's an Intel chip since Nehalem and not an Atom chip, unaligned
267    // memory access is fast. We hard code model numbers here because they
268    // aren't strictly increasing for Intel chips it seems.
269    if (IsIntel &&
270        ((Family == 6 && Model == 0x1E) || // Nehalem: Clarksfield, Lynnfield,
271                                           //          Jasper Froest
272         (Family == 6 && Model == 0x1A) || // Nehalem: Bloomfield, Nehalem-EP
273         (Family == 6 && Model == 0x2E) || // Nehalem: Nehalem-EX
274         (Family == 6 && Model == 0x25) || // Westmere: Arrandale, Clarksdale
275         (Family == 6 && Model == 0x2C) || // Westmere: Gulftown, Westmere-EP
276         (Family == 6 && Model == 0x2F) || // Westmere: Westmere-EX
277         (Family == 6 && Model == 0x2A) || // SandyBridge
278         (Family == 6 && Model == 0x2D) || // SandyBridge: SandyBridge-E*
279         (Family == 6 && Model == 0x3A) || // IvyBridge
280         (Family == 6 && Model == 0x3E) || // IvyBridge EP
281         (Family == 6 && Model == 0x3C) || // Haswell
282         (Family == 6 && Model == 0x3F) || // ...
283         (Family == 6 && Model == 0x45) || // ...
284         (Family == 6 && Model == 0x46))) { // ...
285      IsUAMemFast = true;
286      ToggleFeature(X86::FeatureFastUAMem);
287    }
288
289    // Set processor type. Currently only Atom or Silvermont (SLM) is detected.
290    if (Family == 6 &&
291        (Model == 28 || Model == 38 || Model == 39 ||
292         Model == 53 || Model == 54)) {
293      X86ProcFamily = IntelAtom;
294
295      UseLeaForSP = true;
296      ToggleFeature(X86::FeatureLeaForSP);
297    }
298    else if (Family == 6 &&
299        (Model == 55 || Model == 74 || Model == 77)) {
300      X86ProcFamily = IntelSLM;
301    }
302
303    unsigned MaxExtLevel;
304    X86_MC::GetCpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
305
306    if (MaxExtLevel >= 0x80000001) {
307      X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
308      if ((EDX >> 29) & 0x1) {
309        HasX86_64 = true;
310        ToggleFeature(X86::Feature64Bit);
311      }
312      if ((ECX >> 5) & 0x1) {
313        HasLZCNT = true;
314        ToggleFeature(X86::FeatureLZCNT);
315      }
316      if (IsIntel && ((ECX >> 8) & 0x1)) {
317        HasPRFCHW = true;
318        ToggleFeature(X86::FeaturePRFCHW);
319      }
320      if (IsAMD) {
321        if ((ECX >> 6) & 0x1) {
322          HasSSE4A = true;
323          ToggleFeature(X86::FeatureSSE4A);
324        }
325        if ((ECX >> 11) & 0x1) {
326          HasXOP = true;
327          ToggleFeature(X86::FeatureXOP);
328        }
329        if ((ECX >> 16) & 0x1) {
330          HasFMA4 = true;
331          ToggleFeature(X86::FeatureFMA4);
332        }
333      }
334    }
335  }
336
337  if (MaxLevel >= 7) {
338    if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
339      if (IsIntel && (EBX & 0x1)) {
340        HasFSGSBase = true;
341        ToggleFeature(X86::FeatureFSGSBase);
342      }
343      if ((EBX >> 3) & 0x1) {
344        HasBMI = true;
345        ToggleFeature(X86::FeatureBMI);
346      }
347      if ((EBX >> 4) & 0x1) {
348        HasHLE = true;
349        ToggleFeature(X86::FeatureHLE);
350      }
351      if (IsIntel && ((EBX >> 5) & 0x1)) {
352        X86SSELevel = AVX2;
353        ToggleFeature(X86::FeatureAVX2);
354      }
355      if (IsIntel && ((EBX >> 8) & 0x1)) {
356        HasBMI2 = true;
357        ToggleFeature(X86::FeatureBMI2);
358      }
359      if (IsIntel && ((EBX >> 11) & 0x1)) {
360        HasRTM = true;
361        ToggleFeature(X86::FeatureRTM);
362      }
363      if (IsIntel && ((EBX >> 16) & 0x1)) {
364        X86SSELevel = AVX512F;
365        ToggleFeature(X86::FeatureAVX512);
366      }
367      if (IsIntel && ((EBX >> 18) & 0x1)) {
368        HasRDSEED = true;
369        ToggleFeature(X86::FeatureRDSEED);
370      }
371      if (IsIntel && ((EBX >> 19) & 0x1)) {
372        HasADX = true;
373        ToggleFeature(X86::FeatureADX);
374      }
375      if (IsIntel && ((EBX >> 26) & 0x1)) {
376        HasPFI = true;
377        ToggleFeature(X86::FeaturePFI);
378      }
379      if (IsIntel && ((EBX >> 27) & 0x1)) {
380        HasERI = true;
381        ToggleFeature(X86::FeatureERI);
382      }
383      if (IsIntel && ((EBX >> 28) & 0x1)) {
384        HasCDI = true;
385        ToggleFeature(X86::FeatureCDI);
386      }
387      if (IsIntel && ((EBX >> 29) & 0x1)) {
388        HasSHA = true;
389        ToggleFeature(X86::FeatureSHA);
390      }
391    }
392    if (IsAMD && ((ECX >> 21) & 0x1)) {
393      HasTBM = true;
394      ToggleFeature(X86::FeatureTBM);
395    }
396  }
397}
398
399void X86Subtarget::resetSubtargetFeatures(const MachineFunction *MF) {
400  AttributeSet FnAttrs = MF->getFunction()->getAttributes();
401  Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
402                                           "target-cpu");
403  Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
404                                          "target-features");
405  std::string CPU =
406    !CPUAttr.hasAttribute(Attribute::None) ?CPUAttr.getValueAsString() : "";
407  std::string FS =
408    !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
409  if (!FS.empty()) {
410    initializeEnvironment();
411    resetSubtargetFeatures(CPU, FS);
412  }
413}
414
415void X86Subtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
416  std::string CPUName = CPU;
417  if (!FS.empty() || !CPU.empty()) {
418    if (CPUName.empty()) {
419#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
420    || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
421      CPUName = sys::getHostCPUName();
422#else
423      CPUName = "generic";
424#endif
425    }
426
427    // Make sure 64-bit features are available in 64-bit mode. (But make sure
428    // SSE2 can be turned off explicitly.)
429    std::string FullFS = FS;
430    if (In64BitMode) {
431      if (!FullFS.empty())
432        FullFS = "+64bit,+sse2," + FullFS;
433      else
434        FullFS = "+64bit,+sse2";
435    }
436
437    // If feature string is not empty, parse features string.
438    ParseSubtargetFeatures(CPUName, FullFS);
439  } else {
440    if (CPUName.empty()) {
441#if defined (__x86_64__) || defined(__i386__)
442      CPUName = sys::getHostCPUName();
443#else
444      CPUName = "generic";
445#endif
446    }
447    // Otherwise, use CPUID to auto-detect feature set.
448    AutoDetectSubtargetFeatures();
449
450    // Make sure 64-bit features are available in 64-bit mode.
451    if (In64BitMode) {
452      if (!HasX86_64) { HasX86_64 = true; ToggleFeature(X86::Feature64Bit); }
453      if (!HasCMov)   { HasCMov   = true; ToggleFeature(X86::FeatureCMOV); }
454
455      if (X86SSELevel < SSE2) {
456        X86SSELevel = SSE2;
457        ToggleFeature(X86::FeatureSSE1);
458        ToggleFeature(X86::FeatureSSE2);
459      }
460    }
461  }
462
463  // CPUName may have been set by the CPU detection code. Make sure the
464  // new MCSchedModel is used.
465  InitCPUSchedModel(CPUName);
466
467  if (X86ProcFamily == IntelAtom || X86ProcFamily == IntelSLM)
468    PostRAScheduler = true;
469
470  InstrItins = getInstrItineraryForCPU(CPUName);
471
472  // It's important to keep the MCSubtargetInfo feature bits in sync with
473  // target data structure which is shared with MC code emitter, etc.
474  if (In64BitMode)
475    ToggleFeature(X86::Mode64Bit);
476
477  DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
478               << ", 3DNowLevel " << X863DNowLevel
479               << ", 64bit " << HasX86_64 << "\n");
480  assert((!In64BitMode || HasX86_64) &&
481         "64-bit code requested on a subtarget that doesn't support it!");
482
483  // Stack alignment is 16 bytes on Darwin, Linux and Solaris (both
484  // 32 and 64 bit) and for all 64-bit targets.
485  if (StackAlignOverride)
486    stackAlignment = StackAlignOverride;
487  else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
488           In64BitMode)
489    stackAlignment = 16;
490}
491
492void X86Subtarget::initializeEnvironment() {
493  X86SSELevel = NoMMXSSE;
494  X863DNowLevel = NoThreeDNow;
495  HasCMov = false;
496  HasX86_64 = false;
497  HasPOPCNT = false;
498  HasSSE4A = false;
499  HasAES = false;
500  HasPCLMUL = false;
501  HasFMA = false;
502  HasFMA4 = false;
503  HasXOP = false;
504  HasTBM = false;
505  HasMOVBE = false;
506  HasRDRAND = false;
507  HasF16C = false;
508  HasFSGSBase = false;
509  HasLZCNT = false;
510  HasBMI = false;
511  HasBMI2 = false;
512  HasRTM = false;
513  HasHLE = false;
514  HasERI = false;
515  HasCDI = false;
516  HasPFI = false;
517  HasADX = false;
518  HasSHA = false;
519  HasPRFCHW = false;
520  HasRDSEED = false;
521  IsBTMemSlow = false;
522  IsUAMemFast = false;
523  HasVectorUAMem = false;
524  HasCmpxchg16b = false;
525  UseLeaForSP = false;
526  HasSlowDivide = false;
527  PostRAScheduler = false;
528  PadShortFunctions = false;
529  CallRegIndirect = false;
530  LEAUsesAG = false;
531  stackAlignment = 4;
532  // FIXME: this is a known good value for Yonah. How about others?
533  MaxInlineSizeThreshold = 128;
534}
535
536X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
537                           const std::string &FS,
538                           unsigned StackAlignOverride, bool is64Bit)
539  : X86GenSubtargetInfo(TT, CPU, FS)
540  , X86ProcFamily(Others)
541  , PICStyle(PICStyles::None)
542  , TargetTriple(TT)
543  , StackAlignOverride(StackAlignOverride)
544  , In64BitMode(is64Bit) {
545  initializeEnvironment();
546  resetSubtargetFeatures(CPU, FS);
547}
548
549bool X86Subtarget::enablePostRAScheduler(
550           CodeGenOpt::Level OptLevel,
551           TargetSubtargetInfo::AntiDepBreakMode& Mode,
552           RegClassVector& CriticalPathRCs) const {
553  Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
554  CriticalPathRCs.clear();
555  return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
556}
557