X86TargetMachine.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the X86 specific subclass of TargetMachine. 11// 12//===----------------------------------------------------------------------===// 13 14#include "X86TargetMachine.h" 15#include "X86.h" 16#include "llvm/CodeGen/Passes.h" 17#include "llvm/PassManager.h" 18#include "llvm/Support/CommandLine.h" 19#include "llvm/Support/FormattedStream.h" 20#include "llvm/Support/TargetRegistry.h" 21#include "llvm/Target/TargetOptions.h" 22using namespace llvm; 23 24extern "C" void LLVMInitializeX86Target() { 25 // Register the target. 26 RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target); 27 RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target); 28} 29 30void X86TargetMachine::anchor() { } 31 32static std::string computeDataLayout(const X86Subtarget &ST) { 33 // X86 is little endian 34 std::string Ret = "e"; 35 36 Ret += DataLayout::getManglingComponent(ST.getTargetTriple()); 37 // X86 and x32 have 32 bit pointers. 38 if (ST.isTarget64BitILP32() || !ST.is64Bit()) 39 Ret += "-p:32:32"; 40 41 // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32. 42 if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetKnownWindowsMSVC() || 43 ST.isTargetNaCl()) 44 Ret += "-i64:64"; 45 else 46 Ret += "-f64:32:64"; 47 48 // Some ABIs align long double to 128 bits, others to 32. 49 if (ST.isTargetNaCl()) 50 ; // No f80 51 else if (ST.is64Bit() || ST.isTargetDarwin()) 52 Ret += "-f80:128"; 53 else 54 Ret += "-f80:32"; 55 56 // The registers can hold 8, 16, 32 or, in x86-64, 64 bits. 57 if (ST.is64Bit()) 58 Ret += "-n8:16:32:64"; 59 else 60 Ret += "-n8:16:32"; 61 62 // The stack is aligned to 32 bits on some ABIs and 128 bits on others. 63 if (!ST.is64Bit() && (ST.isTargetCygMing() || ST.isTargetKnownWindowsMSVC())) 64 Ret += "-S32"; 65 else 66 Ret += "-S128"; 67 68 return Ret; 69} 70 71/// X86TargetMachine ctor - Create an X86 target. 72/// 73X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, 74 StringRef CPU, StringRef FS, 75 const TargetOptions &Options, 76 Reloc::Model RM, CodeModel::Model CM, 77 CodeGenOpt::Level OL) 78 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 79 Subtarget(TT, CPU, FS, Options.StackAlignmentOverride), 80 FrameLowering(*this, Subtarget), 81 InstrItins(Subtarget.getInstrItineraryData()), 82 DL(computeDataLayout(*getSubtargetImpl())), 83 InstrInfo(*this), 84 TLInfo(*this), 85 TSInfo(*this), 86 JITInfo(*this) { 87 // Determine the PICStyle based on the target selected. 88 if (getRelocationModel() == Reloc::Static) { 89 // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None. 90 Subtarget.setPICStyle(PICStyles::None); 91 } else if (Subtarget.is64Bit()) { 92 // PIC in 64 bit mode is always rip-rel. 93 Subtarget.setPICStyle(PICStyles::RIPRel); 94 } else if (Subtarget.isTargetCOFF()) { 95 Subtarget.setPICStyle(PICStyles::None); 96 } else if (Subtarget.isTargetDarwin()) { 97 if (getRelocationModel() == Reloc::PIC_) 98 Subtarget.setPICStyle(PICStyles::StubPIC); 99 else { 100 assert(getRelocationModel() == Reloc::DynamicNoPIC); 101 Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC); 102 } 103 } else if (Subtarget.isTargetELF()) { 104 Subtarget.setPICStyle(PICStyles::GOT); 105 } 106 107 // default to hard float ABI 108 if (Options.FloatABIType == FloatABI::Default) 109 this->Options.FloatABIType = FloatABI::Hard; 110 111 initAsmInfo(); 112} 113 114//===----------------------------------------------------------------------===// 115// Command line options for x86 116//===----------------------------------------------------------------------===// 117static cl::opt<bool> 118UseVZeroUpper("x86-use-vzeroupper", cl::Hidden, 119 cl::desc("Minimize AVX to SSE transition penalty"), 120 cl::init(true)); 121 122// Temporary option to control early if-conversion for x86 while adding machine 123// models. 124static cl::opt<bool> 125X86EarlyIfConv("x86-early-ifcvt", cl::Hidden, 126 cl::desc("Enable early if-conversion on X86")); 127 128//===----------------------------------------------------------------------===// 129// X86 Analysis Pass Setup 130//===----------------------------------------------------------------------===// 131 132void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) { 133 // Add first the target-independent BasicTTI pass, then our X86 pass. This 134 // allows the X86 pass to delegate to the target independent layer when 135 // appropriate. 136 PM.add(createBasicTargetTransformInfoPass(this)); 137 PM.add(createX86TargetTransformInfoPass(this)); 138} 139 140 141//===----------------------------------------------------------------------===// 142// Pass Pipeline Configuration 143//===----------------------------------------------------------------------===// 144 145namespace { 146/// X86 Code Generator Pass Configuration Options. 147class X86PassConfig : public TargetPassConfig { 148public: 149 X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM) 150 : TargetPassConfig(TM, PM) {} 151 152 X86TargetMachine &getX86TargetMachine() const { 153 return getTM<X86TargetMachine>(); 154 } 155 156 const X86Subtarget &getX86Subtarget() const { 157 return *getX86TargetMachine().getSubtargetImpl(); 158 } 159 160 bool addInstSelector() override; 161 bool addILPOpts() override; 162 bool addPreRegAlloc() override; 163 bool addPostRegAlloc() override; 164 bool addPreEmitPass() override; 165}; 166} // namespace 167 168TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) { 169 return new X86PassConfig(this, PM); 170} 171 172bool X86PassConfig::addInstSelector() { 173 // Install an instruction selector. 174 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel())); 175 176 // For ELF, cleanup any local-dynamic TLS accesses. 177 if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None) 178 addPass(createCleanupLocalDynamicTLSPass()); 179 180 // For 32-bit, prepend instructions to set the "global base reg" for PIC. 181 if (!getX86Subtarget().is64Bit()) 182 addPass(createGlobalBaseRegPass()); 183 184 return false; 185} 186 187bool X86PassConfig::addILPOpts() { 188 if (X86EarlyIfConv && getX86Subtarget().hasCMov()) { 189 addPass(&EarlyIfConverterID); 190 return true; 191 } 192 return false; 193} 194 195bool X86PassConfig::addPreRegAlloc() { 196 return false; // -print-machineinstr shouldn't print after this. 197} 198 199bool X86PassConfig::addPostRegAlloc() { 200 addPass(createX86FloatingPointStackifierPass()); 201 return true; // -print-machineinstr should print after this. 202} 203 204bool X86PassConfig::addPreEmitPass() { 205 bool ShouldPrint = false; 206 if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) { 207 addPass(createExecutionDependencyFixPass(&X86::VR128RegClass)); 208 ShouldPrint = true; 209 } 210 211 if (getX86Subtarget().hasAVX() && UseVZeroUpper) { 212 addPass(createX86IssueVZeroUpperPass()); 213 ShouldPrint = true; 214 } 215 216 if (getOptLevel() != CodeGenOpt::None && 217 getX86Subtarget().padShortFunctions()) { 218 addPass(createX86PadShortFunctions()); 219 ShouldPrint = true; 220 } 221 if (getOptLevel() != CodeGenOpt::None && 222 getX86Subtarget().LEAusesAG()){ 223 addPass(createX86FixupLEAs()); 224 ShouldPrint = true; 225 } 226 227 return ShouldPrint; 228} 229 230bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, 231 JITCodeEmitter &JCE) { 232 PM.add(createX86JITCodeEmitterPass(*this, JCE)); 233 234 return false; 235} 236