XCoreISelLowering.h revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that XCore uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef XCOREISELLOWERING_H
16#define XCOREISELLOWERING_H
17
18#include "XCore.h"
19#include "llvm/CodeGen/SelectionDAG.h"
20#include "llvm/Target/TargetLowering.h"
21
22namespace llvm {
23
24  // Forward delcarations
25  class XCoreSubtarget;
26  class XCoreTargetMachine;
27
28  namespace XCoreISD {
29    enum NodeType {
30      // Start the numbering where the builtin ops and target ops leave off.
31      FIRST_NUMBER = ISD::BUILTIN_OP_END,
32
33      // Branch and link (call)
34      BL,
35
36      // pc relative address
37      PCRelativeWrapper,
38
39      // dp relative address
40      DPRelativeWrapper,
41
42      // cp relative address
43      CPRelativeWrapper,
44
45      // Load word from stack
46      LDWSP,
47
48      // Store word to stack
49      STWSP,
50
51      // Corresponds to retsp instruction
52      RETSP,
53
54      // Corresponds to LADD instruction
55      LADD,
56
57      // Corresponds to LSUB instruction
58      LSUB,
59
60      // Corresponds to LMUL instruction
61      LMUL,
62
63      // Corresponds to MACCU instruction
64      MACCU,
65
66      // Corresponds to MACCS instruction
67      MACCS,
68
69      // Corresponds to CRC8 instruction
70      CRC8,
71
72      // Jumptable branch.
73      BR_JT,
74
75      // Jumptable branch using long branches for each entry.
76      BR_JT32,
77
78      // Offset from frame pointer to the first (possible) on-stack argument
79      FRAME_TO_ARGS_OFFSET,
80
81      // Exception handler return. The stack is restored to the first
82      // followed by a jump to the second argument.
83      EH_RETURN,
84
85      // Memory barrier.
86      MEMBARRIER
87    };
88  }
89
90  //===--------------------------------------------------------------------===//
91  // TargetLowering Implementation
92  //===--------------------------------------------------------------------===//
93  class XCoreTargetLowering : public TargetLowering
94  {
95  public:
96
97    explicit XCoreTargetLowering(XCoreTargetMachine &TM);
98
99    using TargetLowering::isZExtFree;
100    virtual bool isZExtFree(SDValue Val, EVT VT2) const;
101
102
103    virtual unsigned getJumpTableEncoding() const;
104    virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
105
106    /// LowerOperation - Provide custom lowering hooks for some operations.
107    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
108
109    /// ReplaceNodeResults - Replace the results of node with an illegal result
110    /// type with new values built out of custom code.
111    ///
112    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
113                                    SelectionDAG &DAG) const;
114
115    /// getTargetNodeName - This method returns the name of a target specific
116    //  DAG node.
117    virtual const char *getTargetNodeName(unsigned Opcode) const;
118
119    virtual MachineBasicBlock *
120      EmitInstrWithCustomInserter(MachineInstr *MI,
121                                  MachineBasicBlock *MBB) const;
122
123    virtual bool isLegalAddressingMode(const AddrMode &AM,
124                                       Type *Ty) const;
125
126  private:
127    const XCoreTargetMachine &TM;
128    const XCoreSubtarget &Subtarget;
129
130    // Lower Operand helpers
131    SDValue LowerCCCArguments(SDValue Chain,
132                              CallingConv::ID CallConv,
133                              bool isVarArg,
134                              const SmallVectorImpl<ISD::InputArg> &Ins,
135                              SDLoc dl, SelectionDAG &DAG,
136                              SmallVectorImpl<SDValue> &InVals) const;
137    SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
138                           CallingConv::ID CallConv, bool isVarArg,
139                           bool isTailCall,
140                           const SmallVectorImpl<ISD::OutputArg> &Outs,
141                           const SmallVectorImpl<SDValue> &OutVals,
142                           const SmallVectorImpl<ISD::InputArg> &Ins,
143                           SDLoc dl, SelectionDAG &DAG,
144                           SmallVectorImpl<SDValue> &InVals) const;
145    SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
146    SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
147                                    SelectionDAG &DAG) const;
148    SDValue lowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain,
149                                                   SDValue Base, int64_t Offset,
150                                                   SelectionDAG &DAG) const;
151
152    // Lower Operand specifics
153    SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
154    SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
155    SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
156    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
157    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
158    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
159    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
160    SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
161    SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
162    SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
163    SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
164    SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
165    SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
166    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
167    SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
168    SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
169    SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
170    SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
171    SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
172    SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
173    SDValue LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
174    SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
175
176    // Inline asm support
177    std::pair<unsigned, const TargetRegisterClass*>
178    getRegForInlineAsmConstraint(const std::string &Constraint,
179                                 MVT VT) const;
180
181    // Expand specifics
182    SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
183    SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
184
185    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
186
187    virtual void computeMaskedBitsForTargetNode(const SDValue Op,
188                                                APInt &KnownZero,
189                                                APInt &KnownOne,
190                                                const SelectionDAG &DAG,
191                                                unsigned Depth = 0) const;
192
193    virtual SDValue
194      LowerFormalArguments(SDValue Chain,
195                           CallingConv::ID CallConv,
196                           bool isVarArg,
197                           const SmallVectorImpl<ISD::InputArg> &Ins,
198                           SDLoc dl, SelectionDAG &DAG,
199                           SmallVectorImpl<SDValue> &InVals) const;
200
201    virtual SDValue
202      LowerCall(TargetLowering::CallLoweringInfo &CLI,
203                SmallVectorImpl<SDValue> &InVals) const;
204
205    virtual SDValue
206      LowerReturn(SDValue Chain,
207                  CallingConv::ID CallConv, bool isVarArg,
208                  const SmallVectorImpl<ISD::OutputArg> &Outs,
209                  const SmallVectorImpl<SDValue> &OutVals,
210                  SDLoc dl, SelectionDAG &DAG) const;
211
212    virtual bool
213      CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
214                     bool isVarArg,
215                     const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
216                     LLVMContext &Context) const;
217  };
218}
219
220#endif // XCOREISELLOWERING_H
221