1; Test zero extensions from a halfword to an i64.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
4
5; Test register extension, starting with an i32.
6define i64 @f1(i32 %a) {
7; CHECK-LABEL: f1:
8; CHECK: llghr %r2, %r2
9; CHECK: br %r14
10  %half = trunc i32 %a to i16
11  %ext = zext i16 %half to i64
12  ret i64 %ext
13}
14
15; ...and again with an i64.
16define i64 @f2(i64 %a) {
17; CHECK-LABEL: f2:
18; CHECK: llghr %r2, %r2
19; CHECK: br %r14
20  %half = trunc i64 %a to i16
21  %ext = zext i16 %half to i64
22  ret i64 %ext
23}
24
25; Check ANDs that are equivalent to zero extension.
26define i64 @f3(i64 %a) {
27; CHECK-LABEL: f3:
28; CHECK: llghr %r2, %r2
29; CHECK: br %r14
30  %ext = and i64 %a, 65535
31  ret i64 %ext
32}
33
34; Check LLGH with no displacement.
35define i64 @f4(i16 *%src) {
36; CHECK-LABEL: f4:
37; CHECK: llgh %r2, 0(%r2)
38; CHECK: br %r14
39  %half = load i16 *%src
40  %ext = zext i16 %half to i64
41  ret i64 %ext
42}
43
44; Check the high end of the LLGH range.
45define i64 @f5(i16 *%src) {
46; CHECK-LABEL: f5:
47; CHECK: llgh %r2, 524286(%r2)
48; CHECK: br %r14
49  %ptr = getelementptr i16 *%src, i64 262143
50  %half = load i16 *%ptr
51  %ext = zext i16 %half to i64
52  ret i64 %ext
53}
54
55; Check the next halfword up, which needs separate address logic.
56; Other sequences besides this one would be OK.
57define i64 @f6(i16 *%src) {
58; CHECK-LABEL: f6:
59; CHECK: agfi %r2, 524288
60; CHECK: llgh %r2, 0(%r2)
61; CHECK: br %r14
62  %ptr = getelementptr i16 *%src, i64 262144
63  %half = load i16 *%ptr
64  %ext = zext i16 %half to i64
65  ret i64 %ext
66}
67
68; Check the high end of the negative LLGH range.
69define i64 @f7(i16 *%src) {
70; CHECK-LABEL: f7:
71; CHECK: llgh %r2, -2(%r2)
72; CHECK: br %r14
73  %ptr = getelementptr i16 *%src, i64 -1
74  %half = load i16 *%ptr
75  %ext = zext i16 %half to i64
76  ret i64 %ext
77}
78
79; Check the low end of the LLGH range.
80define i64 @f8(i16 *%src) {
81; CHECK-LABEL: f8:
82; CHECK: llgh %r2, -524288(%r2)
83; CHECK: br %r14
84  %ptr = getelementptr i16 *%src, i64 -262144
85  %half = load i16 *%ptr
86  %ext = zext i16 %half to i64
87  ret i64 %ext
88}
89
90; Check the next halfword down, which needs separate address logic.
91; Other sequences besides this one would be OK.
92define i64 @f9(i16 *%src) {
93; CHECK-LABEL: f9:
94; CHECK: agfi %r2, -524290
95; CHECK: llgh %r2, 0(%r2)
96; CHECK: br %r14
97  %ptr = getelementptr i16 *%src, i64 -262145
98  %half = load i16 *%ptr
99  %ext = zext i16 %half to i64
100  ret i64 %ext
101}
102
103; Check that LLGH allows an index
104define i64 @f10(i64 %src, i64 %index) {
105; CHECK-LABEL: f10:
106; CHECK: llgh %r2, 524287(%r3,%r2)
107; CHECK: br %r14
108  %add1 = add i64 %src, %index
109  %add2 = add i64 %add1, 524287
110  %ptr = inttoptr i64 %add2 to i16 *
111  %half = load i16 *%ptr
112  %ext = zext i16 %half to i64
113  ret i64 %ext
114}
115
116; Test a case where we spill the source of at least one LLGHR.  We want
117; to use LLGH if possible.
118define void @f11(i64 *%ptr) {
119; CHECK-LABEL: f11:
120; CHECK: llgh {{%r[0-9]+}}, 166(%r15)
121; CHECK: br %r14
122  %val0 = load volatile i64 *%ptr
123  %val1 = load volatile i64 *%ptr
124  %val2 = load volatile i64 *%ptr
125  %val3 = load volatile i64 *%ptr
126  %val4 = load volatile i64 *%ptr
127  %val5 = load volatile i64 *%ptr
128  %val6 = load volatile i64 *%ptr
129  %val7 = load volatile i64 *%ptr
130  %val8 = load volatile i64 *%ptr
131  %val9 = load volatile i64 *%ptr
132  %val10 = load volatile i64 *%ptr
133  %val11 = load volatile i64 *%ptr
134  %val12 = load volatile i64 *%ptr
135  %val13 = load volatile i64 *%ptr
136  %val14 = load volatile i64 *%ptr
137  %val15 = load volatile i64 *%ptr
138
139  %trunc0 = trunc i64 %val0 to i16
140  %trunc1 = trunc i64 %val1 to i16
141  %trunc2 = trunc i64 %val2 to i16
142  %trunc3 = trunc i64 %val3 to i16
143  %trunc4 = trunc i64 %val4 to i16
144  %trunc5 = trunc i64 %val5 to i16
145  %trunc6 = trunc i64 %val6 to i16
146  %trunc7 = trunc i64 %val7 to i16
147  %trunc8 = trunc i64 %val8 to i16
148  %trunc9 = trunc i64 %val9 to i16
149  %trunc10 = trunc i64 %val10 to i16
150  %trunc11 = trunc i64 %val11 to i16
151  %trunc12 = trunc i64 %val12 to i16
152  %trunc13 = trunc i64 %val13 to i16
153  %trunc14 = trunc i64 %val14 to i16
154  %trunc15 = trunc i64 %val15 to i16
155
156  %ext0 = zext i16 %trunc0 to i64
157  %ext1 = zext i16 %trunc1 to i64
158  %ext2 = zext i16 %trunc2 to i64
159  %ext3 = zext i16 %trunc3 to i64
160  %ext4 = zext i16 %trunc4 to i64
161  %ext5 = zext i16 %trunc5 to i64
162  %ext6 = zext i16 %trunc6 to i64
163  %ext7 = zext i16 %trunc7 to i64
164  %ext8 = zext i16 %trunc8 to i64
165  %ext9 = zext i16 %trunc9 to i64
166  %ext10 = zext i16 %trunc10 to i64
167  %ext11 = zext i16 %trunc11 to i64
168  %ext12 = zext i16 %trunc12 to i64
169  %ext13 = zext i16 %trunc13 to i64
170  %ext14 = zext i16 %trunc14 to i64
171  %ext15 = zext i16 %trunc15 to i64
172
173  store volatile i64 %val0, i64 *%ptr
174  store volatile i64 %val1, i64 *%ptr
175  store volatile i64 %val2, i64 *%ptr
176  store volatile i64 %val3, i64 *%ptr
177  store volatile i64 %val4, i64 *%ptr
178  store volatile i64 %val5, i64 *%ptr
179  store volatile i64 %val6, i64 *%ptr
180  store volatile i64 %val7, i64 *%ptr
181  store volatile i64 %val8, i64 *%ptr
182  store volatile i64 %val9, i64 *%ptr
183  store volatile i64 %val10, i64 *%ptr
184  store volatile i64 %val11, i64 *%ptr
185  store volatile i64 %val12, i64 *%ptr
186  store volatile i64 %val13, i64 *%ptr
187  store volatile i64 %val14, i64 *%ptr
188  store volatile i64 %val15, i64 *%ptr
189
190  store volatile i64 %ext0, i64 *%ptr
191  store volatile i64 %ext1, i64 *%ptr
192  store volatile i64 %ext2, i64 *%ptr
193  store volatile i64 %ext3, i64 *%ptr
194  store volatile i64 %ext4, i64 *%ptr
195  store volatile i64 %ext5, i64 *%ptr
196  store volatile i64 %ext6, i64 *%ptr
197  store volatile i64 %ext7, i64 *%ptr
198  store volatile i64 %ext8, i64 *%ptr
199  store volatile i64 %ext9, i64 *%ptr
200  store volatile i64 %ext10, i64 *%ptr
201  store volatile i64 %ext11, i64 *%ptr
202  store volatile i64 %ext12, i64 *%ptr
203  store volatile i64 %ext13, i64 *%ptr
204  store volatile i64 %ext14, i64 *%ptr
205  store volatile i64 %ext15, i64 *%ptr
206
207  ret void
208}
209