1; Test 32-bit signed division and remainder. 2; 3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s 4 5declare i32 @foo() 6 7; Test register division. The result is in the second of the two registers. 8define void @f1(i32 *%dest, i32 %a, i32 %b) { 9; CHECK-LABEL: f1: 10; CHECK: lgfr %r1, %r3 11; CHECK: dsgfr %r0, %r4 12; CHECK: st %r1, 0(%r2) 13; CHECK: br %r14 14 %div = sdiv i32 %a, %b 15 store i32 %div, i32 *%dest 16 ret void 17} 18 19; Test register remainder. The result is in the first of the two registers. 20define void @f2(i32 *%dest, i32 %a, i32 %b) { 21; CHECK-LABEL: f2: 22; CHECK: lgfr %r1, %r3 23; CHECK: dsgfr %r0, %r4 24; CHECK: st %r0, 0(%r2) 25; CHECK: br %r14 26 %rem = srem i32 %a, %b 27 store i32 %rem, i32 *%dest 28 ret void 29} 30 31; Test that division and remainder use a single instruction. 32define i32 @f3(i32 %dummy, i32 %a, i32 %b) { 33; CHECK-LABEL: f3: 34; CHECK-NOT: %r2 35; CHECK: lgfr %r3, %r3 36; CHECK-NOT: %r2 37; CHECK: dsgfr %r2, %r4 38; CHECK-NOT: dsgfr 39; CHECK: or %r2, %r3 40; CHECK: br %r14 41 %div = sdiv i32 %a, %b 42 %rem = srem i32 %a, %b 43 %or = or i32 %rem, %div 44 ret i32 %or 45} 46 47; Check that the sign extension of the dividend is elided when the argument 48; is already sign-extended. 49define i32 @f4(i32 %dummy, i32 signext %a, i32 %b) { 50; CHECK-LABEL: f4: 51; CHECK-NOT: {{%r[234]}} 52; CHECK: dsgfr %r2, %r4 53; CHECK-NOT: dsgfr 54; CHECK: or %r2, %r3 55; CHECK: br %r14 56 %div = sdiv i32 %a, %b 57 %rem = srem i32 %a, %b 58 %or = or i32 %rem, %div 59 ret i32 %or 60} 61 62; Test that memory dividends are loaded using sign extension (LGF). 63define i32 @f5(i32 %dummy, i32 *%src, i32 %b) { 64; CHECK-LABEL: f5: 65; CHECK-NOT: %r2 66; CHECK: lgf %r3, 0(%r3) 67; CHECK-NOT: %r2 68; CHECK: dsgfr %r2, %r4 69; CHECK-NOT: dsgfr 70; CHECK: or %r2, %r3 71; CHECK: br %r14 72 %a = load i32 *%src 73 %div = sdiv i32 %a, %b 74 %rem = srem i32 %a, %b 75 %or = or i32 %rem, %div 76 ret i32 %or 77} 78 79; Test memory division with no displacement. 80define void @f6(i32 *%dest, i32 %a, i32 *%src) { 81; CHECK-LABEL: f6: 82; CHECK: lgfr %r1, %r3 83; CHECK: dsgf %r0, 0(%r4) 84; CHECK: st %r1, 0(%r2) 85; CHECK: br %r14 86 %b = load i32 *%src 87 %div = sdiv i32 %a, %b 88 store i32 %div, i32 *%dest 89 ret void 90} 91 92; Test memory remainder with no displacement. 93define void @f7(i32 *%dest, i32 %a, i32 *%src) { 94; CHECK-LABEL: f7: 95; CHECK: lgfr %r1, %r3 96; CHECK: dsgf %r0, 0(%r4) 97; CHECK: st %r0, 0(%r2) 98; CHECK: br %r14 99 %b = load i32 *%src 100 %rem = srem i32 %a, %b 101 store i32 %rem, i32 *%dest 102 ret void 103} 104 105; Test both memory division and memory remainder. 106define i32 @f8(i32 %dummy, i32 %a, i32 *%src) { 107; CHECK-LABEL: f8: 108; CHECK-NOT: %r2 109; CHECK: lgfr %r3, %r3 110; CHECK-NOT: %r2 111; CHECK: dsgf %r2, 0(%r4) 112; CHECK-NOT: {{dsgf|dsgfr}} 113; CHECK: or %r2, %r3 114; CHECK: br %r14 115 %b = load i32 *%src 116 %div = sdiv i32 %a, %b 117 %rem = srem i32 %a, %b 118 %or = or i32 %rem, %div 119 ret i32 %or 120} 121 122; Check the high end of the DSGF range. 123define i32 @f9(i32 %dummy, i32 %a, i32 *%src) { 124; CHECK-LABEL: f9: 125; CHECK: dsgf %r2, 524284(%r4) 126; CHECK: br %r14 127 %ptr = getelementptr i32 *%src, i64 131071 128 %b = load i32 *%ptr 129 %rem = srem i32 %a, %b 130 ret i32 %rem 131} 132 133; Check the next word up, which needs separate address logic. 134; Other sequences besides this one would be OK. 135define i32 @f10(i32 %dummy, i32 %a, i32 *%src) { 136; CHECK-LABEL: f10: 137; CHECK: agfi %r4, 524288 138; CHECK: dsgf %r2, 0(%r4) 139; CHECK: br %r14 140 %ptr = getelementptr i32 *%src, i64 131072 141 %b = load i32 *%ptr 142 %rem = srem i32 %a, %b 143 ret i32 %rem 144} 145 146; Check the high end of the negative aligned DSGF range. 147define i32 @f11(i32 %dummy, i32 %a, i32 *%src) { 148; CHECK-LABEL: f11: 149; CHECK: dsgf %r2, -4(%r4) 150; CHECK: br %r14 151 %ptr = getelementptr i32 *%src, i64 -1 152 %b = load i32 *%ptr 153 %rem = srem i32 %a, %b 154 ret i32 %rem 155} 156 157; Check the low end of the DSGF range. 158define i32 @f12(i32 %dummy, i32 %a, i32 *%src) { 159; CHECK-LABEL: f12: 160; CHECK: dsgf %r2, -524288(%r4) 161; CHECK: br %r14 162 %ptr = getelementptr i32 *%src, i64 -131072 163 %b = load i32 *%ptr 164 %rem = srem i32 %a, %b 165 ret i32 %rem 166} 167 168; Check the next word down, which needs separate address logic. 169; Other sequences besides this one would be OK. 170define i32 @f13(i32 %dummy, i32 %a, i32 *%src) { 171; CHECK-LABEL: f13: 172; CHECK: agfi %r4, -524292 173; CHECK: dsgf %r2, 0(%r4) 174; CHECK: br %r14 175 %ptr = getelementptr i32 *%src, i64 -131073 176 %b = load i32 *%ptr 177 %rem = srem i32 %a, %b 178 ret i32 %rem 179} 180 181; Check that DSGF allows an index. 182define i32 @f14(i32 %dummy, i32 %a, i64 %src, i64 %index) { 183; CHECK-LABEL: f14: 184; CHECK: dsgf %r2, 524287(%r5,%r4) 185; CHECK: br %r14 186 %add1 = add i64 %src, %index 187 %add2 = add i64 %add1, 524287 188 %ptr = inttoptr i64 %add2 to i32 * 189 %b = load i32 *%ptr 190 %rem = srem i32 %a, %b 191 ret i32 %rem 192} 193 194; Make sure that we still use DSGFR rather than DSGR in cases where 195; a load and division cannot be combined. 196define void @f15(i32 *%dest, i32 *%src) { 197; CHECK-LABEL: f15: 198; CHECK: l [[B:%r[0-9]+]], 0(%r3) 199; CHECK: brasl %r14, foo@PLT 200; CHECK: lgfr %r1, %r2 201; CHECK: dsgfr %r0, [[B]] 202; CHECK: br %r14 203 %b = load i32 *%src 204 %a = call i32 @foo() 205 %div = sdiv i32 %a, %b 206 store i32 %div, i32 *%dest 207 ret void 208} 209 210; Check that divisions of spilled values can use DSGF rather than DSGFR. 211define i32 @f16(i32 *%ptr0) { 212; CHECK-LABEL: f16: 213; CHECK: brasl %r14, foo@PLT 214; CHECK: dsgf {{%r[0-9]+}}, 16{{[04]}}(%r15) 215; CHECK: br %r14 216 %ptr1 = getelementptr i32 *%ptr0, i64 2 217 %ptr2 = getelementptr i32 *%ptr0, i64 4 218 %ptr3 = getelementptr i32 *%ptr0, i64 6 219 %ptr4 = getelementptr i32 *%ptr0, i64 8 220 %ptr5 = getelementptr i32 *%ptr0, i64 10 221 %ptr6 = getelementptr i32 *%ptr0, i64 12 222 %ptr7 = getelementptr i32 *%ptr0, i64 14 223 %ptr8 = getelementptr i32 *%ptr0, i64 16 224 %ptr9 = getelementptr i32 *%ptr0, i64 18 225 226 %val0 = load i32 *%ptr0 227 %val1 = load i32 *%ptr1 228 %val2 = load i32 *%ptr2 229 %val3 = load i32 *%ptr3 230 %val4 = load i32 *%ptr4 231 %val5 = load i32 *%ptr5 232 %val6 = load i32 *%ptr6 233 %val7 = load i32 *%ptr7 234 %val8 = load i32 *%ptr8 235 %val9 = load i32 *%ptr9 236 237 %ret = call i32 @foo() 238 239 %div0 = sdiv i32 %ret, %val0 240 %div1 = sdiv i32 %div0, %val1 241 %div2 = sdiv i32 %div1, %val2 242 %div3 = sdiv i32 %div2, %val3 243 %div4 = sdiv i32 %div3, %val4 244 %div5 = sdiv i32 %div4, %val5 245 %div6 = sdiv i32 %div5, %val6 246 %div7 = sdiv i32 %div6, %val7 247 %div8 = sdiv i32 %div7, %val8 248 %div9 = sdiv i32 %div8, %val9 249 250 ret i32 %div9 251} 252