AsmMatcherEmitter.cpp revision 414098571b19fc248fda2be194082cfd012d2729
1//===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend emits a target specifier matcher for converting parsed 11// assembly operands in the MCInst structures. 12// 13// The input to the target specific matcher is a list of literal tokens and 14// operands. The target specific parser should generally eliminate any syntax 15// which is not relevant for matching; for example, comma tokens should have 16// already been consumed and eliminated by the parser. Most instructions will 17// end up with a single literal token (the instruction name) and some number of 18// operands. 19// 20// Some example inputs, for X86: 21// 'addl' (immediate ...) (register ...) 22// 'add' (immediate ...) (memory ...) 23// 'call' '*' %epc 24// 25// The assembly matcher is responsible for converting this input into a precise 26// machine instruction (i.e., an instruction with a well defined encoding). This 27// mapping has several properties which complicate matching: 28// 29// - It may be ambiguous; many architectures can legally encode particular 30// variants of an instruction in different ways (for example, using a smaller 31// encoding for small immediates). Such ambiguities should never be 32// arbitrarily resolved by the assembler, the assembler is always responsible 33// for choosing the "best" available instruction. 34// 35// - It may depend on the subtarget or the assembler context. Instructions 36// which are invalid for the current mode, but otherwise unambiguous (e.g., 37// an SSE instruction in a file being assembled for i486) should be accepted 38// and rejected by the assembler front end. However, if the proper encoding 39// for an instruction is dependent on the assembler context then the matcher 40// is responsible for selecting the correct machine instruction for the 41// current mode. 42// 43// The core matching algorithm attempts to exploit the regularity in most 44// instruction sets to quickly determine the set of possibly matching 45// instructions, and the simplify the generated code. Additionally, this helps 46// to ensure that the ambiguities are intentionally resolved by the user. 47// 48// The matching is divided into two distinct phases: 49// 50// 1. Classification: Each operand is mapped to the unique set which (a) 51// contains it, and (b) is the largest such subset for which a single 52// instruction could match all members. 53// 54// For register classes, we can generate these subgroups automatically. For 55// arbitrary operands, we expect the user to define the classes and their 56// relations to one another (for example, 8-bit signed immediates as a 57// subset of 32-bit immediates). 58// 59// By partitioning the operands in this way, we guarantee that for any 60// tuple of classes, any single instruction must match either all or none 61// of the sets of operands which could classify to that tuple. 62// 63// In addition, the subset relation amongst classes induces a partial order 64// on such tuples, which we use to resolve ambiguities. 65// 66// 2. The input can now be treated as a tuple of classes (static tokens are 67// simple singleton sets). Each such tuple should generally map to a single 68// instruction (we currently ignore cases where this isn't true, whee!!!), 69// which we can emit a simple matcher for. 70// 71//===----------------------------------------------------------------------===// 72 73#include "AsmMatcherEmitter.h" 74#include "CodeGenTarget.h" 75#include "Record.h" 76#include "StringMatcher.h" 77#include "llvm/ADT/OwningPtr.h" 78#include "llvm/ADT/PointerUnion.h" 79#include "llvm/ADT/SmallPtrSet.h" 80#include "llvm/ADT/SmallVector.h" 81#include "llvm/ADT/STLExtras.h" 82#include "llvm/ADT/StringExtras.h" 83#include "llvm/Support/CommandLine.h" 84#include "llvm/Support/Debug.h" 85#include <map> 86#include <set> 87using namespace llvm; 88 89static cl::opt<std::string> 90MatchPrefix("match-prefix", cl::init(""), 91 cl::desc("Only match instructions with the given prefix")); 92 93 94namespace { 95 class AsmMatcherInfo; 96struct SubtargetFeatureInfo; 97 98/// ClassInfo - Helper class for storing the information about a particular 99/// class of operands which can be matched. 100struct ClassInfo { 101 enum ClassInfoKind { 102 /// Invalid kind, for use as a sentinel value. 103 Invalid = 0, 104 105 /// The class for a particular token. 106 Token, 107 108 /// The (first) register class, subsequent register classes are 109 /// RegisterClass0+1, and so on. 110 RegisterClass0, 111 112 /// The (first) user defined class, subsequent user defined classes are 113 /// UserClass0+1, and so on. 114 UserClass0 = 1<<16 115 }; 116 117 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 + 118 /// N) for the Nth user defined class. 119 unsigned Kind; 120 121 /// SuperClasses - The super classes of this class. Note that for simplicities 122 /// sake user operands only record their immediate super class, while register 123 /// operands include all superclasses. 124 std::vector<ClassInfo*> SuperClasses; 125 126 /// Name - The full class name, suitable for use in an enum. 127 std::string Name; 128 129 /// ClassName - The unadorned generic name for this class (e.g., Token). 130 std::string ClassName; 131 132 /// ValueName - The name of the value this class represents; for a token this 133 /// is the literal token string, for an operand it is the TableGen class (or 134 /// empty if this is a derived class). 135 std::string ValueName; 136 137 /// PredicateMethod - The name of the operand method to test whether the 138 /// operand matches this class; this is not valid for Token or register kinds. 139 std::string PredicateMethod; 140 141 /// RenderMethod - The name of the operand method to add this operand to an 142 /// MCInst; this is not valid for Token or register kinds. 143 std::string RenderMethod; 144 145 /// For register classes, the records for all the registers in this class. 146 std::set<Record*> Registers; 147 148public: 149 /// isRegisterClass() - Check if this is a register class. 150 bool isRegisterClass() const { 151 return Kind >= RegisterClass0 && Kind < UserClass0; 152 } 153 154 /// isUserClass() - Check if this is a user defined class. 155 bool isUserClass() const { 156 return Kind >= UserClass0; 157 } 158 159 /// isRelatedTo - Check whether this class is "related" to \arg RHS. Classes 160 /// are related if they are in the same class hierarchy. 161 bool isRelatedTo(const ClassInfo &RHS) const { 162 // Tokens are only related to tokens. 163 if (Kind == Token || RHS.Kind == Token) 164 return Kind == Token && RHS.Kind == Token; 165 166 // Registers classes are only related to registers classes, and only if 167 // their intersection is non-empty. 168 if (isRegisterClass() || RHS.isRegisterClass()) { 169 if (!isRegisterClass() || !RHS.isRegisterClass()) 170 return false; 171 172 std::set<Record*> Tmp; 173 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin()); 174 std::set_intersection(Registers.begin(), Registers.end(), 175 RHS.Registers.begin(), RHS.Registers.end(), 176 II); 177 178 return !Tmp.empty(); 179 } 180 181 // Otherwise we have two users operands; they are related if they are in the 182 // same class hierarchy. 183 // 184 // FIXME: This is an oversimplification, they should only be related if they 185 // intersect, however we don't have that information. 186 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!"); 187 const ClassInfo *Root = this; 188 while (!Root->SuperClasses.empty()) 189 Root = Root->SuperClasses.front(); 190 191 const ClassInfo *RHSRoot = &RHS; 192 while (!RHSRoot->SuperClasses.empty()) 193 RHSRoot = RHSRoot->SuperClasses.front(); 194 195 return Root == RHSRoot; 196 } 197 198 /// isSubsetOf - Test whether this class is a subset of \arg RHS; 199 bool isSubsetOf(const ClassInfo &RHS) const { 200 // This is a subset of RHS if it is the same class... 201 if (this == &RHS) 202 return true; 203 204 // ... or if any of its super classes are a subset of RHS. 205 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(), 206 ie = SuperClasses.end(); it != ie; ++it) 207 if ((*it)->isSubsetOf(RHS)) 208 return true; 209 210 return false; 211 } 212 213 /// operator< - Compare two classes. 214 bool operator<(const ClassInfo &RHS) const { 215 if (this == &RHS) 216 return false; 217 218 // Unrelated classes can be ordered by kind. 219 if (!isRelatedTo(RHS)) 220 return Kind < RHS.Kind; 221 222 switch (Kind) { 223 case Invalid: 224 assert(0 && "Invalid kind!"); 225 case Token: 226 // Tokens are comparable by value. 227 // 228 // FIXME: Compare by enum value. 229 return ValueName < RHS.ValueName; 230 231 default: 232 // This class preceeds the RHS if it is a proper subset of the RHS. 233 if (isSubsetOf(RHS)) 234 return true; 235 if (RHS.isSubsetOf(*this)) 236 return false; 237 238 // Otherwise, order by name to ensure we have a total ordering. 239 return ValueName < RHS.ValueName; 240 } 241 } 242}; 243 244/// MatchableInfo - Helper class for storing the necessary information for an 245/// instruction or alias which is capable of being matched. 246struct MatchableInfo { 247 struct AsmOperand { 248 /// Token - This is the token that the operand came from. 249 StringRef Token; 250 251 /// The unique class instance this operand should match. 252 ClassInfo *Class; 253 254 /// The operand name this is, if anything. 255 StringRef SrcOpName; 256 257 explicit AsmOperand(StringRef T) : Token(T), Class(0) {} 258 }; 259 260 /// ResOperand - This represents a single operand in the result instruction 261 /// generated by the match. In cases (like addressing modes) where a single 262 /// assembler operand expands to multiple MCOperands, this represents the 263 /// single assembler operand, not the MCOperand. 264 struct ResOperand { 265 enum { 266 /// RenderAsmOperand - This represents an operand result that is 267 /// generated by calling the render method on the assembly operand. The 268 /// corresponding AsmOperand is specified by AsmOperandNum. 269 RenderAsmOperand, 270 271 /// TiedOperand - This represents a result operand that is a duplicate of 272 /// a previous result operand. 273 TiedOperand 274 } Kind; 275 276 union { 277 /// This is the operand # in the AsmOperands list that this should be 278 /// copied from. 279 unsigned AsmOperandNum; 280 281 /// TiedOperandNum - This is the (earlier) result operand that should be 282 /// copied from. 283 unsigned TiedOperandNum; 284 }; 285 286 /// OpInfo - This is the information about the instruction operand that is 287 /// being populated. 288 const CGIOperandList::OperandInfo *OpInfo; 289 290 static ResOperand getRenderedOp(unsigned AsmOpNum, 291 const CGIOperandList::OperandInfo *Op) { 292 ResOperand X; 293 X.Kind = RenderAsmOperand; 294 X.AsmOperandNum = AsmOpNum; 295 X.OpInfo = Op; 296 return X; 297 } 298 299 static ResOperand getTiedOp(unsigned TiedOperandNum, 300 const CGIOperandList::OperandInfo *Op) { 301 ResOperand X; 302 X.Kind = TiedOperand; 303 X.TiedOperandNum = TiedOperandNum; 304 X.OpInfo = Op; 305 return X; 306 } 307 }; 308 309 /// TheDef - This is the definition of the instruction or InstAlias that this 310 /// matchable came from. 311 Record *const TheDef; 312 313 /// DefRec - This is the definition that it came from. 314 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec; 315 316 const CodeGenInstruction *getResultInst() const { 317 if (DefRec.is<const CodeGenInstruction*>()) 318 return DefRec.get<const CodeGenInstruction*>(); 319 return DefRec.get<const CodeGenInstAlias*>()->ResultInst; 320 } 321 322 /// ResOperands - This is the operand list that should be built for the result 323 /// MCInst. 324 std::vector<ResOperand> ResOperands; 325 326 /// AsmString - The assembly string for this instruction (with variants 327 /// removed), e.g. "movsx $src, $dst". 328 std::string AsmString; 329 330 /// Mnemonic - This is the first token of the matched instruction, its 331 /// mnemonic. 332 StringRef Mnemonic; 333 334 /// AsmOperands - The textual operands that this instruction matches, 335 /// annotated with a class and where in the OperandList they were defined. 336 /// This directly corresponds to the tokenized AsmString after the mnemonic is 337 /// removed. 338 SmallVector<AsmOperand, 4> AsmOperands; 339 340 /// Predicates - The required subtarget features to match this instruction. 341 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures; 342 343 /// ConversionFnKind - The enum value which is passed to the generated 344 /// ConvertToMCInst to convert parsed operands into an MCInst for this 345 /// function. 346 std::string ConversionFnKind; 347 348 MatchableInfo(const CodeGenInstruction &CGI) 349 : TheDef(CGI.TheDef), DefRec(&CGI), AsmString(CGI.AsmString) { 350 } 351 352 MatchableInfo(const CodeGenInstAlias *Alias) 353 : TheDef(Alias->TheDef), DefRec(Alias), AsmString(Alias->AsmString) { 354 } 355 356 void Initialize(const AsmMatcherInfo &Info, 357 SmallPtrSet<Record*, 16> &SingletonRegisters); 358 359 /// Validate - Return true if this matchable is a valid thing to match against 360 /// and perform a bunch of validity checking. 361 bool Validate(StringRef CommentDelimiter, bool Hack) const; 362 363 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton 364 /// register, return the Record for it, otherwise return null. 365 Record *getSingletonRegisterForAsmOperand(unsigned i, 366 const AsmMatcherInfo &Info) const; 367 368 int FindAsmOperandNamed(StringRef N) const { 369 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) 370 if (N == AsmOperands[i].SrcOpName) 371 return i; 372 return -1; 373 } 374 375 void BuildInstructionResultOperands(); 376 void BuildAliasResultOperands(); 377 378 /// operator< - Compare two matchables. 379 bool operator<(const MatchableInfo &RHS) const { 380 // The primary comparator is the instruction mnemonic. 381 if (Mnemonic != RHS.Mnemonic) 382 return Mnemonic < RHS.Mnemonic; 383 384 if (AsmOperands.size() != RHS.AsmOperands.size()) 385 return AsmOperands.size() < RHS.AsmOperands.size(); 386 387 // Compare lexicographically by operand. The matcher validates that other 388 // orderings wouldn't be ambiguous using \see CouldMatchAmiguouslyWith(). 389 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { 390 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class) 391 return true; 392 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class) 393 return false; 394 } 395 396 return false; 397 } 398 399 /// CouldMatchAmiguouslyWith - Check whether this matchable could 400 /// ambiguously match the same set of operands as \arg RHS (without being a 401 /// strictly superior match). 402 bool CouldMatchAmiguouslyWith(const MatchableInfo &RHS) { 403 // The primary comparator is the instruction mnemonic. 404 if (Mnemonic != RHS.Mnemonic) 405 return false; 406 407 // The number of operands is unambiguous. 408 if (AsmOperands.size() != RHS.AsmOperands.size()) 409 return false; 410 411 // Otherwise, make sure the ordering of the two instructions is unambiguous 412 // by checking that either (a) a token or operand kind discriminates them, 413 // or (b) the ordering among equivalent kinds is consistent. 414 415 // Tokens and operand kinds are unambiguous (assuming a correct target 416 // specific parser). 417 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) 418 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind || 419 AsmOperands[i].Class->Kind == ClassInfo::Token) 420 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class || 421 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class) 422 return false; 423 424 // Otherwise, this operand could commute if all operands are equivalent, or 425 // there is a pair of operands that compare less than and a pair that 426 // compare greater than. 427 bool HasLT = false, HasGT = false; 428 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { 429 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class) 430 HasLT = true; 431 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class) 432 HasGT = true; 433 } 434 435 return !(HasLT ^ HasGT); 436 } 437 438 void dump(); 439 440private: 441 void TokenizeAsmString(const AsmMatcherInfo &Info); 442}; 443 444/// SubtargetFeatureInfo - Helper class for storing information on a subtarget 445/// feature which participates in instruction matching. 446struct SubtargetFeatureInfo { 447 /// \brief The predicate record for this feature. 448 Record *TheDef; 449 450 /// \brief An unique index assigned to represent this feature. 451 unsigned Index; 452 453 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {} 454 455 /// \brief The name of the enumerated constant identifying this feature. 456 std::string getEnumName() const { 457 return "Feature_" + TheDef->getName(); 458 } 459}; 460 461class AsmMatcherInfo { 462public: 463 /// The tablegen AsmParser record. 464 Record *AsmParser; 465 466 /// Target - The target information. 467 CodeGenTarget &Target; 468 469 /// The AsmParser "RegisterPrefix" value. 470 std::string RegisterPrefix; 471 472 /// The classes which are needed for matching. 473 std::vector<ClassInfo*> Classes; 474 475 /// The information on the matchables to match. 476 std::vector<MatchableInfo*> Matchables; 477 478 /// Map of Register records to their class information. 479 std::map<Record*, ClassInfo*> RegisterClasses; 480 481 /// Map of Predicate records to their subtarget information. 482 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures; 483 484private: 485 /// Map of token to class information which has already been constructed. 486 std::map<std::string, ClassInfo*> TokenClasses; 487 488 /// Map of RegisterClass records to their class information. 489 std::map<Record*, ClassInfo*> RegisterClassClasses; 490 491 /// Map of AsmOperandClass records to their class information. 492 std::map<Record*, ClassInfo*> AsmOperandClasses; 493 494private: 495 /// getTokenClass - Lookup or create the class for the given token. 496 ClassInfo *getTokenClass(StringRef Token); 497 498 /// getOperandClass - Lookup or create the class for the given operand. 499 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI); 500 501 /// BuildRegisterClasses - Build the ClassInfo* instances for register 502 /// classes. 503 void BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters); 504 505 /// BuildOperandClasses - Build the ClassInfo* instances for user defined 506 /// operand classes. 507 void BuildOperandClasses(); 508 509 void BuildInstructionOperandReference(MatchableInfo *II, 510 StringRef OpName, 511 MatchableInfo::AsmOperand &Op); 512 void BuildAliasOperandReference(MatchableInfo *II, 513 StringRef OpName, 514 MatchableInfo::AsmOperand &Op); 515 516public: 517 AsmMatcherInfo(Record *AsmParser, CodeGenTarget &Target); 518 519 /// BuildInfo - Construct the various tables used during matching. 520 void BuildInfo(); 521 522 /// getSubtargetFeature - Lookup or create the subtarget feature info for the 523 /// given operand. 524 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const { 525 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!"); 526 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I = 527 SubtargetFeatures.find(Def); 528 return I == SubtargetFeatures.end() ? 0 : I->second; 529 } 530}; 531 532} 533 534void MatchableInfo::dump() { 535 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n"; 536 537 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { 538 AsmOperand &Op = AsmOperands[i]; 539 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - "; 540 errs() << '\"' << Op.Token << "\"\n"; 541#if 0 542 if (!Op.OperandInfo) { 543 errs() << "(singleton register)\n"; 544 continue; 545 } 546 547 const CGIOperandList::OperandInfo &OI = *Op.OperandInfo; 548 errs() << OI.Name << " " << OI.Rec->getName() 549 << " (" << OI.MIOperandNo << ", " << OI.MINumOperands << ")\n"; 550#endif 551 } 552} 553 554void MatchableInfo::Initialize(const AsmMatcherInfo &Info, 555 SmallPtrSet<Record*, 16> &SingletonRegisters) { 556 // TODO: Eventually support asmparser for Variant != 0. 557 AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, 0); 558 559 TokenizeAsmString(Info); 560 561 // Compute the require features. 562 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates"); 563 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) 564 if (SubtargetFeatureInfo *Feature = 565 Info.getSubtargetFeature(Predicates[i])) 566 RequiredFeatures.push_back(Feature); 567 568 // Collect singleton registers, if used. 569 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { 570 if (Record *Reg = getSingletonRegisterForAsmOperand(i, Info)) 571 SingletonRegisters.insert(Reg); 572 } 573} 574 575/// TokenizeAsmString - Tokenize a simplified assembly string. 576void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) { 577 StringRef String = AsmString; 578 unsigned Prev = 0; 579 bool InTok = true; 580 for (unsigned i = 0, e = String.size(); i != e; ++i) { 581 switch (String[i]) { 582 case '[': 583 case ']': 584 case '*': 585 case '!': 586 case ' ': 587 case '\t': 588 case ',': 589 if (InTok) { 590 AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); 591 InTok = false; 592 } 593 if (!isspace(String[i]) && String[i] != ',') 594 AsmOperands.push_back(AsmOperand(String.substr(i, 1))); 595 Prev = i + 1; 596 break; 597 598 case '\\': 599 if (InTok) { 600 AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); 601 InTok = false; 602 } 603 ++i; 604 assert(i != String.size() && "Invalid quoted character"); 605 AsmOperands.push_back(AsmOperand(String.substr(i, 1))); 606 Prev = i + 1; 607 break; 608 609 case '$': { 610 // If this isn't "${", treat like a normal token. 611 if (i + 1 == String.size() || String[i + 1] != '{') { 612 if (InTok) { 613 AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); 614 InTok = false; 615 } 616 Prev = i; 617 break; 618 } 619 620 if (InTok) { 621 AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); 622 InTok = false; 623 } 624 625 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}'); 626 assert(End != String.end() && "Missing brace in operand reference!"); 627 size_t EndPos = End - String.begin(); 628 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1))); 629 Prev = EndPos + 1; 630 i = EndPos; 631 break; 632 } 633 634 case '.': 635 if (InTok) 636 AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); 637 Prev = i; 638 InTok = true; 639 break; 640 641 default: 642 InTok = true; 643 } 644 } 645 if (InTok && Prev != String.size()) 646 AsmOperands.push_back(AsmOperand(String.substr(Prev))); 647 648 // The first token of the instruction is the mnemonic, which must be a 649 // simple string, not a $foo variable or a singleton register. 650 assert(!AsmOperands.empty() && "Instruction has no tokens?"); 651 Mnemonic = AsmOperands[0].Token; 652 if (Mnemonic[0] == '$' || getSingletonRegisterForAsmOperand(0, Info)) 653 throw TGError(TheDef->getLoc(), 654 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!"); 655 656 // Remove the first operand, it is tracked in the mnemonic field. 657 AsmOperands.erase(AsmOperands.begin()); 658} 659 660 661 662bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const { 663 // Reject matchables with no .s string. 664 if (AsmString.empty()) 665 throw TGError(TheDef->getLoc(), "instruction with empty asm string"); 666 667 // Reject any matchables with a newline in them, they should be marked 668 // isCodeGenOnly if they are pseudo instructions. 669 if (AsmString.find('\n') != std::string::npos) 670 throw TGError(TheDef->getLoc(), 671 "multiline instruction is not valid for the asmparser, " 672 "mark it isCodeGenOnly"); 673 674 // Remove comments from the asm string. We know that the asmstring only 675 // has one line. 676 if (!CommentDelimiter.empty() && 677 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos) 678 throw TGError(TheDef->getLoc(), 679 "asmstring for instruction has comment character in it, " 680 "mark it isCodeGenOnly"); 681 682 // Reject matchables with operand modifiers, these aren't something we can 683 /// handle, the target should be refactored to use operands instead of 684 /// modifiers. 685 // 686 // Also, check for instructions which reference the operand multiple times; 687 // this implies a constraint we would not honor. 688 std::set<std::string> OperandNames; 689 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { 690 StringRef Tok = AsmOperands[i].Token; 691 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos) 692 throw TGError(TheDef->getLoc(), 693 "matchable with operand modifier '" + Tok.str() + 694 "' not supported by asm matcher. Mark isCodeGenOnly!"); 695 696 // Verify that any operand is only mentioned once. 697 // We reject aliases and ignore instructions for now. 698 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) { 699 if (!Hack) 700 throw TGError(TheDef->getLoc(), 701 "ERROR: matchable with tied operand '" + Tok.str() + 702 "' can never be matched!"); 703 // FIXME: Should reject these. The ARM backend hits this with $lane in a 704 // bunch of instructions. It is unclear what the right answer is. 705 DEBUG({ 706 errs() << "warning: '" << TheDef->getName() << "': " 707 << "ignoring instruction with tied operand '" 708 << Tok.str() << "'\n"; 709 }); 710 return false; 711 } 712 } 713 714 return true; 715} 716 717 718/// getSingletonRegisterForAsmOperand - If the specified token is a singleton 719/// register, return the register name, otherwise return a null StringRef. 720Record *MatchableInfo:: 721getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const{ 722 StringRef Tok = AsmOperands[i].Token; 723 if (!Tok.startswith(Info.RegisterPrefix)) 724 return 0; 725 726 StringRef RegName = Tok.substr(Info.RegisterPrefix.size()); 727 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName)) 728 return Reg->TheDef; 729 730 // If there is no register prefix (i.e. "%" in "%eax"), then this may 731 // be some random non-register token, just ignore it. 732 if (Info.RegisterPrefix.empty()) 733 return 0; 734 735 // Otherwise, we have something invalid prefixed with the register prefix, 736 // such as %foo. 737 std::string Err = "unable to find register for '" + RegName.str() + 738 "' (which matches register prefix)"; 739 throw TGError(TheDef->getLoc(), Err); 740} 741 742 743static std::string getEnumNameForToken(StringRef Str) { 744 std::string Res; 745 746 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) { 747 switch (*it) { 748 case '*': Res += "_STAR_"; break; 749 case '%': Res += "_PCT_"; break; 750 case ':': Res += "_COLON_"; break; 751 default: 752 if (isalnum(*it)) 753 Res += *it; 754 else 755 Res += "_" + utostr((unsigned) *it) + "_"; 756 } 757 } 758 759 return Res; 760} 761 762ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) { 763 ClassInfo *&Entry = TokenClasses[Token]; 764 765 if (!Entry) { 766 Entry = new ClassInfo(); 767 Entry->Kind = ClassInfo::Token; 768 Entry->ClassName = "Token"; 769 Entry->Name = "MCK_" + getEnumNameForToken(Token); 770 Entry->ValueName = Token; 771 Entry->PredicateMethod = "<invalid>"; 772 Entry->RenderMethod = "<invalid>"; 773 Classes.push_back(Entry); 774 } 775 776 return Entry; 777} 778 779ClassInfo * 780AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI) { 781 if (OI.Rec->isSubClassOf("RegisterClass")) { 782 if (ClassInfo *CI = RegisterClassClasses[OI.Rec]) 783 return CI; 784 throw TGError(OI.Rec->getLoc(), "register class has no class info!"); 785 } 786 787 assert(OI.Rec->isSubClassOf("Operand") && "Unexpected operand!"); 788 Record *MatchClass = OI.Rec->getValueAsDef("ParserMatchClass"); 789 if (ClassInfo *CI = AsmOperandClasses[MatchClass]) 790 return CI; 791 792 throw TGError(OI.Rec->getLoc(), "operand has no match class!"); 793} 794 795void AsmMatcherInfo:: 796BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) { 797 const std::vector<CodeGenRegister> &Registers = Target.getRegisters(); 798 const std::vector<CodeGenRegisterClass> &RegClassList = 799 Target.getRegisterClasses(); 800 801 // The register sets used for matching. 802 std::set< std::set<Record*> > RegisterSets; 803 804 // Gather the defined sets. 805 for (std::vector<CodeGenRegisterClass>::const_iterator it = 806 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) 807 RegisterSets.insert(std::set<Record*>(it->Elements.begin(), 808 it->Elements.end())); 809 810 // Add any required singleton sets. 811 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(), 812 ie = SingletonRegisters.end(); it != ie; ++it) { 813 Record *Rec = *it; 814 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1)); 815 } 816 817 // Introduce derived sets where necessary (when a register does not determine 818 // a unique register set class), and build the mapping of registers to the set 819 // they should classify to. 820 std::map<Record*, std::set<Record*> > RegisterMap; 821 for (std::vector<CodeGenRegister>::const_iterator it = Registers.begin(), 822 ie = Registers.end(); it != ie; ++it) { 823 const CodeGenRegister &CGR = *it; 824 // Compute the intersection of all sets containing this register. 825 std::set<Record*> ContainingSet; 826 827 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(), 828 ie = RegisterSets.end(); it != ie; ++it) { 829 if (!it->count(CGR.TheDef)) 830 continue; 831 832 if (ContainingSet.empty()) { 833 ContainingSet = *it; 834 continue; 835 } 836 837 std::set<Record*> Tmp; 838 std::swap(Tmp, ContainingSet); 839 std::insert_iterator< std::set<Record*> > II(ContainingSet, 840 ContainingSet.begin()); 841 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II); 842 } 843 844 if (!ContainingSet.empty()) { 845 RegisterSets.insert(ContainingSet); 846 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet)); 847 } 848 } 849 850 // Construct the register classes. 851 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses; 852 unsigned Index = 0; 853 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(), 854 ie = RegisterSets.end(); it != ie; ++it, ++Index) { 855 ClassInfo *CI = new ClassInfo(); 856 CI->Kind = ClassInfo::RegisterClass0 + Index; 857 CI->ClassName = "Reg" + utostr(Index); 858 CI->Name = "MCK_Reg" + utostr(Index); 859 CI->ValueName = ""; 860 CI->PredicateMethod = ""; // unused 861 CI->RenderMethod = "addRegOperands"; 862 CI->Registers = *it; 863 Classes.push_back(CI); 864 RegisterSetClasses.insert(std::make_pair(*it, CI)); 865 } 866 867 // Find the superclasses; we could compute only the subgroup lattice edges, 868 // but there isn't really a point. 869 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(), 870 ie = RegisterSets.end(); it != ie; ++it) { 871 ClassInfo *CI = RegisterSetClasses[*it]; 872 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(), 873 ie2 = RegisterSets.end(); it2 != ie2; ++it2) 874 if (*it != *it2 && 875 std::includes(it2->begin(), it2->end(), it->begin(), it->end())) 876 CI->SuperClasses.push_back(RegisterSetClasses[*it2]); 877 } 878 879 // Name the register classes which correspond to a user defined RegisterClass. 880 for (std::vector<CodeGenRegisterClass>::const_iterator 881 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) { 882 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(it->Elements.begin(), 883 it->Elements.end())]; 884 if (CI->ValueName.empty()) { 885 CI->ClassName = it->getName(); 886 CI->Name = "MCK_" + it->getName(); 887 CI->ValueName = it->getName(); 888 } else 889 CI->ValueName = CI->ValueName + "," + it->getName(); 890 891 RegisterClassClasses.insert(std::make_pair(it->TheDef, CI)); 892 } 893 894 // Populate the map for individual registers. 895 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(), 896 ie = RegisterMap.end(); it != ie; ++it) 897 RegisterClasses[it->first] = RegisterSetClasses[it->second]; 898 899 // Name the register classes which correspond to singleton registers. 900 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(), 901 ie = SingletonRegisters.end(); it != ie; ++it) { 902 Record *Rec = *it; 903 ClassInfo *CI = RegisterClasses[Rec]; 904 assert(CI && "Missing singleton register class info!"); 905 906 if (CI->ValueName.empty()) { 907 CI->ClassName = Rec->getName(); 908 CI->Name = "MCK_" + Rec->getName(); 909 CI->ValueName = Rec->getName(); 910 } else 911 CI->ValueName = CI->ValueName + "," + Rec->getName(); 912 } 913} 914 915void AsmMatcherInfo::BuildOperandClasses() { 916 std::vector<Record*> AsmOperands = 917 Records.getAllDerivedDefinitions("AsmOperandClass"); 918 919 // Pre-populate AsmOperandClasses map. 920 for (std::vector<Record*>::iterator it = AsmOperands.begin(), 921 ie = AsmOperands.end(); it != ie; ++it) 922 AsmOperandClasses[*it] = new ClassInfo(); 923 924 unsigned Index = 0; 925 for (std::vector<Record*>::iterator it = AsmOperands.begin(), 926 ie = AsmOperands.end(); it != ie; ++it, ++Index) { 927 ClassInfo *CI = AsmOperandClasses[*it]; 928 CI->Kind = ClassInfo::UserClass0 + Index; 929 930 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses"); 931 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) { 932 DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i)); 933 if (!DI) { 934 PrintError((*it)->getLoc(), "Invalid super class reference!"); 935 continue; 936 } 937 938 ClassInfo *SC = AsmOperandClasses[DI->getDef()]; 939 if (!SC) 940 PrintError((*it)->getLoc(), "Invalid super class reference!"); 941 else 942 CI->SuperClasses.push_back(SC); 943 } 944 CI->ClassName = (*it)->getValueAsString("Name"); 945 CI->Name = "MCK_" + CI->ClassName; 946 CI->ValueName = (*it)->getName(); 947 948 // Get or construct the predicate method name. 949 Init *PMName = (*it)->getValueInit("PredicateMethod"); 950 if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) { 951 CI->PredicateMethod = SI->getValue(); 952 } else { 953 assert(dynamic_cast<UnsetInit*>(PMName) && 954 "Unexpected PredicateMethod field!"); 955 CI->PredicateMethod = "is" + CI->ClassName; 956 } 957 958 // Get or construct the render method name. 959 Init *RMName = (*it)->getValueInit("RenderMethod"); 960 if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) { 961 CI->RenderMethod = SI->getValue(); 962 } else { 963 assert(dynamic_cast<UnsetInit*>(RMName) && 964 "Unexpected RenderMethod field!"); 965 CI->RenderMethod = "add" + CI->ClassName + "Operands"; 966 } 967 968 AsmOperandClasses[*it] = CI; 969 Classes.push_back(CI); 970 } 971} 972 973AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, CodeGenTarget &target) 974 : AsmParser(asmParser), Target(target), 975 RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")) { 976} 977 978 979void AsmMatcherInfo::BuildInfo() { 980 // Build information about all of the AssemblerPredicates. 981 std::vector<Record*> AllPredicates = 982 Records.getAllDerivedDefinitions("Predicate"); 983 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) { 984 Record *Pred = AllPredicates[i]; 985 // Ignore predicates that are not intended for the assembler. 986 if (!Pred->getValueAsBit("AssemblerMatcherPredicate")) 987 continue; 988 989 if (Pred->getName().empty()) 990 throw TGError(Pred->getLoc(), "Predicate has no name!"); 991 992 unsigned FeatureNo = SubtargetFeatures.size(); 993 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo); 994 assert(FeatureNo < 32 && "Too many subtarget features!"); 995 } 996 997 StringRef CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter"); 998 999 // Parse the instructions; we need to do this first so that we can gather the 1000 // singleton register classes. 1001 SmallPtrSet<Record*, 16> SingletonRegisters; 1002 for (CodeGenTarget::inst_iterator I = Target.inst_begin(), 1003 E = Target.inst_end(); I != E; ++I) { 1004 const CodeGenInstruction &CGI = **I; 1005 1006 // If the tblgen -match-prefix option is specified (for tblgen hackers), 1007 // filter the set of instructions we consider. 1008 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix)) 1009 continue; 1010 1011 // Ignore "codegen only" instructions. 1012 if (CGI.TheDef->getValueAsBit("isCodeGenOnly")) 1013 continue; 1014 1015 // Validate the operand list to ensure we can handle this instruction. 1016 for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) { 1017 const CGIOperandList::OperandInfo &OI = CGI.Operands[i]; 1018 1019 // Validate tied operands. 1020 if (OI.getTiedRegister() != -1) { 1021 // If we have a tied operand that consists of multiple MCOperands, reject 1022 // it. We reject aliases and ignore instructions for now. 1023 if (OI.MINumOperands != 1) { 1024 // FIXME: Should reject these. The ARM backend hits this with $lane 1025 // in a bunch of instructions. It is unclear what the right answer is. 1026 DEBUG({ 1027 errs() << "warning: '" << CGI.TheDef->getName() << "': " 1028 << "ignoring instruction with multi-operand tied operand '" 1029 << OI.Name << "'\n"; 1030 }); 1031 continue; 1032 } 1033 } 1034 } 1035 1036 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI)); 1037 1038 II->Initialize(*this, SingletonRegisters); 1039 1040 // Ignore instructions which shouldn't be matched and diagnose invalid 1041 // instruction definitions with an error. 1042 if (!II->Validate(CommentDelimiter, true)) 1043 continue; 1044 1045 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases. 1046 // 1047 // FIXME: This is a total hack. 1048 if (StringRef(II->TheDef->getName()).startswith("Int_") || 1049 StringRef(II->TheDef->getName()).endswith("_Int")) 1050 continue; 1051 1052 Matchables.push_back(II.take()); 1053 } 1054 1055 // Parse all of the InstAlias definitions and stick them in the list of 1056 // matchables. 1057 std::vector<Record*> AllInstAliases = 1058 Records.getAllDerivedDefinitions("InstAlias"); 1059 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) { 1060 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target); 1061 1062 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias)); 1063 1064 II->Initialize(*this, SingletonRegisters); 1065 1066 // Validate the alias definitions. 1067 II->Validate(CommentDelimiter, false); 1068 1069 Matchables.push_back(II.take()); 1070 } 1071 1072 // Build info for the register classes. 1073 BuildRegisterClasses(SingletonRegisters); 1074 1075 // Build info for the user defined assembly operand classes. 1076 BuildOperandClasses(); 1077 1078 // Build the information about matchables, now that we have fully formed 1079 // classes. 1080 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(), 1081 ie = Matchables.end(); it != ie; ++it) { 1082 MatchableInfo *II = *it; 1083 1084 // Parse the tokens after the mnemonic. 1085 for (unsigned i = 0, e = II->AsmOperands.size(); i != e; ++i) { 1086 MatchableInfo::AsmOperand &Op = II->AsmOperands[i]; 1087 StringRef Token = Op.Token; 1088 1089 // Check for singleton registers. 1090 if (Record *RegRecord = II->getSingletonRegisterForAsmOperand(i, *this)) { 1091 Op.Class = RegisterClasses[RegRecord]; 1092 assert(Op.Class && Op.Class->Registers.size() == 1 && 1093 "Unexpected class for singleton register"); 1094 continue; 1095 } 1096 1097 // Check for simple tokens. 1098 if (Token[0] != '$') { 1099 Op.Class = getTokenClass(Token); 1100 continue; 1101 } 1102 1103 // Otherwise this is an operand reference. 1104 StringRef OperandName; 1105 if (Token[1] == '{') 1106 OperandName = Token.substr(2, Token.size() - 3); 1107 else 1108 OperandName = Token.substr(1); 1109 1110 if (II->DefRec.is<const CodeGenInstruction*>()) 1111 BuildInstructionOperandReference(II, OperandName, Op); 1112 else 1113 BuildAliasOperandReference(II, OperandName, Op); 1114 } 1115 1116 if (II->DefRec.is<const CodeGenInstruction*>()) 1117 II->BuildInstructionResultOperands(); 1118 else 1119 II->BuildAliasResultOperands(); 1120 } 1121 1122 // Reorder classes so that classes preceed super classes. 1123 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>()); 1124} 1125 1126/// BuildInstructionOperandReference - The specified operand is a reference to a 1127/// named operand such as $src. Resolve the Class and OperandInfo pointers. 1128void AsmMatcherInfo:: 1129BuildInstructionOperandReference(MatchableInfo *II, 1130 StringRef OperandName, 1131 MatchableInfo::AsmOperand &Op) { 1132 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>(); 1133 const CGIOperandList &Operands = CGI.Operands; 1134 1135 // Map this token to an operand. 1136 unsigned Idx; 1137 if (!Operands.hasOperandNamed(OperandName, Idx)) 1138 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" + 1139 OperandName.str() + "'"); 1140 1141 // Set up the operand class. 1142 Op.Class = getOperandClass(Operands[Idx]); 1143 1144 // If the named operand is tied, canonicalize it to the untied operand. 1145 // For example, something like: 1146 // (outs GPR:$dst), (ins GPR:$src) 1147 // with an asmstring of 1148 // "inc $src" 1149 // we want to canonicalize to: 1150 // "inc $dst" 1151 // so that we know how to provide the $dst operand when filling in the result. 1152 int OITied = Operands[Idx].getTiedRegister(); 1153 if (OITied != -1) { 1154 // The tied operand index is an MIOperand index, find the operand that 1155 // contains it. 1156 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 1157 if (Operands[i].MIOperandNo == unsigned(OITied)) { 1158 OperandName = Operands[i].Name; 1159 break; 1160 } 1161 } 1162 } 1163 1164 Op.SrcOpName = OperandName; 1165} 1166 1167/// BuildAliasOperandReference - When parsing an operand reference out of the 1168/// matching string (e.g. "movsx $src, $dst"), determine what the class of the 1169/// operand reference is by looking it up in the result pattern definition. 1170void AsmMatcherInfo::BuildAliasOperandReference(MatchableInfo *II, 1171 StringRef OperandName, 1172 MatchableInfo::AsmOperand &Op) { 1173 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>(); 1174 1175 // Set up the operand class. 1176 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i) 1177 if (CGA.ResultOperands[i].Name == OperandName) { 1178 // It's safe to go with the first one we find, because CodeGenInstAlias 1179 // validates that all operands with the same name have the same record. 1180 Op.Class = getOperandClass(CGA.ResultInst->Operands[i]); 1181 Op.SrcOpName = OperandName; 1182 return; 1183 } 1184 1185 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" + 1186 OperandName.str() + "'"); 1187} 1188 1189void MatchableInfo::BuildInstructionResultOperands() { 1190 const CodeGenInstruction *ResultInst = getResultInst(); 1191 1192 // Loop over all operands of the result instruction, determining how to 1193 // populate them. 1194 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) { 1195 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i]; 1196 1197 // If this is a tied operand, just copy from the previously handled operand. 1198 int TiedOp = OpInfo.getTiedRegister(); 1199 if (TiedOp != -1) { 1200 ResOperands.push_back(ResOperand::getTiedOp(TiedOp, &OpInfo)); 1201 continue; 1202 } 1203 1204 // Find out what operand from the asmparser that this MCInst operand comes 1205 // from. 1206 int SrcOperand = FindAsmOperandNamed(OpInfo.Name); 1207 1208 if (!OpInfo.Name.empty() && SrcOperand != -1) { 1209 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, &OpInfo)); 1210 continue; 1211 } 1212 1213 throw TGError(TheDef->getLoc(), "Instruction '" + 1214 TheDef->getName() + "' has operand '" + OpInfo.Name + 1215 "' that doesn't appear in asm string!"); 1216 } 1217} 1218 1219void MatchableInfo::BuildAliasResultOperands() { 1220 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>(); 1221 const CodeGenInstruction *ResultInst = getResultInst(); 1222 1223 // Loop over all operands of the result instruction, determining how to 1224 // populate them. 1225 unsigned AliasOpNo = 0; 1226 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) { 1227 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i]; 1228 1229 // If this is a tied operand, just copy from the previously handled operand. 1230 int TiedOp = OpInfo.getTiedRegister(); 1231 if (TiedOp != -1) { 1232 ResOperands.push_back(ResOperand::getTiedOp(TiedOp, &OpInfo)); 1233 continue; 1234 } 1235 1236 // Find out what operand from the asmparser that this MCInst operand comes 1237 // from. 1238 int SrcOperand = FindAsmOperandNamed(CGA.ResultOperands[AliasOpNo++].Name); 1239 if (SrcOperand != -1) { 1240 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, &OpInfo)); 1241 continue; 1242 } 1243 1244 throw TGError(TheDef->getLoc(), "Instruction '" + 1245 TheDef->getName() + "' has operand '" + OpInfo.Name + 1246 "' that doesn't appear in asm string!"); 1247 } 1248} 1249 1250static void EmitConvertToMCInst(CodeGenTarget &Target, 1251 std::vector<MatchableInfo*> &Infos, 1252 raw_ostream &OS) { 1253 // Write the convert function to a separate stream, so we can drop it after 1254 // the enum. 1255 std::string ConvertFnBody; 1256 raw_string_ostream CvtOS(ConvertFnBody); 1257 1258 // Function we have already generated. 1259 std::set<std::string> GeneratedFns; 1260 1261 // Start the unified conversion function. 1262 CvtOS << "static void ConvertToMCInst(ConversionKind Kind, MCInst &Inst, " 1263 << "unsigned Opcode,\n" 1264 << " const SmallVectorImpl<MCParsedAsmOperand*" 1265 << "> &Operands) {\n"; 1266 CvtOS << " Inst.setOpcode(Opcode);\n"; 1267 CvtOS << " switch (Kind) {\n"; 1268 CvtOS << " default:\n"; 1269 1270 // Start the enum, which we will generate inline. 1271 1272 OS << "// Unified function for converting operands to MCInst instances.\n\n"; 1273 OS << "enum ConversionKind {\n"; 1274 1275 // TargetOperandClass - This is the target's operand class, like X86Operand. 1276 std::string TargetOperandClass = Target.getName() + "Operand"; 1277 1278 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(), 1279 ie = Infos.end(); it != ie; ++it) { 1280 MatchableInfo &II = **it; 1281 1282 // Build the conversion function signature. 1283 std::string Signature = "Convert"; 1284 std::string CaseBody; 1285 raw_string_ostream CaseOS(CaseBody); 1286 1287 // Compute the convert enum and the case body. 1288 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) { 1289 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i]; 1290 1291 // Generate code to populate each result operand. 1292 switch (OpInfo.Kind) { 1293 default: assert(0 && "Unknown result operand kind"); 1294 case MatchableInfo::ResOperand::RenderAsmOperand: { 1295 // This comes from something we parsed. 1296 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum]; 1297 1298 // Registers are always converted the same, don't duplicate the 1299 // conversion function based on them. 1300 Signature += "__"; 1301 if (Op.Class->isRegisterClass()) 1302 Signature += "Reg"; 1303 else 1304 Signature += Op.Class->ClassName; 1305 Signature += utostr(OpInfo.OpInfo->MINumOperands); 1306 Signature += "_" + itostr(OpInfo.AsmOperandNum); 1307 1308 CaseOS << " ((" << TargetOperandClass << "*)Operands[" 1309 << (OpInfo.AsmOperandNum+1) << "])->" << Op.Class->RenderMethod 1310 << "(Inst, " << OpInfo.OpInfo->MINumOperands << ");\n"; 1311 break; 1312 } 1313 1314 case MatchableInfo::ResOperand::TiedOperand: { 1315 // If this operand is tied to a previous one, just copy the MCInst 1316 // operand from the earlier one.We can only tie single MCOperand values. 1317 //assert(OpInfo.OpInfo->MINumOperands == 1 && "Not a singular MCOperand"); 1318 unsigned TiedOp = OpInfo.TiedOperandNum; 1319 assert(i > TiedOp && "Tied operand preceeds its target!"); 1320 CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n"; 1321 Signature += "__Tie" + utostr(TiedOp); 1322 break; 1323 } 1324 } 1325 } 1326 1327 II.ConversionFnKind = Signature; 1328 1329 // Check if we have already generated this signature. 1330 if (!GeneratedFns.insert(Signature).second) 1331 continue; 1332 1333 // If not, emit it now. Add to the enum list. 1334 OS << " " << Signature << ",\n"; 1335 1336 CvtOS << " case " << Signature << ":\n"; 1337 CvtOS << CaseOS.str(); 1338 CvtOS << " return;\n"; 1339 } 1340 1341 // Finish the convert function. 1342 1343 CvtOS << " }\n"; 1344 CvtOS << "}\n\n"; 1345 1346 // Finish the enum, and drop the convert function after it. 1347 1348 OS << " NumConversionVariants\n"; 1349 OS << "};\n\n"; 1350 1351 OS << CvtOS.str(); 1352} 1353 1354/// EmitMatchClassEnumeration - Emit the enumeration for match class kinds. 1355static void EmitMatchClassEnumeration(CodeGenTarget &Target, 1356 std::vector<ClassInfo*> &Infos, 1357 raw_ostream &OS) { 1358 OS << "namespace {\n\n"; 1359 1360 OS << "/// MatchClassKind - The kinds of classes which participate in\n" 1361 << "/// instruction matching.\n"; 1362 OS << "enum MatchClassKind {\n"; 1363 OS << " InvalidMatchClass = 0,\n"; 1364 for (std::vector<ClassInfo*>::iterator it = Infos.begin(), 1365 ie = Infos.end(); it != ie; ++it) { 1366 ClassInfo &CI = **it; 1367 OS << " " << CI.Name << ", // "; 1368 if (CI.Kind == ClassInfo::Token) { 1369 OS << "'" << CI.ValueName << "'\n"; 1370 } else if (CI.isRegisterClass()) { 1371 if (!CI.ValueName.empty()) 1372 OS << "register class '" << CI.ValueName << "'\n"; 1373 else 1374 OS << "derived register class\n"; 1375 } else { 1376 OS << "user defined class '" << CI.ValueName << "'\n"; 1377 } 1378 } 1379 OS << " NumMatchClassKinds\n"; 1380 OS << "};\n\n"; 1381 1382 OS << "}\n\n"; 1383} 1384 1385/// EmitClassifyOperand - Emit the function to classify an operand. 1386static void EmitClassifyOperand(AsmMatcherInfo &Info, 1387 raw_ostream &OS) { 1388 OS << "static MatchClassKind ClassifyOperand(MCParsedAsmOperand *GOp) {\n" 1389 << " " << Info.Target.getName() << "Operand &Operand = *(" 1390 << Info.Target.getName() << "Operand*)GOp;\n"; 1391 1392 // Classify tokens. 1393 OS << " if (Operand.isToken())\n"; 1394 OS << " return MatchTokenString(Operand.getToken());\n\n"; 1395 1396 // Classify registers. 1397 // 1398 // FIXME: Don't hardcode isReg, getReg. 1399 OS << " if (Operand.isReg()) {\n"; 1400 OS << " switch (Operand.getReg()) {\n"; 1401 OS << " default: return InvalidMatchClass;\n"; 1402 for (std::map<Record*, ClassInfo*>::iterator 1403 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end(); 1404 it != ie; ++it) 1405 OS << " case " << Info.Target.getName() << "::" 1406 << it->first->getName() << ": return " << it->second->Name << ";\n"; 1407 OS << " }\n"; 1408 OS << " }\n\n"; 1409 1410 // Classify user defined operands. 1411 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(), 1412 ie = Info.Classes.end(); it != ie; ++it) { 1413 ClassInfo &CI = **it; 1414 1415 if (!CI.isUserClass()) 1416 continue; 1417 1418 OS << " // '" << CI.ClassName << "' class"; 1419 if (!CI.SuperClasses.empty()) { 1420 OS << ", subclass of "; 1421 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i) { 1422 if (i) OS << ", "; 1423 OS << "'" << CI.SuperClasses[i]->ClassName << "'"; 1424 assert(CI < *CI.SuperClasses[i] && "Invalid class relation!"); 1425 } 1426 } 1427 OS << "\n"; 1428 1429 OS << " if (Operand." << CI.PredicateMethod << "()) {\n"; 1430 1431 // Validate subclass relationships. 1432 if (!CI.SuperClasses.empty()) { 1433 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i) 1434 OS << " assert(Operand." << CI.SuperClasses[i]->PredicateMethod 1435 << "() && \"Invalid class relationship!\");\n"; 1436 } 1437 1438 OS << " return " << CI.Name << ";\n"; 1439 OS << " }\n\n"; 1440 } 1441 OS << " return InvalidMatchClass;\n"; 1442 OS << "}\n\n"; 1443} 1444 1445/// EmitIsSubclass - Emit the subclass predicate function. 1446static void EmitIsSubclass(CodeGenTarget &Target, 1447 std::vector<ClassInfo*> &Infos, 1448 raw_ostream &OS) { 1449 OS << "/// IsSubclass - Compute whether \\arg A is a subclass of \\arg B.\n"; 1450 OS << "static bool IsSubclass(MatchClassKind A, MatchClassKind B) {\n"; 1451 OS << " if (A == B)\n"; 1452 OS << " return true;\n\n"; 1453 1454 OS << " switch (A) {\n"; 1455 OS << " default:\n"; 1456 OS << " return false;\n"; 1457 for (std::vector<ClassInfo*>::iterator it = Infos.begin(), 1458 ie = Infos.end(); it != ie; ++it) { 1459 ClassInfo &A = **it; 1460 1461 if (A.Kind != ClassInfo::Token) { 1462 std::vector<StringRef> SuperClasses; 1463 for (std::vector<ClassInfo*>::iterator it = Infos.begin(), 1464 ie = Infos.end(); it != ie; ++it) { 1465 ClassInfo &B = **it; 1466 1467 if (&A != &B && A.isSubsetOf(B)) 1468 SuperClasses.push_back(B.Name); 1469 } 1470 1471 if (SuperClasses.empty()) 1472 continue; 1473 1474 OS << "\n case " << A.Name << ":\n"; 1475 1476 if (SuperClasses.size() == 1) { 1477 OS << " return B == " << SuperClasses.back() << ";\n"; 1478 continue; 1479 } 1480 1481 OS << " switch (B) {\n"; 1482 OS << " default: return false;\n"; 1483 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i) 1484 OS << " case " << SuperClasses[i] << ": return true;\n"; 1485 OS << " }\n"; 1486 } 1487 } 1488 OS << " }\n"; 1489 OS << "}\n\n"; 1490} 1491 1492 1493 1494/// EmitMatchTokenString - Emit the function to match a token string to the 1495/// appropriate match class value. 1496static void EmitMatchTokenString(CodeGenTarget &Target, 1497 std::vector<ClassInfo*> &Infos, 1498 raw_ostream &OS) { 1499 // Construct the match list. 1500 std::vector<StringMatcher::StringPair> Matches; 1501 for (std::vector<ClassInfo*>::iterator it = Infos.begin(), 1502 ie = Infos.end(); it != ie; ++it) { 1503 ClassInfo &CI = **it; 1504 1505 if (CI.Kind == ClassInfo::Token) 1506 Matches.push_back(StringMatcher::StringPair(CI.ValueName, 1507 "return " + CI.Name + ";")); 1508 } 1509 1510 OS << "static MatchClassKind MatchTokenString(StringRef Name) {\n"; 1511 1512 StringMatcher("Name", Matches, OS).Emit(); 1513 1514 OS << " return InvalidMatchClass;\n"; 1515 OS << "}\n\n"; 1516} 1517 1518/// EmitMatchRegisterName - Emit the function to match a string to the target 1519/// specific register enum. 1520static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser, 1521 raw_ostream &OS) { 1522 // Construct the match list. 1523 std::vector<StringMatcher::StringPair> Matches; 1524 for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) { 1525 const CodeGenRegister &Reg = Target.getRegisters()[i]; 1526 if (Reg.TheDef->getValueAsString("AsmName").empty()) 1527 continue; 1528 1529 Matches.push_back(StringMatcher::StringPair( 1530 Reg.TheDef->getValueAsString("AsmName"), 1531 "return " + utostr(i + 1) + ";")); 1532 } 1533 1534 OS << "static unsigned MatchRegisterName(StringRef Name) {\n"; 1535 1536 StringMatcher("Name", Matches, OS).Emit(); 1537 1538 OS << " return 0;\n"; 1539 OS << "}\n\n"; 1540} 1541 1542/// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag 1543/// definitions. 1544static void EmitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info, 1545 raw_ostream &OS) { 1546 OS << "// Flags for subtarget features that participate in " 1547 << "instruction matching.\n"; 1548 OS << "enum SubtargetFeatureFlag {\n"; 1549 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator 1550 it = Info.SubtargetFeatures.begin(), 1551 ie = Info.SubtargetFeatures.end(); it != ie; ++it) { 1552 SubtargetFeatureInfo &SFI = *it->second; 1553 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n"; 1554 } 1555 OS << " Feature_None = 0\n"; 1556 OS << "};\n\n"; 1557} 1558 1559/// EmitComputeAvailableFeatures - Emit the function to compute the list of 1560/// available features given a subtarget. 1561static void EmitComputeAvailableFeatures(AsmMatcherInfo &Info, 1562 raw_ostream &OS) { 1563 std::string ClassName = 1564 Info.AsmParser->getValueAsString("AsmParserClassName"); 1565 1566 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n" 1567 << "ComputeAvailableFeatures(const " << Info.Target.getName() 1568 << "Subtarget *Subtarget) const {\n"; 1569 OS << " unsigned Features = 0;\n"; 1570 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator 1571 it = Info.SubtargetFeatures.begin(), 1572 ie = Info.SubtargetFeatures.end(); it != ie; ++it) { 1573 SubtargetFeatureInfo &SFI = *it->second; 1574 OS << " if (" << SFI.TheDef->getValueAsString("CondString") 1575 << ")\n"; 1576 OS << " Features |= " << SFI.getEnumName() << ";\n"; 1577 } 1578 OS << " return Features;\n"; 1579 OS << "}\n\n"; 1580} 1581 1582static std::string GetAliasRequiredFeatures(Record *R, 1583 const AsmMatcherInfo &Info) { 1584 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates"); 1585 std::string Result; 1586 unsigned NumFeatures = 0; 1587 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) { 1588 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]); 1589 1590 if (F == 0) 1591 throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() + 1592 "' is not marked as an AssemblerPredicate!"); 1593 1594 if (NumFeatures) 1595 Result += '|'; 1596 1597 Result += F->getEnumName(); 1598 ++NumFeatures; 1599 } 1600 1601 if (NumFeatures > 1) 1602 Result = '(' + Result + ')'; 1603 return Result; 1604} 1605 1606/// EmitMnemonicAliases - If the target has any MnemonicAlias<> definitions, 1607/// emit a function for them and return true, otherwise return false. 1608static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) { 1609 std::vector<Record*> Aliases = 1610 Records.getAllDerivedDefinitions("MnemonicAlias"); 1611 if (Aliases.empty()) return false; 1612 1613 OS << "static void ApplyMnemonicAliases(StringRef &Mnemonic, " 1614 "unsigned Features) {\n"; 1615 1616 // Keep track of all the aliases from a mnemonic. Use an std::map so that the 1617 // iteration order of the map is stable. 1618 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic; 1619 1620 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) { 1621 Record *R = Aliases[i]; 1622 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R); 1623 } 1624 1625 // Process each alias a "from" mnemonic at a time, building the code executed 1626 // by the string remapper. 1627 std::vector<StringMatcher::StringPair> Cases; 1628 for (std::map<std::string, std::vector<Record*> >::iterator 1629 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end(); 1630 I != E; ++I) { 1631 const std::vector<Record*> &ToVec = I->second; 1632 1633 // Loop through each alias and emit code that handles each case. If there 1634 // are two instructions without predicates, emit an error. If there is one, 1635 // emit it last. 1636 std::string MatchCode; 1637 int AliasWithNoPredicate = -1; 1638 1639 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) { 1640 Record *R = ToVec[i]; 1641 std::string FeatureMask = GetAliasRequiredFeatures(R, Info); 1642 1643 // If this unconditionally matches, remember it for later and diagnose 1644 // duplicates. 1645 if (FeatureMask.empty()) { 1646 if (AliasWithNoPredicate != -1) { 1647 // We can't have two aliases from the same mnemonic with no predicate. 1648 PrintError(ToVec[AliasWithNoPredicate]->getLoc(), 1649 "two MnemonicAliases with the same 'from' mnemonic!"); 1650 throw TGError(R->getLoc(), "this is the other MnemonicAlias."); 1651 } 1652 1653 AliasWithNoPredicate = i; 1654 continue; 1655 } 1656 1657 if (!MatchCode.empty()) 1658 MatchCode += "else "; 1659 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n"; 1660 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n"; 1661 } 1662 1663 if (AliasWithNoPredicate != -1) { 1664 Record *R = ToVec[AliasWithNoPredicate]; 1665 if (!MatchCode.empty()) 1666 MatchCode += "else\n "; 1667 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n"; 1668 } 1669 1670 MatchCode += "return;"; 1671 1672 Cases.push_back(std::make_pair(I->first, MatchCode)); 1673 } 1674 1675 1676 StringMatcher("Mnemonic", Cases, OS).Emit(); 1677 OS << "}\n"; 1678 1679 return true; 1680} 1681 1682void AsmMatcherEmitter::run(raw_ostream &OS) { 1683 CodeGenTarget Target; 1684 Record *AsmParser = Target.getAsmParser(); 1685 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName"); 1686 1687 // Compute the information on the instructions to match. 1688 AsmMatcherInfo Info(AsmParser, Target); 1689 Info.BuildInfo(); 1690 1691 // Sort the instruction table using the partial order on classes. We use 1692 // stable_sort to ensure that ambiguous instructions are still 1693 // deterministically ordered. 1694 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(), 1695 less_ptr<MatchableInfo>()); 1696 1697 DEBUG_WITH_TYPE("instruction_info", { 1698 for (std::vector<MatchableInfo*>::iterator 1699 it = Info.Matchables.begin(), ie = Info.Matchables.end(); 1700 it != ie; ++it) 1701 (*it)->dump(); 1702 }); 1703 1704 // Check for ambiguous matchables. 1705 DEBUG_WITH_TYPE("ambiguous_instrs", { 1706 unsigned NumAmbiguous = 0; 1707 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) { 1708 for (unsigned j = i + 1; j != e; ++j) { 1709 MatchableInfo &A = *Info.Matchables[i]; 1710 MatchableInfo &B = *Info.Matchables[j]; 1711 1712 if (A.CouldMatchAmiguouslyWith(B)) { 1713 errs() << "warning: ambiguous matchables:\n"; 1714 A.dump(); 1715 errs() << "\nis incomparable with:\n"; 1716 B.dump(); 1717 errs() << "\n\n"; 1718 ++NumAmbiguous; 1719 } 1720 } 1721 } 1722 if (NumAmbiguous) 1723 errs() << "warning: " << NumAmbiguous 1724 << " ambiguous matchables!\n"; 1725 }); 1726 1727 // Write the output. 1728 1729 EmitSourceFileHeader("Assembly Matcher Source Fragment", OS); 1730 1731 // Information for the class declaration. 1732 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n"; 1733 OS << "#undef GET_ASSEMBLER_HEADER\n"; 1734 OS << " // This should be included into the middle of the declaration of \n"; 1735 OS << " // your subclasses implementation of TargetAsmParser.\n"; 1736 OS << " unsigned ComputeAvailableFeatures(const " << 1737 Target.getName() << "Subtarget *Subtarget) const;\n"; 1738 OS << " enum MatchResultTy {\n"; 1739 OS << " Match_Success, Match_MnemonicFail, Match_InvalidOperand,\n"; 1740 OS << " Match_MissingFeature\n"; 1741 OS << " };\n"; 1742 OS << " MatchResultTy MatchInstructionImpl(const " 1743 << "SmallVectorImpl<MCParsedAsmOperand*>" 1744 << " &Operands, MCInst &Inst, unsigned &ErrorInfo);\n\n"; 1745 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n"; 1746 1747 1748 1749 1750 OS << "\n#ifdef GET_REGISTER_MATCHER\n"; 1751 OS << "#undef GET_REGISTER_MATCHER\n\n"; 1752 1753 // Emit the subtarget feature enumeration. 1754 EmitSubtargetFeatureFlagEnumeration(Info, OS); 1755 1756 // Emit the function to match a register name to number. 1757 EmitMatchRegisterName(Target, AsmParser, OS); 1758 1759 OS << "#endif // GET_REGISTER_MATCHER\n\n"; 1760 1761 1762 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n"; 1763 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n"; 1764 1765 // Generate the function that remaps for mnemonic aliases. 1766 bool HasMnemonicAliases = EmitMnemonicAliases(OS, Info); 1767 1768 // Generate the unified function to convert operands into an MCInst. 1769 EmitConvertToMCInst(Target, Info.Matchables, OS); 1770 1771 // Emit the enumeration for classes which participate in matching. 1772 EmitMatchClassEnumeration(Target, Info.Classes, OS); 1773 1774 // Emit the routine to match token strings to their match class. 1775 EmitMatchTokenString(Target, Info.Classes, OS); 1776 1777 // Emit the routine to classify an operand. 1778 EmitClassifyOperand(Info, OS); 1779 1780 // Emit the subclass predicate routine. 1781 EmitIsSubclass(Target, Info.Classes, OS); 1782 1783 // Emit the available features compute function. 1784 EmitComputeAvailableFeatures(Info, OS); 1785 1786 1787 size_t MaxNumOperands = 0; 1788 for (std::vector<MatchableInfo*>::const_iterator it = 1789 Info.Matchables.begin(), ie = Info.Matchables.end(); 1790 it != ie; ++it) 1791 MaxNumOperands = std::max(MaxNumOperands, (*it)->AsmOperands.size()); 1792 1793 1794 // Emit the static match table; unused classes get initalized to 0 which is 1795 // guaranteed to be InvalidMatchClass. 1796 // 1797 // FIXME: We can reduce the size of this table very easily. First, we change 1798 // it so that store the kinds in separate bit-fields for each index, which 1799 // only needs to be the max width used for classes at that index (we also need 1800 // to reject based on this during classification). If we then make sure to 1801 // order the match kinds appropriately (putting mnemonics last), then we 1802 // should only end up using a few bits for each class, especially the ones 1803 // following the mnemonic. 1804 OS << "namespace {\n"; 1805 OS << " struct MatchEntry {\n"; 1806 OS << " unsigned Opcode;\n"; 1807 OS << " const char *Mnemonic;\n"; 1808 OS << " ConversionKind ConvertFn;\n"; 1809 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n"; 1810 OS << " unsigned RequiredFeatures;\n"; 1811 OS << " };\n\n"; 1812 1813 OS << "// Predicate for searching for an opcode.\n"; 1814 OS << " struct LessOpcode {\n"; 1815 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n"; 1816 OS << " return StringRef(LHS.Mnemonic) < RHS;\n"; 1817 OS << " }\n"; 1818 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n"; 1819 OS << " return LHS < StringRef(RHS.Mnemonic);\n"; 1820 OS << " }\n"; 1821 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n"; 1822 OS << " return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic);\n"; 1823 OS << " }\n"; 1824 OS << " };\n"; 1825 1826 OS << "} // end anonymous namespace.\n\n"; 1827 1828 OS << "static const MatchEntry MatchTable[" 1829 << Info.Matchables.size() << "] = {\n"; 1830 1831 for (std::vector<MatchableInfo*>::const_iterator it = 1832 Info.Matchables.begin(), ie = Info.Matchables.end(); 1833 it != ie; ++it) { 1834 MatchableInfo &II = **it; 1835 1836 1837 OS << " { " << Target.getName() << "::" 1838 << II.getResultInst()->TheDef->getName() << ", \"" << II.Mnemonic << "\"" 1839 << ", " << II.ConversionFnKind << ", { "; 1840 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) { 1841 MatchableInfo::AsmOperand &Op = II.AsmOperands[i]; 1842 1843 if (i) OS << ", "; 1844 OS << Op.Class->Name; 1845 } 1846 OS << " }, "; 1847 1848 // Write the required features mask. 1849 if (!II.RequiredFeatures.empty()) { 1850 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) { 1851 if (i) OS << "|"; 1852 OS << II.RequiredFeatures[i]->getEnumName(); 1853 } 1854 } else 1855 OS << "0"; 1856 1857 OS << "},\n"; 1858 } 1859 1860 OS << "};\n\n"; 1861 1862 // Finally, build the match function. 1863 OS << Target.getName() << ClassName << "::MatchResultTy " 1864 << Target.getName() << ClassName << "::\n" 1865 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>" 1866 << " &Operands,\n"; 1867 OS << " MCInst &Inst, unsigned &ErrorInfo) {\n"; 1868 1869 // Emit code to get the available features. 1870 OS << " // Get the current feature set.\n"; 1871 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n"; 1872 1873 OS << " // Get the instruction mnemonic, which is the first token.\n"; 1874 OS << " StringRef Mnemonic = ((" << Target.getName() 1875 << "Operand*)Operands[0])->getToken();\n\n"; 1876 1877 if (HasMnemonicAliases) { 1878 OS << " // Process all MnemonicAliases to remap the mnemonic.\n"; 1879 OS << " ApplyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n"; 1880 } 1881 1882 // Emit code to compute the class list for this operand vector. 1883 OS << " // Eliminate obvious mismatches.\n"; 1884 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n"; 1885 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n"; 1886 OS << " return Match_InvalidOperand;\n"; 1887 OS << " }\n\n"; 1888 1889 OS << " // Compute the class list for this operand vector.\n"; 1890 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n"; 1891 OS << " for (unsigned i = 1, e = Operands.size(); i != e; ++i) {\n"; 1892 OS << " Classes[i-1] = ClassifyOperand(Operands[i]);\n\n"; 1893 1894 OS << " // Check for invalid operands before matching.\n"; 1895 OS << " if (Classes[i-1] == InvalidMatchClass) {\n"; 1896 OS << " ErrorInfo = i;\n"; 1897 OS << " return Match_InvalidOperand;\n"; 1898 OS << " }\n"; 1899 OS << " }\n\n"; 1900 1901 OS << " // Mark unused classes.\n"; 1902 OS << " for (unsigned i = Operands.size()-1, e = " << MaxNumOperands << "; " 1903 << "i != e; ++i)\n"; 1904 OS << " Classes[i] = InvalidMatchClass;\n\n"; 1905 1906 OS << " // Some state to try to produce better error messages.\n"; 1907 OS << " bool HadMatchOtherThanFeatures = false;\n\n"; 1908 OS << " // Set ErrorInfo to the operand that mismatches if it is \n"; 1909 OS << " // wrong for all instances of the instruction.\n"; 1910 OS << " ErrorInfo = ~0U;\n"; 1911 1912 // Emit code to search the table. 1913 OS << " // Search the table.\n"; 1914 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n"; 1915 OS << " std::equal_range(MatchTable, MatchTable+" 1916 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n"; 1917 1918 OS << " // Return a more specific error code if no mnemonics match.\n"; 1919 OS << " if (MnemonicRange.first == MnemonicRange.second)\n"; 1920 OS << " return Match_MnemonicFail;\n\n"; 1921 1922 OS << " for (const MatchEntry *it = MnemonicRange.first, " 1923 << "*ie = MnemonicRange.second;\n"; 1924 OS << " it != ie; ++it) {\n"; 1925 1926 OS << " // equal_range guarantees that instruction mnemonic matches.\n"; 1927 OS << " assert(Mnemonic == it->Mnemonic);\n"; 1928 1929 // Emit check that the subclasses match. 1930 OS << " bool OperandsValid = true;\n"; 1931 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n"; 1932 OS << " if (IsSubclass(Classes[i], it->Classes[i]))\n"; 1933 OS << " continue;\n"; 1934 OS << " // If this operand is broken for all of the instances of this\n"; 1935 OS << " // mnemonic, keep track of it so we can report loc info.\n"; 1936 OS << " if (it == MnemonicRange.first || ErrorInfo == i+1)\n"; 1937 OS << " ErrorInfo = i+1;\n"; 1938 OS << " else\n"; 1939 OS << " ErrorInfo = ~0U;"; 1940 OS << " // Otherwise, just reject this instance of the mnemonic.\n"; 1941 OS << " OperandsValid = false;\n"; 1942 OS << " break;\n"; 1943 OS << " }\n\n"; 1944 1945 OS << " if (!OperandsValid) continue;\n"; 1946 1947 // Emit check that the required features are available. 1948 OS << " if ((AvailableFeatures & it->RequiredFeatures) " 1949 << "!= it->RequiredFeatures) {\n"; 1950 OS << " HadMatchOtherThanFeatures = true;\n"; 1951 OS << " continue;\n"; 1952 OS << " }\n"; 1953 1954 OS << "\n"; 1955 OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n"; 1956 1957 // Call the post-processing function, if used. 1958 std::string InsnCleanupFn = 1959 AsmParser->getValueAsString("AsmParserInstCleanup"); 1960 if (!InsnCleanupFn.empty()) 1961 OS << " " << InsnCleanupFn << "(Inst);\n"; 1962 1963 OS << " return Match_Success;\n"; 1964 OS << " }\n\n"; 1965 1966 OS << " // Okay, we had no match. Try to return a useful error code.\n"; 1967 OS << " if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n"; 1968 OS << " return Match_InvalidOperand;\n"; 1969 OS << "}\n\n"; 1970 1971 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n"; 1972} 1973