1//===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines wrappers for the Target class and related global 11// functionality. This makes it easier to access the data and provides a single 12// place that needs to check it for validity. All of these classes abort 13// on error conditions. 14// 15//===----------------------------------------------------------------------===// 16 17#ifndef CODEGEN_TARGET_H 18#define CODEGEN_TARGET_H 19 20#include "CodeGenInstruction.h" 21#include "CodeGenRegisters.h" 22#include "llvm/Support/raw_ostream.h" 23#include "llvm/TableGen/Record.h" 24#include <algorithm> 25 26namespace llvm { 27 28struct CodeGenRegister; 29class CodeGenSchedModels; 30class CodeGenTarget; 31 32// SelectionDAG node properties. 33// SDNPMemOperand: indicates that a node touches memory and therefore must 34// have an associated memory operand that describes the access. 35enum SDNP { 36 SDNPCommutative, 37 SDNPAssociative, 38 SDNPHasChain, 39 SDNPOutGlue, 40 SDNPInGlue, 41 SDNPOptInGlue, 42 SDNPMayLoad, 43 SDNPMayStore, 44 SDNPSideEffect, 45 SDNPMemOperand, 46 SDNPVariadic, 47 SDNPWantRoot, 48 SDNPWantParent 49}; 50 51/// getValueType - Return the MVT::SimpleValueType that the specified TableGen 52/// record corresponds to. 53MVT::SimpleValueType getValueType(Record *Rec); 54 55std::string getName(MVT::SimpleValueType T); 56std::string getEnumName(MVT::SimpleValueType T); 57 58/// getQualifiedName - Return the name of the specified record, with a 59/// namespace qualifier if the record contains one. 60std::string getQualifiedName(const Record *R); 61 62/// CodeGenTarget - This class corresponds to the Target class in the .td files. 63/// 64class CodeGenTarget { 65 RecordKeeper &Records; 66 Record *TargetRec; 67 68 mutable DenseMap<const Record*, CodeGenInstruction*> Instructions; 69 mutable CodeGenRegBank *RegBank; 70 mutable std::vector<Record*> RegAltNameIndices; 71 mutable SmallVector<MVT::SimpleValueType, 8> LegalValueTypes; 72 void ReadRegAltNameIndices() const; 73 void ReadInstructions() const; 74 void ReadLegalValueTypes() const; 75 76 mutable CodeGenSchedModels *SchedModels; 77 78 mutable std::vector<const CodeGenInstruction*> InstrsByEnum; 79public: 80 CodeGenTarget(RecordKeeper &Records); 81 ~CodeGenTarget(); 82 83 Record *getTargetRecord() const { return TargetRec; } 84 const std::string &getName() const; 85 86 /// getInstNamespace - Return the target-specific instruction namespace. 87 /// 88 std::string getInstNamespace() const; 89 90 /// getInstructionSet - Return the InstructionSet object. 91 /// 92 Record *getInstructionSet() const; 93 94 /// getAsmParser - Return the AssemblyParser definition for this target. 95 /// 96 Record *getAsmParser() const; 97 98 /// getAsmParserVariant - Return the AssmblyParserVariant definition for 99 /// this target. 100 /// 101 Record *getAsmParserVariant(unsigned i) const; 102 103 /// getAsmParserVariantCount - Return the AssmblyParserVariant definition 104 /// available for this target. 105 /// 106 unsigned getAsmParserVariantCount() const; 107 108 /// getAsmWriter - Return the AssemblyWriter definition for this target. 109 /// 110 Record *getAsmWriter() const; 111 112 /// getRegBank - Return the register bank description. 113 CodeGenRegBank &getRegBank() const; 114 115 /// getRegisterByName - If there is a register with the specific AsmName, 116 /// return it. 117 const CodeGenRegister *getRegisterByName(StringRef Name) const; 118 119 const std::vector<Record*> &getRegAltNameIndices() const { 120 if (RegAltNameIndices.empty()) ReadRegAltNameIndices(); 121 return RegAltNameIndices; 122 } 123 124 const CodeGenRegisterClass &getRegisterClass(Record *R) const { 125 return *getRegBank().getRegClass(R); 126 } 127 128 /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the 129 /// specified physical register. 130 std::vector<MVT::SimpleValueType> getRegisterVTs(Record *R) const; 131 132 ArrayRef<MVT::SimpleValueType> getLegalValueTypes() const { 133 if (LegalValueTypes.empty()) ReadLegalValueTypes(); 134 return LegalValueTypes; 135 } 136 137 /// isLegalValueType - Return true if the specified value type is natively 138 /// supported by the target (i.e. there are registers that directly hold it). 139 bool isLegalValueType(MVT::SimpleValueType VT) const { 140 ArrayRef<MVT::SimpleValueType> LegalVTs = getLegalValueTypes(); 141 for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i) 142 if (LegalVTs[i] == VT) return true; 143 return false; 144 } 145 146 CodeGenSchedModels &getSchedModels() const; 147 148private: 149 DenseMap<const Record*, CodeGenInstruction*> &getInstructions() const { 150 if (Instructions.empty()) ReadInstructions(); 151 return Instructions; 152 } 153public: 154 155 CodeGenInstruction &getInstruction(const Record *InstRec) const { 156 if (Instructions.empty()) ReadInstructions(); 157 DenseMap<const Record*, CodeGenInstruction*>::iterator I = 158 Instructions.find(InstRec); 159 assert(I != Instructions.end() && "Not an instruction"); 160 return *I->second; 161 } 162 163 /// getInstructionsByEnumValue - Return all of the instructions defined by the 164 /// target, ordered by their enum value. 165 const std::vector<const CodeGenInstruction*> & 166 getInstructionsByEnumValue() const { 167 if (InstrsByEnum.empty()) ComputeInstrsByEnum(); 168 return InstrsByEnum; 169 } 170 171 typedef std::vector<const CodeGenInstruction*>::const_iterator inst_iterator; 172 inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();} 173 inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); } 174 iterator_range<inst_iterator> instructions() const { 175 return iterator_range<inst_iterator>(inst_begin(), inst_end()); 176 } 177 178 179 /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]? 180 /// 181 bool isLittleEndianEncoding() const; 182 183 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit 184 /// encodings, reverse the bit order of all instructions. 185 void reverseBitsForLittleEndianEncoding(); 186 187 /// guessInstructionProperties - should we just guess unset instruction 188 /// properties? 189 bool guessInstructionProperties() const; 190 191private: 192 void ComputeInstrsByEnum() const; 193}; 194 195/// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern 196/// tablegen class in TargetSelectionDAG.td 197class ComplexPattern { 198 MVT::SimpleValueType Ty; 199 unsigned NumOperands; 200 std::string SelectFunc; 201 std::vector<Record*> RootNodes; 202 unsigned Properties; // Node properties 203public: 204 ComplexPattern() : NumOperands(0) {} 205 ComplexPattern(Record *R); 206 207 MVT::SimpleValueType getValueType() const { return Ty; } 208 unsigned getNumOperands() const { return NumOperands; } 209 const std::string &getSelectFunc() const { return SelectFunc; } 210 const std::vector<Record*> &getRootNodes() const { 211 return RootNodes; 212 } 213 bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); } 214}; 215 216} // End llvm namespace 217 218#endif 219