FastISelEmitter.cpp revision 206a10cf286572cd22140559b328e0a14cef7984
1//===- FastISelEmitter.cpp - Generate an instruction selector -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend emits code for use by the "fast" instruction 11// selection algorithm. See the comments at the top of 12// lib/CodeGen/SelectionDAG/FastISel.cpp for background. 13// 14// This file scans through the target's tablegen instruction-info files 15// and extracts instructions with obvious-looking patterns, and it emits 16// code to look up these instructions by type and operator. 17// 18//===----------------------------------------------------------------------===// 19 20#include "FastISelEmitter.h" 21#include "Record.h" 22#include "llvm/Support/Debug.h" 23#include "llvm/ADT/SmallString.h" 24#include "llvm/ADT/VectorExtras.h" 25using namespace llvm; 26 27namespace { 28 29/// InstructionMemo - This class holds additional information about an 30/// instruction needed to emit code for it. 31/// 32struct InstructionMemo { 33 std::string Name; 34 const CodeGenRegisterClass *RC; 35 std::string SubRegNo; 36 std::vector<std::string>* PhysRegs; 37}; 38 39/// ImmPredicateSet - This uniques predicates (represented as a string) and 40/// gives them unique (small) integer ID's that start at 0. 41class ImmPredicateSet { 42 DenseMap<TreePattern *, unsigned> ImmIDs; 43 std::vector<TreePredicateFn> PredsByName; 44public: 45 46 unsigned getIDFor(TreePredicateFn Pred) { 47 unsigned &Entry = ImmIDs[Pred.getOrigPatFragRecord()]; 48 if (Entry == 0) { 49 PredsByName.push_back(Pred); 50 Entry = PredsByName.size(); 51 } 52 return Entry-1; 53 } 54 55 const TreePredicateFn &getPredicate(unsigned i) { 56 assert(i < PredsByName.size()); 57 return PredsByName[i]; 58 } 59 60 typedef std::vector<TreePredicateFn>::const_iterator iterator; 61 iterator begin() const { return PredsByName.begin(); } 62 iterator end() const { return PredsByName.end(); } 63 64}; 65 66/// OperandsSignature - This class holds a description of a list of operand 67/// types. It has utility methods for emitting text based on the operands. 68/// 69struct OperandsSignature { 70 class OpKind { 71 enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 }; 72 char Repr; 73 public: 74 75 OpKind() : Repr(OK_Invalid) {} 76 77 bool operator<(OpKind RHS) const { return Repr < RHS.Repr; } 78 bool operator==(OpKind RHS) const { return Repr == RHS.Repr; } 79 80 static OpKind getReg() { OpKind K; K.Repr = OK_Reg; return K; } 81 static OpKind getFP() { OpKind K; K.Repr = OK_FP; return K; } 82 static OpKind getImm(unsigned V) { 83 assert((unsigned)OK_Imm+V < 128 && 84 "Too many integer predicates for the 'Repr' char"); 85 OpKind K; K.Repr = OK_Imm+V; return K; 86 } 87 88 bool isReg() const { return Repr == OK_Reg; } 89 bool isFP() const { return Repr == OK_FP; } 90 bool isImm() const { return Repr >= OK_Imm; } 91 92 unsigned getImmCode() const { assert(isImm()); return Repr-OK_Imm; } 93 94 void printManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates, 95 bool StripImmCodes) const { 96 if (isReg()) 97 OS << 'r'; 98 else if (isFP()) 99 OS << 'f'; 100 else { 101 OS << 'i'; 102 if (!StripImmCodes) 103 if (unsigned Code = getImmCode()) 104 OS << "_" << ImmPredicates.getPredicate(Code-1).getFnName(); 105 } 106 } 107 }; 108 109 110 SmallVector<OpKind, 3> Operands; 111 112 bool operator<(const OperandsSignature &O) const { 113 return Operands < O.Operands; 114 } 115 bool operator==(const OperandsSignature &O) const { 116 return Operands == O.Operands; 117 } 118 119 bool empty() const { return Operands.empty(); } 120 121 bool hasAnyImmediateCodes() const { 122 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 123 if (Operands[i].isImm() && Operands[i].getImmCode() != 0) 124 return true; 125 return false; 126 } 127 128 /// getWithoutImmCodes - Return a copy of this with any immediate codes forced 129 /// to zero. 130 OperandsSignature getWithoutImmCodes() const { 131 OperandsSignature Result; 132 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 133 if (!Operands[i].isImm()) 134 Result.Operands.push_back(Operands[i]); 135 else 136 Result.Operands.push_back(OpKind::getImm(0)); 137 return Result; 138 } 139 140 void emitImmediatePredicate(raw_ostream &OS, ImmPredicateSet &ImmPredicates) { 141 bool EmittedAnything = false; 142 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 143 if (!Operands[i].isImm()) continue; 144 145 unsigned Code = Operands[i].getImmCode(); 146 if (Code == 0) continue; 147 148 if (EmittedAnything) 149 OS << " &&\n "; 150 151 TreePredicateFn PredFn = ImmPredicates.getPredicate(Code-1); 152 153 // Emit the type check. 154 OS << "VT == " 155 << getEnumName(PredFn.getOrigPatFragRecord()->getTree(0)->getType(0)) 156 << " && "; 157 158 159 OS << PredFn.getFnName() << "(imm" << i <<')'; 160 EmittedAnything = true; 161 } 162 } 163 164 /// initialize - Examine the given pattern and initialize the contents 165 /// of the Operands array accordingly. Return true if all the operands 166 /// are supported, false otherwise. 167 /// 168 bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target, 169 MVT::SimpleValueType VT, 170 ImmPredicateSet &ImmediatePredicates) { 171 if (InstPatNode->isLeaf()) 172 return false; 173 174 if (InstPatNode->getOperator()->getName() == "imm") { 175 Operands.push_back(OpKind::getImm(0)); 176 return true; 177 } 178 179 if (InstPatNode->getOperator()->getName() == "fpimm") { 180 Operands.push_back(OpKind::getFP()); 181 return true; 182 } 183 184 const CodeGenRegisterClass *DstRC = 0; 185 186 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { 187 TreePatternNode *Op = InstPatNode->getChild(i); 188 189 // Handle imm operands specially. 190 if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") { 191 unsigned PredNo = 0; 192 if (!Op->getPredicateFns().empty()) { 193 TreePredicateFn PredFn = Op->getPredicateFns()[0]; 194 // If there is more than one predicate weighing in on this operand 195 // then we don't handle it. This doesn't typically happen for 196 // immediates anyway. 197 if (Op->getPredicateFns().size() > 1 || 198 !PredFn.isImmediatePattern()) 199 return false; 200 // Ignore any instruction with 'FastIselShouldIgnore', these are 201 // not needed and just bloat the fast instruction selector. For 202 // example, X86 doesn't need to generate code to match ADD16ri8 since 203 // ADD16ri will do just fine. 204 Record *Rec = PredFn.getOrigPatFragRecord()->getRecord(); 205 if (Rec->getValueAsBit("FastIselShouldIgnore")) 206 return false; 207 208 PredNo = ImmediatePredicates.getIDFor(PredFn)+1; 209 } 210 211 // Handle unmatched immediate sizes here. 212 //if (Op->getType(0) != VT) 213 // return false; 214 215 Operands.push_back(OpKind::getImm(PredNo)); 216 continue; 217 } 218 219 220 // For now, filter out any operand with a predicate. 221 // For now, filter out any operand with multiple values. 222 if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1) 223 return false; 224 225 if (!Op->isLeaf()) { 226 if (Op->getOperator()->getName() == "fpimm") { 227 Operands.push_back(OpKind::getFP()); 228 continue; 229 } 230 // For now, ignore other non-leaf nodes. 231 return false; 232 } 233 234 assert(Op->hasTypeSet(0) && "Type infererence not done?"); 235 236 // For now, all the operands must have the same type (if they aren't 237 // immediates). Note that this causes us to reject variable sized shifts 238 // on X86. 239 if (Op->getType(0) != VT) 240 return false; 241 242 DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue()); 243 if (!OpDI) 244 return false; 245 Record *OpLeafRec = OpDI->getDef(); 246 247 // For now, the only other thing we accept is register operands. 248 const CodeGenRegisterClass *RC = 0; 249 if (OpLeafRec->isSubClassOf("RegisterClass")) 250 RC = &Target.getRegisterClass(OpLeafRec); 251 else if (OpLeafRec->isSubClassOf("Register")) 252 RC = Target.getRegisterClassForRegister(OpLeafRec); 253 else 254 return false; 255 256 // For now, this needs to be a register class of some sort. 257 if (!RC) 258 return false; 259 260 // For now, all the operands must have the same register class or be 261 // a strict subclass of the destination. 262 if (DstRC) { 263 if (DstRC != RC && !DstRC->hasSubClass(RC)) 264 return false; 265 } else 266 DstRC = RC; 267 Operands.push_back(OpKind::getReg()); 268 } 269 return true; 270 } 271 272 void PrintParameters(raw_ostream &OS) const { 273 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 274 if (Operands[i].isReg()) { 275 OS << "unsigned Op" << i << ", bool Op" << i << "IsKill"; 276 } else if (Operands[i].isImm()) { 277 OS << "uint64_t imm" << i; 278 } else if (Operands[i].isFP()) { 279 OS << "ConstantFP *f" << i; 280 } else { 281 assert("Unknown operand kind!"); 282 abort(); 283 } 284 if (i + 1 != e) 285 OS << ", "; 286 } 287 } 288 289 void PrintArguments(raw_ostream &OS, 290 const std::vector<std::string> &PR) const { 291 assert(PR.size() == Operands.size()); 292 bool PrintedArg = false; 293 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 294 if (PR[i] != "") 295 // Implicit physical register operand. 296 continue; 297 298 if (PrintedArg) 299 OS << ", "; 300 if (Operands[i].isReg()) { 301 OS << "Op" << i << ", Op" << i << "IsKill"; 302 PrintedArg = true; 303 } else if (Operands[i].isImm()) { 304 OS << "imm" << i; 305 PrintedArg = true; 306 } else if (Operands[i].isFP()) { 307 OS << "f" << i; 308 PrintedArg = true; 309 } else { 310 assert("Unknown operand kind!"); 311 abort(); 312 } 313 } 314 } 315 316 void PrintArguments(raw_ostream &OS) const { 317 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 318 if (Operands[i].isReg()) { 319 OS << "Op" << i << ", Op" << i << "IsKill"; 320 } else if (Operands[i].isImm()) { 321 OS << "imm" << i; 322 } else if (Operands[i].isFP()) { 323 OS << "f" << i; 324 } else { 325 assert("Unknown operand kind!"); 326 abort(); 327 } 328 if (i + 1 != e) 329 OS << ", "; 330 } 331 } 332 333 334 void PrintManglingSuffix(raw_ostream &OS, const std::vector<std::string> &PR, 335 ImmPredicateSet &ImmPredicates, 336 bool StripImmCodes = false) const { 337 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 338 if (PR[i] != "") 339 // Implicit physical register operand. e.g. Instruction::Mul expect to 340 // select to a binary op. On x86, mul may take a single operand with 341 // the other operand being implicit. We must emit something that looks 342 // like a binary instruction except for the very inner FastEmitInst_* 343 // call. 344 continue; 345 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes); 346 } 347 } 348 349 void PrintManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates, 350 bool StripImmCodes = false) const { 351 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 352 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes); 353 } 354}; 355 356class FastISelMap { 357 typedef std::map<std::string, InstructionMemo> PredMap; 358 typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap; 359 typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap; 360 typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap; 361 typedef std::map<OperandsSignature, OpcodeTypeRetPredMap> 362 OperandsOpcodeTypeRetPredMap; 363 364 OperandsOpcodeTypeRetPredMap SimplePatterns; 365 366 std::map<OperandsSignature, std::vector<OperandsSignature> > 367 SignaturesWithConstantForms; 368 369 std::string InstNS; 370 ImmPredicateSet ImmediatePredicates; 371public: 372 explicit FastISelMap(std::string InstNS); 373 374 void collectPatterns(CodeGenDAGPatterns &CGP); 375 void printImmediatePredicates(raw_ostream &OS); 376 void printFunctionDefinitions(raw_ostream &OS); 377}; 378 379} 380 381static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) { 382 return CGP.getSDNodeInfo(Op).getEnumName(); 383} 384 385static std::string getLegalCName(std::string OpName) { 386 std::string::size_type pos = OpName.find("::"); 387 if (pos != std::string::npos) 388 OpName.replace(pos, 2, "_"); 389 return OpName; 390} 391 392FastISelMap::FastISelMap(std::string instns) 393 : InstNS(instns) { 394} 395 396static std::string PhyRegForNode(TreePatternNode *Op, 397 const CodeGenTarget &Target) { 398 std::string PhysReg; 399 400 if (!Op->isLeaf()) 401 return PhysReg; 402 403 DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue()); 404 Record *OpLeafRec = OpDI->getDef(); 405 if (!OpLeafRec->isSubClassOf("Register")) 406 return PhysReg; 407 408 PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \ 409 "Namespace")->getValue())->getValue(); 410 PhysReg += "::"; 411 412 std::vector<CodeGenRegister> Regs = Target.getRegisters(); 413 for (unsigned i = 0; i < Regs.size(); ++i) { 414 if (Regs[i].TheDef == OpLeafRec) { 415 PhysReg += Regs[i].getName(); 416 break; 417 } 418 } 419 420 return PhysReg; 421} 422 423void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) { 424 const CodeGenTarget &Target = CGP.getTargetInfo(); 425 426 // Determine the target's namespace name. 427 InstNS = Target.getInstNamespace() + "::"; 428 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!"); 429 430 // Scan through all the patterns and record the simple ones. 431 for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(), 432 E = CGP.ptm_end(); I != E; ++I) { 433 const PatternToMatch &Pattern = *I; 434 435 // For now, just look at Instructions, so that we don't have to worry 436 // about emitting multiple instructions for a pattern. 437 TreePatternNode *Dst = Pattern.getDstPattern(); 438 if (Dst->isLeaf()) continue; 439 Record *Op = Dst->getOperator(); 440 if (!Op->isSubClassOf("Instruction")) 441 continue; 442 CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op); 443 if (II.Operands.empty()) 444 continue; 445 446 // For now, ignore multi-instruction patterns. 447 bool MultiInsts = false; 448 for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) { 449 TreePatternNode *ChildOp = Dst->getChild(i); 450 if (ChildOp->isLeaf()) 451 continue; 452 if (ChildOp->getOperator()->isSubClassOf("Instruction")) { 453 MultiInsts = true; 454 break; 455 } 456 } 457 if (MultiInsts) 458 continue; 459 460 // For now, ignore instructions where the first operand is not an 461 // output register. 462 const CodeGenRegisterClass *DstRC = 0; 463 std::string SubRegNo; 464 if (Op->getName() != "EXTRACT_SUBREG") { 465 Record *Op0Rec = II.Operands[0].Rec; 466 if (!Op0Rec->isSubClassOf("RegisterClass")) 467 continue; 468 DstRC = &Target.getRegisterClass(Op0Rec); 469 if (!DstRC) 470 continue; 471 } else { 472 // If this isn't a leaf, then continue since the register classes are 473 // a bit too complicated for now. 474 if (!Dst->getChild(1)->isLeaf()) continue; 475 476 DefInit *SR = dynamic_cast<DefInit*>(Dst->getChild(1)->getLeafValue()); 477 if (SR) 478 SubRegNo = getQualifiedName(SR->getDef()); 479 else 480 SubRegNo = Dst->getChild(1)->getLeafValue()->getAsString(); 481 } 482 483 // Inspect the pattern. 484 TreePatternNode *InstPatNode = Pattern.getSrcPattern(); 485 if (!InstPatNode) continue; 486 if (InstPatNode->isLeaf()) continue; 487 488 // Ignore multiple result nodes for now. 489 if (InstPatNode->getNumTypes() > 1) continue; 490 491 Record *InstPatOp = InstPatNode->getOperator(); 492 std::string OpcodeName = getOpcodeName(InstPatOp, CGP); 493 MVT::SimpleValueType RetVT = MVT::isVoid; 494 if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getType(0); 495 MVT::SimpleValueType VT = RetVT; 496 if (InstPatNode->getNumChildren()) { 497 assert(InstPatNode->getChild(0)->getNumTypes() == 1); 498 VT = InstPatNode->getChild(0)->getType(0); 499 } 500 501 // For now, filter out any instructions with predicates. 502 if (!InstPatNode->getPredicateFns().empty()) 503 continue; 504 505 // Check all the operands. 506 OperandsSignature Operands; 507 if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates)) 508 continue; 509 510 std::vector<std::string>* PhysRegInputs = new std::vector<std::string>(); 511 if (InstPatNode->getOperator()->getName() == "imm" || 512 InstPatNode->getOperator()->getName() == "fpimmm") 513 PhysRegInputs->push_back(""); 514 else { 515 // Compute the PhysRegs used by the given pattern, and check that 516 // the mapping from the src to dst patterns is simple. 517 bool FoundNonSimplePattern = false; 518 unsigned DstIndex = 0; 519 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { 520 std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target); 521 if (PhysReg.empty()) { 522 if (DstIndex >= Dst->getNumChildren() || 523 Dst->getChild(DstIndex)->getName() != 524 InstPatNode->getChild(i)->getName()) { 525 FoundNonSimplePattern = true; 526 break; 527 } 528 ++DstIndex; 529 } 530 531 PhysRegInputs->push_back(PhysReg); 532 } 533 534 if (Op->getName() != "EXTRACT_SUBREG" && DstIndex < Dst->getNumChildren()) 535 FoundNonSimplePattern = true; 536 537 if (FoundNonSimplePattern) 538 continue; 539 } 540 541 // Get the predicate that guards this pattern. 542 std::string PredicateCheck = Pattern.getPredicateCheck(); 543 544 // Ok, we found a pattern that we can handle. Remember it. 545 InstructionMemo Memo = { 546 Pattern.getDstPattern()->getOperator()->getName(), 547 DstRC, 548 SubRegNo, 549 PhysRegInputs 550 }; 551 552 if (SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck)) 553 throw TGError(Pattern.getSrcRecord()->getLoc(), 554 "Duplicate record in FastISel table!"); 555 556 SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo; 557 558 // If any of the operands were immediates with predicates on them, strip 559 // them down to a signature that doesn't have predicates so that we can 560 // associate them with the stripped predicate version. 561 if (Operands.hasAnyImmediateCodes()) { 562 SignaturesWithConstantForms[Operands.getWithoutImmCodes()] 563 .push_back(Operands); 564 } 565 } 566} 567 568void FastISelMap::printImmediatePredicates(raw_ostream &OS) { 569 if (ImmediatePredicates.begin() == ImmediatePredicates.end()) 570 return; 571 572 OS << "\n// FastEmit Immediate Predicate functions.\n"; 573 for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(), 574 E = ImmediatePredicates.end(); I != E; ++I) { 575 OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n"; 576 OS << I->getImmediatePredicateCode() << "\n}\n"; 577 } 578 579 OS << "\n\n"; 580} 581 582 583void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { 584 // Now emit code for all the patterns that we collected. 585 for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(), 586 OE = SimplePatterns.end(); OI != OE; ++OI) { 587 const OperandsSignature &Operands = OI->first; 588 const OpcodeTypeRetPredMap &OTM = OI->second; 589 590 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end(); 591 I != E; ++I) { 592 const std::string &Opcode = I->first; 593 const TypeRetPredMap &TM = I->second; 594 595 OS << "// FastEmit functions for " << Opcode << ".\n"; 596 OS << "\n"; 597 598 // Emit one function for each opcode,type pair. 599 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end(); 600 TI != TE; ++TI) { 601 MVT::SimpleValueType VT = TI->first; 602 const RetPredMap &RM = TI->second; 603 if (RM.size() != 1) { 604 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end(); 605 RI != RE; ++RI) { 606 MVT::SimpleValueType RetVT = RI->first; 607 const PredMap &PM = RI->second; 608 bool HasPred = false; 609 610 OS << "unsigned FastEmit_" 611 << getLegalCName(Opcode) 612 << "_" << getLegalCName(getName(VT)) 613 << "_" << getLegalCName(getName(RetVT)) << "_"; 614 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 615 OS << "("; 616 Operands.PrintParameters(OS); 617 OS << ") {\n"; 618 619 // Emit code for each possible instruction. There may be 620 // multiple if there are subtarget concerns. 621 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); 622 PI != PE; ++PI) { 623 std::string PredicateCheck = PI->first; 624 const InstructionMemo &Memo = PI->second; 625 626 if (PredicateCheck.empty()) { 627 assert(!HasPred && 628 "Multiple instructions match, at least one has " 629 "a predicate and at least one doesn't!"); 630 } else { 631 OS << " if (" + PredicateCheck + ") {\n"; 632 OS << " "; 633 HasPred = true; 634 } 635 636 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) { 637 if ((*Memo.PhysRegs)[i] != "") 638 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, " 639 << "TII.get(TargetOpcode::COPY), " 640 << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n"; 641 } 642 643 OS << " return FastEmitInst_"; 644 if (Memo.SubRegNo.empty()) { 645 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs, 646 ImmediatePredicates, true); 647 OS << "(" << InstNS << Memo.Name << ", "; 648 OS << InstNS << Memo.RC->getName() << "RegisterClass"; 649 if (!Operands.empty()) 650 OS << ", "; 651 Operands.PrintArguments(OS, *Memo.PhysRegs); 652 OS << ");\n"; 653 } else { 654 OS << "extractsubreg(" << getName(RetVT); 655 OS << ", Op0, Op0IsKill, " << Memo.SubRegNo << ");\n"; 656 } 657 658 if (HasPred) 659 OS << " }\n"; 660 661 } 662 // Return 0 if none of the predicates were satisfied. 663 if (HasPred) 664 OS << " return 0;\n"; 665 OS << "}\n"; 666 OS << "\n"; 667 } 668 669 // Emit one function for the type that demultiplexes on return type. 670 OS << "unsigned FastEmit_" 671 << getLegalCName(Opcode) << "_" 672 << getLegalCName(getName(VT)) << "_"; 673 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 674 OS << "(MVT RetVT"; 675 if (!Operands.empty()) 676 OS << ", "; 677 Operands.PrintParameters(OS); 678 OS << ") {\nswitch (RetVT.SimpleTy) {\n"; 679 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end(); 680 RI != RE; ++RI) { 681 MVT::SimpleValueType RetVT = RI->first; 682 OS << " case " << getName(RetVT) << ": return FastEmit_" 683 << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT)) 684 << "_" << getLegalCName(getName(RetVT)) << "_"; 685 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 686 OS << "("; 687 Operands.PrintArguments(OS); 688 OS << ");\n"; 689 } 690 OS << " default: return 0;\n}\n}\n\n"; 691 692 } else { 693 // Non-variadic return type. 694 OS << "unsigned FastEmit_" 695 << getLegalCName(Opcode) << "_" 696 << getLegalCName(getName(VT)) << "_"; 697 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 698 OS << "(MVT RetVT"; 699 if (!Operands.empty()) 700 OS << ", "; 701 Operands.PrintParameters(OS); 702 OS << ") {\n"; 703 704 OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first) 705 << ")\n return 0;\n"; 706 707 const PredMap &PM = RM.begin()->second; 708 bool HasPred = false; 709 710 // Emit code for each possible instruction. There may be 711 // multiple if there are subtarget concerns. 712 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE; 713 ++PI) { 714 std::string PredicateCheck = PI->first; 715 const InstructionMemo &Memo = PI->second; 716 717 if (PredicateCheck.empty()) { 718 assert(!HasPred && 719 "Multiple instructions match, at least one has " 720 "a predicate and at least one doesn't!"); 721 } else { 722 OS << " if (" + PredicateCheck + ") {\n"; 723 OS << " "; 724 HasPred = true; 725 } 726 727 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) { 728 if ((*Memo.PhysRegs)[i] != "") 729 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, " 730 << "TII.get(TargetOpcode::COPY), " 731 << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n"; 732 } 733 734 OS << " return FastEmitInst_"; 735 736 if (Memo.SubRegNo.empty()) { 737 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs, 738 ImmediatePredicates, true); 739 OS << "(" << InstNS << Memo.Name << ", "; 740 OS << InstNS << Memo.RC->getName() << "RegisterClass"; 741 if (!Operands.empty()) 742 OS << ", "; 743 Operands.PrintArguments(OS, *Memo.PhysRegs); 744 OS << ");\n"; 745 } else { 746 OS << "extractsubreg(RetVT, Op0, Op0IsKill, "; 747 OS << Memo.SubRegNo; 748 OS << ");\n"; 749 } 750 751 if (HasPred) 752 OS << " }\n"; 753 } 754 755 // Return 0 if none of the predicates were satisfied. 756 if (HasPred) 757 OS << " return 0;\n"; 758 OS << "}\n"; 759 OS << "\n"; 760 } 761 } 762 763 // Emit one function for the opcode that demultiplexes based on the type. 764 OS << "unsigned FastEmit_" 765 << getLegalCName(Opcode) << "_"; 766 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 767 OS << "(MVT VT, MVT RetVT"; 768 if (!Operands.empty()) 769 OS << ", "; 770 Operands.PrintParameters(OS); 771 OS << ") {\n"; 772 OS << " switch (VT.SimpleTy) {\n"; 773 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end(); 774 TI != TE; ++TI) { 775 MVT::SimpleValueType VT = TI->first; 776 std::string TypeName = getName(VT); 777 OS << " case " << TypeName << ": return FastEmit_" 778 << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_"; 779 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 780 OS << "(RetVT"; 781 if (!Operands.empty()) 782 OS << ", "; 783 Operands.PrintArguments(OS); 784 OS << ");\n"; 785 } 786 OS << " default: return 0;\n"; 787 OS << " }\n"; 788 OS << "}\n"; 789 OS << "\n"; 790 } 791 792 OS << "// Top-level FastEmit function.\n"; 793 OS << "\n"; 794 795 // Emit one function for the operand signature that demultiplexes based 796 // on opcode and type. 797 OS << "unsigned FastEmit_"; 798 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 799 OS << "(MVT VT, MVT RetVT, unsigned Opcode"; 800 if (!Operands.empty()) 801 OS << ", "; 802 Operands.PrintParameters(OS); 803 OS << ") {\n"; 804 805 // If there are any forms of this signature available that operand on 806 // constrained forms of the immediate (e.g. 32-bit sext immediate in a 807 // 64-bit operand), check them first. 808 809 std::map<OperandsSignature, std::vector<OperandsSignature> >::iterator MI 810 = SignaturesWithConstantForms.find(Operands); 811 if (MI != SignaturesWithConstantForms.end()) { 812 // Unique any duplicates out of the list. 813 std::sort(MI->second.begin(), MI->second.end()); 814 MI->second.erase(std::unique(MI->second.begin(), MI->second.end()), 815 MI->second.end()); 816 817 // Check each in order it was seen. It would be nice to have a good 818 // relative ordering between them, but we're not going for optimality 819 // here. 820 for (unsigned i = 0, e = MI->second.size(); i != e; ++i) { 821 OS << " if ("; 822 MI->second[i].emitImmediatePredicate(OS, ImmediatePredicates); 823 OS << ")\n if (unsigned Reg = FastEmit_"; 824 MI->second[i].PrintManglingSuffix(OS, ImmediatePredicates); 825 OS << "(VT, RetVT, Opcode"; 826 if (!MI->second[i].empty()) 827 OS << ", "; 828 MI->second[i].PrintArguments(OS); 829 OS << "))\n return Reg;\n\n"; 830 } 831 832 // Done with this, remove it. 833 SignaturesWithConstantForms.erase(MI); 834 } 835 836 OS << " switch (Opcode) {\n"; 837 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end(); 838 I != E; ++I) { 839 const std::string &Opcode = I->first; 840 841 OS << " case " << Opcode << ": return FastEmit_" 842 << getLegalCName(Opcode) << "_"; 843 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 844 OS << "(VT, RetVT"; 845 if (!Operands.empty()) 846 OS << ", "; 847 Operands.PrintArguments(OS); 848 OS << ");\n"; 849 } 850 OS << " default: return 0;\n"; 851 OS << " }\n"; 852 OS << "}\n"; 853 OS << "\n"; 854 } 855 856 // TODO: SignaturesWithConstantForms should be empty here. 857} 858 859void FastISelEmitter::run(raw_ostream &OS) { 860 const CodeGenTarget &Target = CGP.getTargetInfo(); 861 862 // Determine the target's namespace name. 863 std::string InstNS = Target.getInstNamespace() + "::"; 864 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!"); 865 866 EmitSourceFileHeader("\"Fast\" Instruction Selector for the " + 867 Target.getName() + " target", OS); 868 869 FastISelMap F(InstNS); 870 F.collectPatterns(CGP); 871 F.printImmediatePredicates(OS); 872 F.printFunctionDefinitions(OS); 873} 874 875FastISelEmitter::FastISelEmitter(RecordKeeper &R) 876 : Records(R), CGP(R) { 877} 878 879