InstrInfoEmitter.cpp revision 3f7b7f8ce0b050fc6a0100839d9c5a84198b2aed 
1//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend is responsible for emitting a description of the target
11// instruction set for the code generator.
12//
13//===----------------------------------------------------------------------===//
14
15
16#include "CodeGenDAGPatterns.h"
17#include "CodeGenSchedule.h"
18#include "CodeGenTarget.h"
19#include "SequenceToOffsetTable.h"
20#include "llvm/ADT/StringExtras.h"
21#include "llvm/TableGen/Record.h"
22#include "llvm/TableGen/TableGenBackend.h"
23#include <algorithm>
24#include <cstdio>
25#include <map>
26#include <vector>
27using namespace llvm;
28
29namespace {
30class InstrInfoEmitter {
31  RecordKeeper &Records;
32  CodeGenDAGPatterns CDP;
33  const CodeGenSchedModels &SchedModels;
34
35public:
36  InstrInfoEmitter(RecordKeeper &R):
37    Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {}
38
39  // run - Output the instruction set description.
40  void run(raw_ostream &OS);
41
42private:
43  void emitEnums(raw_ostream &OS);
44
45  typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
46  void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
47                  Record *InstrInfo,
48                  std::map<std::vector<Record*>, unsigned> &EL,
49                  const OperandInfoMapTy &OpInfo,
50                  raw_ostream &OS);
51
52  // Operand information.
53  void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs);
54  std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
55};
56} // End anonymous namespace
57
58static void PrintDefList(const std::vector<Record*> &Uses,
59                         unsigned Num, raw_ostream &OS) {
60  OS << "static const uint16_t ImplicitList" << Num << "[] = { ";
61  for (unsigned i = 0, e = Uses.size(); i != e; ++i)
62    OS << getQualifiedName(Uses[i]) << ", ";
63  OS << "0 };\n";
64}
65
66//===----------------------------------------------------------------------===//
67// Operand Info Emission.
68//===----------------------------------------------------------------------===//
69
70std::vector<std::string>
71InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
72  std::vector<std::string> Result;
73
74  for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
75    // Handle aggregate operands and normal operands the same way by expanding
76    // either case into a list of operands for this op.
77    std::vector<CGIOperandList::OperandInfo> OperandList;
78
79    // This might be a multiple operand thing.  Targets like X86 have
80    // registers in their multi-operand operands.  It may also be an anonymous
81    // operand, which has a single operand, but no declared class for the
82    // operand.
83    DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
84
85    if (!MIOI || MIOI->getNumArgs() == 0) {
86      // Single, anonymous, operand.
87      OperandList.push_back(Inst.Operands[i]);
88    } else {
89      for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) {
90        OperandList.push_back(Inst.Operands[i]);
91
92        Record *OpR = cast<DefInit>(MIOI->getArg(j))->getDef();
93        OperandList.back().Rec = OpR;
94      }
95    }
96
97    for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
98      Record *OpR = OperandList[j].Rec;
99      std::string Res;
100
101      if (OpR->isSubClassOf("RegisterOperand"))
102        OpR = OpR->getValueAsDef("RegClass");
103      if (OpR->isSubClassOf("RegisterClass"))
104        Res += getQualifiedName(OpR) + "RegClassID, ";
105      else if (OpR->isSubClassOf("PointerLikeRegClass"))
106        Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
107      else
108        // -1 means the operand does not have a fixed register class.
109        Res += "-1, ";
110
111      // Fill in applicable flags.
112      Res += "0";
113
114      // Ptr value whose register class is resolved via callback.
115      if (OpR->isSubClassOf("PointerLikeRegClass"))
116        Res += "|(1<<MCOI::LookupPtrRegClass)";
117
118      // Predicate operands.  Check to see if the original unexpanded operand
119      // was of type PredicateOperand.
120      if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand"))
121        Res += "|(1<<MCOI::Predicate)";
122
123      // Optional def operands.  Check to see if the original unexpanded operand
124      // was of type OptionalDefOperand.
125      if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand"))
126        Res += "|(1<<MCOI::OptionalDef)";
127
128      // Fill in operand type.
129      Res += ", MCOI::";
130      assert(!Inst.Operands[i].OperandType.empty() && "Invalid operand type.");
131      Res += Inst.Operands[i].OperandType;
132
133      // Fill in constraint info.
134      Res += ", ";
135
136      const CGIOperandList::ConstraintInfo &Constraint =
137        Inst.Operands[i].Constraints[j];
138      if (Constraint.isNone())
139        Res += "0";
140      else if (Constraint.isEarlyClobber())
141        Res += "(1 << MCOI::EARLY_CLOBBER)";
142      else {
143        assert(Constraint.isTied());
144        Res += "((" + utostr(Constraint.getTiedOperand()) +
145                    " << 16) | (1 << MCOI::TIED_TO))";
146      }
147
148      Result.push_back(Res);
149    }
150  }
151
152  return Result;
153}
154
155void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
156                                       OperandInfoMapTy &OperandInfoIDs) {
157  // ID #0 is for no operand info.
158  unsigned OperandListNum = 0;
159  OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
160
161  OS << "\n";
162  const CodeGenTarget &Target = CDP.getTargetInfo();
163  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
164       E = Target.inst_end(); II != E; ++II) {
165    std::vector<std::string> OperandInfo = GetOperandInfo(**II);
166    unsigned &N = OperandInfoIDs[OperandInfo];
167    if (N != 0) continue;
168
169    N = ++OperandListNum;
170    OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";
171    for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
172      OS << "{ " << OperandInfo[i] << " }, ";
173    OS << "};\n";
174  }
175}
176
177//===----------------------------------------------------------------------===//
178// Main Output.
179//===----------------------------------------------------------------------===//
180
181// run - Emit the main instruction description records for the target...
182void InstrInfoEmitter::run(raw_ostream &OS) {
183  emitSourceFileHeader("Target Instruction Enum Values", OS);
184  emitEnums(OS);
185
186  emitSourceFileHeader("Target Instruction Descriptors", OS);
187
188  OS << "\n#ifdef GET_INSTRINFO_MC_DESC\n";
189  OS << "#undef GET_INSTRINFO_MC_DESC\n";
190
191  OS << "namespace llvm {\n\n";
192
193  CodeGenTarget &Target = CDP.getTargetInfo();
194  const std::string &TargetName = Target.getName();
195  Record *InstrInfo = Target.getInstructionSet();
196
197  // Keep track of all of the def lists we have emitted already.
198  std::map<std::vector<Record*>, unsigned> EmittedLists;
199  unsigned ListNumber = 0;
200
201  // Emit all of the instruction's implicit uses and defs.
202  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
203         E = Target.inst_end(); II != E; ++II) {
204    Record *Inst = (*II)->TheDef;
205    std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
206    if (!Uses.empty()) {
207      unsigned &IL = EmittedLists[Uses];
208      if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
209    }
210    std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
211    if (!Defs.empty()) {
212      unsigned &IL = EmittedLists[Defs];
213      if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
214    }
215  }
216
217  OperandInfoMapTy OperandInfoIDs;
218
219  // Emit all of the operand info records.
220  EmitOperandInfo(OS, OperandInfoIDs);
221
222  // Emit all of the MCInstrDesc records in their ENUM ordering.
223  //
224  OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
225  const std::vector<const CodeGenInstruction*> &NumberedInstructions =
226    Target.getInstructionsByEnumValue();
227
228  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
229    emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
230               OperandInfoIDs, OS);
231  OS << "};\n\n";
232
233  // Build an array of instruction names
234  SequenceToOffsetTable<std::string> InstrNames;
235  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
236    const CodeGenInstruction *Instr = NumberedInstructions[i];
237    InstrNames.add(Instr->TheDef->getName());
238  }
239
240  InstrNames.layout();
241  OS << "extern const char " << TargetName << "InstrNameData[] = {\n";
242  InstrNames.emit(OS, printChar);
243  OS << "};\n\n";
244
245  OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {";
246  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
247    if (i % 8 == 0)
248      OS << "\n    ";
249    const CodeGenInstruction *Instr = NumberedInstructions[i];
250    OS << InstrNames.get(Instr->TheDef->getName()) << "U, ";
251  }
252
253  OS << "\n};\n\n";
254
255  // MCInstrInfo initialization routine.
256  OS << "static inline void Init" << TargetName
257     << "MCInstrInfo(MCInstrInfo *II) {\n";
258  OS << "  II->InitMCInstrInfo(" << TargetName << "Insts, "
259     << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
260     << NumberedInstructions.size() << ");\n}\n\n";
261
262  OS << "} // End llvm namespace \n";
263
264  OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
265
266  // Create a TargetInstrInfo subclass to hide the MC layer initialization.
267  OS << "\n#ifdef GET_INSTRINFO_HEADER\n";
268  OS << "#undef GET_INSTRINFO_HEADER\n";
269
270  std::string ClassName = TargetName + "GenInstrInfo";
271  OS << "namespace llvm {\n";
272  OS << "struct " << ClassName << " : public TargetInstrInfoImpl {\n"
273     << "  explicit " << ClassName << "(int SO = -1, int DO = -1);\n"
274     << "};\n";
275  OS << "} // End llvm namespace \n";
276
277  OS << "#endif // GET_INSTRINFO_HEADER\n\n";
278
279  OS << "\n#ifdef GET_INSTRINFO_CTOR\n";
280  OS << "#undef GET_INSTRINFO_CTOR\n";
281
282  OS << "namespace llvm {\n";
283  OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n";
284  OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n";
285  OS << "extern const char " << TargetName << "InstrNameData[];\n";
286  OS << ClassName << "::" << ClassName << "(int SO, int DO)\n"
287     << "  : TargetInstrInfoImpl(SO, DO) {\n"
288     << "  InitMCInstrInfo(" << TargetName << "Insts, "
289     << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
290     << NumberedInstructions.size() << ");\n}\n";
291  OS << "} // End llvm namespace \n";
292
293  OS << "#endif // GET_INSTRINFO_CTOR\n\n";
294}
295
296void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
297                                  Record *InstrInfo,
298                         std::map<std::vector<Record*>, unsigned> &EmittedLists,
299                                  const OperandInfoMapTy &OpInfo,
300                                  raw_ostream &OS) {
301  int MinOperands = 0;
302  if (!Inst.Operands.size() == 0)
303    // Each logical operand can be multiple MI operands.
304    MinOperands = Inst.Operands.back().MIOperandNo +
305                  Inst.Operands.back().MINumOperands;
306
307  OS << "  { ";
308  OS << Num << ",\t" << MinOperands << ",\t"
309     << Inst.Operands.NumDefs << ",\t"
310     << SchedModels.getSchedClassIdx(Inst) << ",\t"
311     << Inst.TheDef->getValueAsInt("Size") << ",\t0";
312
313  // Emit all of the target indepedent flags...
314  if (Inst.isPseudo)           OS << "|(1<<MCID::Pseudo)";
315  if (Inst.isReturn)           OS << "|(1<<MCID::Return)";
316  if (Inst.isBranch)           OS << "|(1<<MCID::Branch)";
317  if (Inst.isIndirectBranch)   OS << "|(1<<MCID::IndirectBranch)";
318  if (Inst.isCompare)          OS << "|(1<<MCID::Compare)";
319  if (Inst.isMoveImm)          OS << "|(1<<MCID::MoveImm)";
320  if (Inst.isBitcast)          OS << "|(1<<MCID::Bitcast)";
321  if (Inst.isSelect)           OS << "|(1<<MCID::Select)";
322  if (Inst.isBarrier)          OS << "|(1<<MCID::Barrier)";
323  if (Inst.hasDelaySlot)       OS << "|(1<<MCID::DelaySlot)";
324  if (Inst.isCall)             OS << "|(1<<MCID::Call)";
325  if (Inst.canFoldAsLoad)      OS << "|(1<<MCID::FoldableAsLoad)";
326  if (Inst.mayLoad)            OS << "|(1<<MCID::MayLoad)";
327  if (Inst.mayStore)           OS << "|(1<<MCID::MayStore)";
328  if (Inst.isPredicable)       OS << "|(1<<MCID::Predicable)";
329  if (Inst.isConvertibleToThreeAddress) OS << "|(1<<MCID::ConvertibleTo3Addr)";
330  if (Inst.isCommutable)       OS << "|(1<<MCID::Commutable)";
331  if (Inst.isTerminator)       OS << "|(1<<MCID::Terminator)";
332  if (Inst.isReMaterializable) OS << "|(1<<MCID::Rematerializable)";
333  if (Inst.isNotDuplicable)    OS << "|(1<<MCID::NotDuplicable)";
334  if (Inst.Operands.hasOptionalDef) OS << "|(1<<MCID::HasOptionalDef)";
335  if (Inst.usesCustomInserter) OS << "|(1<<MCID::UsesCustomInserter)";
336  if (Inst.hasPostISelHook)    OS << "|(1<<MCID::HasPostISelHook)";
337  if (Inst.Operands.isVariadic)OS << "|(1<<MCID::Variadic)";
338  if (Inst.hasSideEffects)     OS << "|(1<<MCID::UnmodeledSideEffects)";
339  if (Inst.isAsCheapAsAMove)   OS << "|(1<<MCID::CheapAsAMove)";
340  if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<MCID::ExtraSrcRegAllocReq)";
341  if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<MCID::ExtraDefRegAllocReq)";
342
343  // Emit all of the target-specific flags...
344  BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
345  if (!TSF) throw "no TSFlags?";
346  uint64_t Value = 0;
347  for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
348    if (BitInit *Bit = dyn_cast<BitInit>(TSF->getBit(i)))
349      Value |= uint64_t(Bit->getValue()) << i;
350    else
351      throw "Invalid TSFlags bit in " + Inst.TheDef->getName();
352  }
353  OS << ", 0x";
354  OS.write_hex(Value);
355  OS << "ULL, ";
356
357  // Emit the implicit uses and defs lists...
358  std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
359  if (UseList.empty())
360    OS << "NULL, ";
361  else
362    OS << "ImplicitList" << EmittedLists[UseList] << ", ";
363
364  std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
365  if (DefList.empty())
366    OS << "NULL, ";
367  else
368    OS << "ImplicitList" << EmittedLists[DefList] << ", ";
369
370  // Emit the operand info.
371  std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
372  if (OperandInfo.empty())
373    OS << "0";
374  else
375    OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
376
377  OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
378}
379
380// emitEnums - Print out enum values for all of the instructions.
381void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
382
383  OS << "\n#ifdef GET_INSTRINFO_ENUM\n";
384  OS << "#undef GET_INSTRINFO_ENUM\n";
385
386  OS << "namespace llvm {\n\n";
387
388  CodeGenTarget Target(Records);
389
390  // We must emit the PHI opcode first...
391  std::string Namespace = Target.getInstNamespace();
392
393  if (Namespace.empty()) {
394    fprintf(stderr, "No instructions defined!\n");
395    exit(1);
396  }
397
398  const std::vector<const CodeGenInstruction*> &NumberedInstructions =
399    Target.getInstructionsByEnumValue();
400
401  OS << "namespace " << Namespace << " {\n";
402  OS << "  enum {\n";
403  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
404    OS << "    " << NumberedInstructions[i]->TheDef->getName()
405       << "\t= " << i << ",\n";
406  }
407  OS << "    INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
408  OS << "  };\n}\n";
409  OS << "} // End llvm namespace \n";
410
411  OS << "#endif // GET_INSTRINFO_ENUM\n\n";
412}
413
414namespace llvm {
415
416void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) {
417  InstrInfoEmitter(RK).run(OS);
418}
419
420} // End llvm namespace
421