InstrInfoEmitter.cpp revision 5a364c5561ec04e33a6f5d52c14f1bac6f247ea0
1//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend is responsible for emitting a description of the target 11// instruction set for the code generator. 12// 13//===----------------------------------------------------------------------===// 14 15 16#include "CodeGenDAGPatterns.h" 17#include "CodeGenSchedule.h" 18#include "CodeGenTarget.h" 19#include "SequenceToOffsetTable.h" 20#include "TableGenBackends.h" 21#include "llvm/ADT/StringExtras.h" 22#include "llvm/TableGen/Error.h" 23#include "llvm/TableGen/Record.h" 24#include "llvm/TableGen/TableGenBackend.h" 25#include <algorithm> 26#include <cstdio> 27#include <map> 28#include <vector> 29using namespace llvm; 30 31namespace { 32class InstrInfoEmitter { 33 RecordKeeper &Records; 34 CodeGenDAGPatterns CDP; 35 const CodeGenSchedModels &SchedModels; 36 37public: 38 InstrInfoEmitter(RecordKeeper &R): 39 Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {} 40 41 // run - Output the instruction set description. 42 void run(raw_ostream &OS); 43 44private: 45 void emitEnums(raw_ostream &OS); 46 47 typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy; 48 49 /// The keys of this map are maps which have OpName enum values as their keys 50 /// and instruction operand indices as their values. The values of this map 51 /// are lists of instruction names. 52 typedef std::map<std::map<unsigned, unsigned>, 53 std::vector<std::string> > OpNameMapTy; 54 typedef std::map<std::string, unsigned>::iterator StrUintMapIter; 55 void emitRecord(const CodeGenInstruction &Inst, unsigned Num, 56 Record *InstrInfo, 57 std::map<std::vector<Record*>, unsigned> &EL, 58 const OperandInfoMapTy &OpInfo, 59 raw_ostream &OS); 60 void initOperandMapData( 61 const std::vector<const CodeGenInstruction *> NumberedInstructions, 62 const std::string &Namespace, 63 std::map<std::string, unsigned> &Operands, 64 OpNameMapTy &OperandMap); 65 void emitOperandNameMappings(raw_ostream &OS, const CodeGenTarget &Target, 66 const std::vector<const CodeGenInstruction*> &NumberedInstructions); 67 68 // Operand information. 69 void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs); 70 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst); 71}; 72} // End anonymous namespace 73 74static void PrintDefList(const std::vector<Record*> &Uses, 75 unsigned Num, raw_ostream &OS) { 76 OS << "static const uint16_t ImplicitList" << Num << "[] = { "; 77 for (unsigned i = 0, e = Uses.size(); i != e; ++i) 78 OS << getQualifiedName(Uses[i]) << ", "; 79 OS << "0 };\n"; 80} 81 82//===----------------------------------------------------------------------===// 83// Operand Info Emission. 84//===----------------------------------------------------------------------===// 85 86std::vector<std::string> 87InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { 88 std::vector<std::string> Result; 89 90 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) { 91 // Handle aggregate operands and normal operands the same way by expanding 92 // either case into a list of operands for this op. 93 std::vector<CGIOperandList::OperandInfo> OperandList; 94 95 // This might be a multiple operand thing. Targets like X86 have 96 // registers in their multi-operand operands. It may also be an anonymous 97 // operand, which has a single operand, but no declared class for the 98 // operand. 99 DagInit *MIOI = Inst.Operands[i].MIOperandInfo; 100 101 if (!MIOI || MIOI->getNumArgs() == 0) { 102 // Single, anonymous, operand. 103 OperandList.push_back(Inst.Operands[i]); 104 } else { 105 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) { 106 OperandList.push_back(Inst.Operands[i]); 107 108 Record *OpR = cast<DefInit>(MIOI->getArg(j))->getDef(); 109 OperandList.back().Rec = OpR; 110 } 111 } 112 113 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) { 114 Record *OpR = OperandList[j].Rec; 115 std::string Res; 116 117 if (OpR->isSubClassOf("RegisterOperand")) 118 OpR = OpR->getValueAsDef("RegClass"); 119 if (OpR->isSubClassOf("RegisterClass")) 120 Res += getQualifiedName(OpR) + "RegClassID, "; 121 else if (OpR->isSubClassOf("PointerLikeRegClass")) 122 Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", "; 123 else 124 // -1 means the operand does not have a fixed register class. 125 Res += "-1, "; 126 127 // Fill in applicable flags. 128 Res += "0"; 129 130 // Ptr value whose register class is resolved via callback. 131 if (OpR->isSubClassOf("PointerLikeRegClass")) 132 Res += "|(1<<MCOI::LookupPtrRegClass)"; 133 134 // Predicate operands. Check to see if the original unexpanded operand 135 // was of type PredicateOp. 136 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOp")) 137 Res += "|(1<<MCOI::Predicate)"; 138 139 // Optional def operands. Check to see if the original unexpanded operand 140 // was of type OptionalDefOperand. 141 if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand")) 142 Res += "|(1<<MCOI::OptionalDef)"; 143 144 // Fill in operand type. 145 Res += ", MCOI::"; 146 assert(!Inst.Operands[i].OperandType.empty() && "Invalid operand type."); 147 Res += Inst.Operands[i].OperandType; 148 149 // Fill in constraint info. 150 Res += ", "; 151 152 const CGIOperandList::ConstraintInfo &Constraint = 153 Inst.Operands[i].Constraints[j]; 154 if (Constraint.isNone()) 155 Res += "0"; 156 else if (Constraint.isEarlyClobber()) 157 Res += "(1 << MCOI::EARLY_CLOBBER)"; 158 else { 159 assert(Constraint.isTied()); 160 Res += "((" + utostr(Constraint.getTiedOperand()) + 161 " << 16) | (1 << MCOI::TIED_TO))"; 162 } 163 164 Result.push_back(Res); 165 } 166 } 167 168 return Result; 169} 170 171void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS, 172 OperandInfoMapTy &OperandInfoIDs) { 173 // ID #0 is for no operand info. 174 unsigned OperandListNum = 0; 175 OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum; 176 177 OS << "\n"; 178 const CodeGenTarget &Target = CDP.getTargetInfo(); 179 for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 180 E = Target.inst_end(); II != E; ++II) { 181 std::vector<std::string> OperandInfo = GetOperandInfo(**II); 182 unsigned &N = OperandInfoIDs[OperandInfo]; 183 if (N != 0) continue; 184 185 N = ++OperandListNum; 186 OS << "static const MCOperandInfo OperandInfo" << N << "[] = { "; 187 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) 188 OS << "{ " << OperandInfo[i] << " }, "; 189 OS << "};\n"; 190 } 191} 192 193 194/// Initialize data structures for generating operand name mappings. 195/// 196/// \param Operands [out] A map used to generate the OpName enum with operand 197/// names as its keys and operand enum values as its values. 198/// \param OperandMap [out] A map for representing the operand name mappings for 199/// each instructions. This is used to generate the OperandMap table as 200/// well as the getNamedOperandIdx() function. 201void InstrInfoEmitter::initOperandMapData( 202 const std::vector<const CodeGenInstruction *> NumberedInstructions, 203 const std::string &Namespace, 204 std::map<std::string, unsigned> &Operands, 205 OpNameMapTy &OperandMap) { 206 207 unsigned NumOperands = 0; 208 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 209 const CodeGenInstruction *Inst = NumberedInstructions[i]; 210 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable")) { 211 continue; 212 } 213 std::map<unsigned, unsigned> OpList; 214 for (unsigned j = 0, je = Inst->Operands.size(); j != je; ++j) { 215 const CGIOperandList::OperandInfo &Info = Inst->Operands[j]; 216 StrUintMapIter I = Operands.find(Info.Name); 217 218 if (I == Operands.end()) { 219 I = Operands.insert(Operands.begin(), 220 std::pair<std::string, unsigned>(Info.Name, NumOperands++)); 221 } 222 OpList[I->second] = Info.MIOperandNo; 223 } 224 OperandMap[OpList].push_back(Namespace + "::" + Inst->TheDef->getName()); 225 } 226} 227 228/// Generate a table and function for looking up the indices of operands by 229/// name. 230/// 231/// This code generates: 232/// - An enum in the llvm::TargetNamespace::OpName namespace, with one entry 233/// for each operand name. 234/// - A 2-dimensional table called OperandMap for mapping OpName enum values to 235/// operand indices. 236/// - A function called getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) 237/// for looking up the operand index for an instruction, given a value from 238/// OpName enum 239void InstrInfoEmitter::emitOperandNameMappings(raw_ostream &OS, 240 const CodeGenTarget &Target, 241 const std::vector<const CodeGenInstruction*> &NumberedInstructions) { 242 243 const std::string &Namespace = Target.getInstNamespace(); 244 std::string OpNameNS = "OpName"; 245 // Map of operand names to their enumeration value. This will be used to 246 // generate the OpName enum. 247 std::map<std::string, unsigned> Operands; 248 OpNameMapTy OperandMap; 249 250 initOperandMapData(NumberedInstructions, Namespace, Operands, OperandMap); 251 252 OS << "#ifdef GET_INSTRINFO_OPERAND_ENUM\n"; 253 OS << "#undef GET_INSTRINFO_OPERAND_ENUM\n"; 254 OS << "namespace llvm {"; 255 OS << "namespace " << Namespace << " {\n"; 256 OS << "namespace " << OpNameNS << " { \n"; 257 OS << "enum {\n"; 258 for (StrUintMapIter i = Operands.begin(), e = Operands.end(); i != e; ++i) 259 OS << " " << i->first << " = " << i->second << ",\n"; 260 261 OS << "OPERAND_LAST"; 262 OS << "\n};\n"; 263 OS << "} // End namespace OpName\n"; 264 OS << "} // End namespace " << Namespace << "\n"; 265 OS << "} // End namespace llvm\n"; 266 OS << "#endif //GET_INSTRINFO_OPERAND_ENUM\n"; 267 268 OS << "#ifdef GET_INSTRINFO_NAMED_OPS\n"; 269 OS << "#undef GET_INSTRINFO_NAMED_OPS\n"; 270 OS << "namespace llvm {"; 271 OS << "namespace " << Namespace << " {\n"; 272 OS << "int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {\n"; 273 if (!Operands.empty()) { 274 OS << " static const int16_t OperandMap [][" << Operands.size() 275 << "] = {\n"; 276 for (OpNameMapTy::iterator i = OperandMap.begin(), e = OperandMap.end(); 277 i != e; ++i) { 278 const std::map<unsigned, unsigned> &OpList = i->first; 279 OS << "{"; 280 281 // Emit a row of the OperandMap table 282 for (unsigned ii = 0, ie = Operands.size(); ii != ie; ++ii) 283 OS << (OpList.count(ii) == 0 ? -1 : (int)OpList.find(ii)->second) 284 << ", "; 285 286 OS << "},\n"; 287 } 288 OS << "};\n"; 289 290 OS << " switch(Opcode) {\n"; 291 unsigned TableIndex = 0; 292 for (OpNameMapTy::iterator i = OperandMap.begin(), e = OperandMap.end(); 293 i != e; ++i) { 294 std::vector<std::string> &OpcodeList = i->second; 295 296 for (unsigned ii = 0, ie = OpcodeList.size(); ii != ie; ++ii) 297 OS << " case " << OpcodeList[ii] << ":\n"; 298 299 OS << " return OperandMap[" << TableIndex++ << "][NamedIdx];\n"; 300 } 301 OS << " default: return -1;\n"; 302 OS << " }\n"; 303 } else { 304 // There are no operands, so no need to emit anything 305 OS << " return -1;\n"; 306 } 307 OS << "}\n"; 308 OS << "} // End namespace " << Namespace << "\n"; 309 OS << "} // End namespace llvm\n"; 310 OS << "#endif //GET_INSTRINFO_NAMED_OPS\n"; 311 312} 313 314//===----------------------------------------------------------------------===// 315// Main Output. 316//===----------------------------------------------------------------------===// 317 318// run - Emit the main instruction description records for the target... 319void InstrInfoEmitter::run(raw_ostream &OS) { 320 emitSourceFileHeader("Target Instruction Enum Values", OS); 321 emitEnums(OS); 322 323 emitSourceFileHeader("Target Instruction Descriptors", OS); 324 325 OS << "\n#ifdef GET_INSTRINFO_MC_DESC\n"; 326 OS << "#undef GET_INSTRINFO_MC_DESC\n"; 327 328 OS << "namespace llvm {\n\n"; 329 330 CodeGenTarget &Target = CDP.getTargetInfo(); 331 const std::string &TargetName = Target.getName(); 332 Record *InstrInfo = Target.getInstructionSet(); 333 334 // Keep track of all of the def lists we have emitted already. 335 std::map<std::vector<Record*>, unsigned> EmittedLists; 336 unsigned ListNumber = 0; 337 338 // Emit all of the instruction's implicit uses and defs. 339 for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 340 E = Target.inst_end(); II != E; ++II) { 341 Record *Inst = (*II)->TheDef; 342 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses"); 343 if (!Uses.empty()) { 344 unsigned &IL = EmittedLists[Uses]; 345 if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS); 346 } 347 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs"); 348 if (!Defs.empty()) { 349 unsigned &IL = EmittedLists[Defs]; 350 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS); 351 } 352 } 353 354 OperandInfoMapTy OperandInfoIDs; 355 356 // Emit all of the operand info records. 357 EmitOperandInfo(OS, OperandInfoIDs); 358 359 // Emit all of the MCInstrDesc records in their ENUM ordering. 360 // 361 OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n"; 362 const std::vector<const CodeGenInstruction*> &NumberedInstructions = 363 Target.getInstructionsByEnumValue(); 364 365 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) 366 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists, 367 OperandInfoIDs, OS); 368 OS << "};\n\n"; 369 370 // Build an array of instruction names 371 SequenceToOffsetTable<std::string> InstrNames; 372 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 373 const CodeGenInstruction *Instr = NumberedInstructions[i]; 374 InstrNames.add(Instr->TheDef->getName()); 375 } 376 377 InstrNames.layout(); 378 OS << "extern const char " << TargetName << "InstrNameData[] = {\n"; 379 InstrNames.emit(OS, printChar); 380 OS << "};\n\n"; 381 382 OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {"; 383 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 384 if (i % 8 == 0) 385 OS << "\n "; 386 const CodeGenInstruction *Instr = NumberedInstructions[i]; 387 OS << InstrNames.get(Instr->TheDef->getName()) << "U, "; 388 } 389 390 OS << "\n};\n\n"; 391 392 // MCInstrInfo initialization routine. 393 OS << "static inline void Init" << TargetName 394 << "MCInstrInfo(MCInstrInfo *II) {\n"; 395 OS << " II->InitMCInstrInfo(" << TargetName << "Insts, " 396 << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, " 397 << NumberedInstructions.size() << ");\n}\n\n"; 398 399 OS << "} // End llvm namespace \n"; 400 401 OS << "#endif // GET_INSTRINFO_MC_DESC\n\n"; 402 403 // Create a TargetInstrInfo subclass to hide the MC layer initialization. 404 OS << "\n#ifdef GET_INSTRINFO_HEADER\n"; 405 OS << "#undef GET_INSTRINFO_HEADER\n"; 406 407 std::string ClassName = TargetName + "GenInstrInfo"; 408 OS << "namespace llvm {\n"; 409 OS << "struct " << ClassName << " : public TargetInstrInfo {\n" 410 << " explicit " << ClassName << "(int SO = -1, int DO = -1);\n" 411 << " virtual ~" << ClassName << "();\n" 412 << "};\n"; 413 OS << "} // End llvm namespace \n"; 414 415 OS << "#endif // GET_INSTRINFO_HEADER\n\n"; 416 417 OS << "\n#ifdef GET_INSTRINFO_CTOR_DTOR\n"; 418 OS << "#undef GET_INSTRINFO_CTOR_DTOR\n"; 419 420 OS << "namespace llvm {\n"; 421 OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n"; 422 OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n"; 423 OS << "extern const char " << TargetName << "InstrNameData[];\n"; 424 OS << ClassName << "::" << ClassName << "(int SO, int DO)\n" 425 << " : TargetInstrInfo(SO, DO) {\n" 426 << " InitMCInstrInfo(" << TargetName << "Insts, " 427 << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, " 428 << NumberedInstructions.size() << ");\n}\n" 429 << ClassName << "::~" << ClassName << "() {}\n"; 430 OS << "} // End llvm namespace \n"; 431 432 OS << "#endif // GET_INSTRINFO_CTOR_DTOR\n\n"; 433 434 emitOperandNameMappings(OS, Target, NumberedInstructions); 435} 436 437void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, 438 Record *InstrInfo, 439 std::map<std::vector<Record*>, unsigned> &EmittedLists, 440 const OperandInfoMapTy &OpInfo, 441 raw_ostream &OS) { 442 int MinOperands = 0; 443 if (!Inst.Operands.empty()) 444 // Each logical operand can be multiple MI operands. 445 MinOperands = Inst.Operands.back().MIOperandNo + 446 Inst.Operands.back().MINumOperands; 447 448 OS << " { "; 449 OS << Num << ",\t" << MinOperands << ",\t" 450 << Inst.Operands.NumDefs << ",\t" 451 << SchedModels.getSchedClassIdx(Inst) << ",\t" 452 << Inst.TheDef->getValueAsInt("Size") << ",\t0"; 453 454 // Emit all of the target indepedent flags... 455 if (Inst.isPseudo) OS << "|(1<<MCID::Pseudo)"; 456 if (Inst.isReturn) OS << "|(1<<MCID::Return)"; 457 if (Inst.isBranch) OS << "|(1<<MCID::Branch)"; 458 if (Inst.isIndirectBranch) OS << "|(1<<MCID::IndirectBranch)"; 459 if (Inst.isCompare) OS << "|(1<<MCID::Compare)"; 460 if (Inst.isMoveImm) OS << "|(1<<MCID::MoveImm)"; 461 if (Inst.isBitcast) OS << "|(1<<MCID::Bitcast)"; 462 if (Inst.isSelect) OS << "|(1<<MCID::Select)"; 463 if (Inst.isBarrier) OS << "|(1<<MCID::Barrier)"; 464 if (Inst.hasDelaySlot) OS << "|(1<<MCID::DelaySlot)"; 465 if (Inst.isCall) OS << "|(1<<MCID::Call)"; 466 if (Inst.canFoldAsLoad) OS << "|(1<<MCID::FoldableAsLoad)"; 467 if (Inst.mayLoad) OS << "|(1<<MCID::MayLoad)"; 468 if (Inst.mayStore) OS << "|(1<<MCID::MayStore)"; 469 if (Inst.isPredicable) OS << "|(1<<MCID::Predicable)"; 470 if (Inst.isConvertibleToThreeAddress) OS << "|(1<<MCID::ConvertibleTo3Addr)"; 471 if (Inst.isCommutable) OS << "|(1<<MCID::Commutable)"; 472 if (Inst.isTerminator) OS << "|(1<<MCID::Terminator)"; 473 if (Inst.isReMaterializable) OS << "|(1<<MCID::Rematerializable)"; 474 if (Inst.isNotDuplicable) OS << "|(1<<MCID::NotDuplicable)"; 475 if (Inst.Operands.hasOptionalDef) OS << "|(1<<MCID::HasOptionalDef)"; 476 if (Inst.usesCustomInserter) OS << "|(1<<MCID::UsesCustomInserter)"; 477 if (Inst.hasPostISelHook) OS << "|(1<<MCID::HasPostISelHook)"; 478 if (Inst.Operands.isVariadic)OS << "|(1<<MCID::Variadic)"; 479 if (Inst.hasSideEffects) OS << "|(1<<MCID::UnmodeledSideEffects)"; 480 if (Inst.isAsCheapAsAMove) OS << "|(1<<MCID::CheapAsAMove)"; 481 if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<MCID::ExtraSrcRegAllocReq)"; 482 if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<MCID::ExtraDefRegAllocReq)"; 483 484 // Emit all of the target-specific flags... 485 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags"); 486 if (!TSF) 487 PrintFatalError("no TSFlags?"); 488 uint64_t Value = 0; 489 for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) { 490 if (BitInit *Bit = dyn_cast<BitInit>(TSF->getBit(i))) 491 Value |= uint64_t(Bit->getValue()) << i; 492 else 493 PrintFatalError("Invalid TSFlags bit in " + Inst.TheDef->getName()); 494 } 495 OS << ", 0x"; 496 OS.write_hex(Value); 497 OS << "ULL, "; 498 499 // Emit the implicit uses and defs lists... 500 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses"); 501 if (UseList.empty()) 502 OS << "NULL, "; 503 else 504 OS << "ImplicitList" << EmittedLists[UseList] << ", "; 505 506 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs"); 507 if (DefList.empty()) 508 OS << "NULL, "; 509 else 510 OS << "ImplicitList" << EmittedLists[DefList] << ", "; 511 512 // Emit the operand info. 513 std::vector<std::string> OperandInfo = GetOperandInfo(Inst); 514 if (OperandInfo.empty()) 515 OS << "0"; 516 else 517 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second; 518 519 CodeGenTarget &Target = CDP.getTargetInfo(); 520 if (Inst.HasComplexDeprecationPredicate) 521 // Emit a function pointer to the complex predicate method. 522 OS << ",0" 523 << ",&get" << Inst.DeprecatedReason << "DeprecationInfo"; 524 else if (!Inst.DeprecatedReason.empty()) 525 // Emit the Subtarget feature. 526 OS << "," << Target.getInstNamespace() << "::" << Inst.DeprecatedReason 527 << ",0"; 528 else 529 // Instruction isn't deprecated. 530 OS << ",0,0"; 531 532 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n"; 533} 534 535// emitEnums - Print out enum values for all of the instructions. 536void InstrInfoEmitter::emitEnums(raw_ostream &OS) { 537 538 OS << "\n#ifdef GET_INSTRINFO_ENUM\n"; 539 OS << "#undef GET_INSTRINFO_ENUM\n"; 540 541 OS << "namespace llvm {\n\n"; 542 543 CodeGenTarget Target(Records); 544 545 // We must emit the PHI opcode first... 546 std::string Namespace = Target.getInstNamespace(); 547 548 if (Namespace.empty()) { 549 fprintf(stderr, "No instructions defined!\n"); 550 exit(1); 551 } 552 553 const std::vector<const CodeGenInstruction*> &NumberedInstructions = 554 Target.getInstructionsByEnumValue(); 555 556 OS << "namespace " << Namespace << " {\n"; 557 OS << " enum {\n"; 558 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 559 OS << " " << NumberedInstructions[i]->TheDef->getName() 560 << "\t= " << i << ",\n"; 561 } 562 OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n"; 563 OS << " };\n"; 564 OS << "namespace Sched {\n"; 565 OS << " enum {\n"; 566 for (unsigned i = 0, e = SchedModels.numInstrSchedClasses(); i != e; ++i) { 567 OS << " " << SchedModels.getSchedClass(i).Name 568 << "\t= " << i << ",\n"; 569 } 570 OS << " SCHED_LIST_END = " << SchedModels.numInstrSchedClasses() << "\n"; 571 OS << " };\n}\n}\n"; 572 OS << "} // End llvm namespace \n"; 573 574 OS << "#endif // GET_INSTRINFO_ENUM\n\n"; 575} 576 577namespace llvm { 578 579void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) { 580 InstrInfoEmitter(RK).run(OS); 581 EmitMapTable(RK, OS); 582} 583 584} // End llvm namespace 585