InstrInfoEmitter.cpp revision 60f09928a0d22d5927ff0a40fe9163cf1ba1014a 
1//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend is responsible for emitting a description of the target
11// instruction set for the code generator.
12//
13//===----------------------------------------------------------------------===//
14
15#include "InstrInfoEmitter.h"
16#include "CodeGenTarget.h"
17#include "Record.h"
18#include <algorithm>
19using namespace llvm;
20
21// runEnums - Print out enum values for all of the instructions.
22void InstrInfoEmitter::runEnums(std::ostream &OS) {
23  EmitSourceFileHeader("Target Instruction Enum Values", OS);
24  OS << "namespace llvm {\n\n";
25
26  CodeGenTarget Target;
27
28  // We must emit the PHI opcode first...
29  std::string Namespace;
30  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
31       E = Target.inst_end(); II != E; ++II) {
32    if (II->second.Namespace != "TargetInstrInfo") {
33      Namespace = II->second.Namespace;
34      break;
35    }
36  }
37
38  if (Namespace.empty()) {
39    std::cerr << "No instructions defined!\n";
40    exit(1);
41  }
42
43  std::vector<const CodeGenInstruction*> NumberedInstructions;
44  Target.getInstructionsByEnumValue(NumberedInstructions);
45
46  OS << "namespace " << Namespace << " {\n";
47  OS << "  enum {\n";
48  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
49    OS << "    " << NumberedInstructions[i]->TheDef->getName()
50       << "\t= " << i << ",\n";
51  }
52  OS << "    INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
53  OS << "  };\n}\n";
54  OS << "} // End llvm namespace \n";
55}
56
57void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
58                                    unsigned Num, std::ostream &OS) const {
59  OS << "static const unsigned ImplicitList" << Num << "[] = { ";
60  for (unsigned i = 0, e = Uses.size(); i != e; ++i)
61    OS << getQualifiedName(Uses[i]) << ", ";
62  OS << "0 };\n";
63}
64
65static std::vector<Record*> GetOperandInfo(const CodeGenInstruction &Inst) {
66  std::vector<Record*> Result;
67  for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
68    if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass")) {
69      Result.push_back(Inst.OperandList[i].Rec);
70    } else {
71      // This might be a multiple operand thing.
72      // Targets like X86 have registers in their multi-operand operands.
73      DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
74      unsigned NumDefs = MIOI->getNumArgs();
75      for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
76        if (NumDefs <= j) {
77          Result.push_back(0);
78        } else {
79          DefInit *Def = dynamic_cast<DefInit*>(MIOI->getArg(j));
80          Result.push_back(Def ? Def->getDef() : 0);
81        }
82      }
83    }
84  }
85  return Result;
86}
87
88
89// run - Emit the main instruction description records for the target...
90void InstrInfoEmitter::run(std::ostream &OS) {
91  GatherItinClasses();
92
93  EmitSourceFileHeader("Target Instruction Descriptors", OS);
94  OS << "namespace llvm {\n\n";
95
96  CodeGenTarget Target;
97  const std::string &TargetName = Target.getName();
98  Record *InstrInfo = Target.getInstructionSet();
99
100  // Emit empty implicit uses and defs lists
101  OS << "static const unsigned EmptyImpList[] = { 0 };\n";
102
103  // Keep track of all of the def lists we have emitted already.
104  std::map<std::vector<Record*>, unsigned> EmittedLists;
105  unsigned ListNumber = 0;
106
107  // Emit all of the instruction's implicit uses and defs.
108  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
109         E = Target.inst_end(); II != E; ++II) {
110    Record *Inst = II->second.TheDef;
111    std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
112    if (!Uses.empty()) {
113      unsigned &IL = EmittedLists[Uses];
114      if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
115    }
116    std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
117    if (!Defs.empty()) {
118      unsigned &IL = EmittedLists[Defs];
119      if (!IL) printDefList(Defs, IL = ++ListNumber, OS);
120    }
121  }
122
123  std::map<std::vector<Record*>, unsigned> OperandInfosEmitted;
124  unsigned OperandListNum = 0;
125  OperandInfosEmitted[std::vector<Record*>()] = ++OperandListNum;
126
127  // Emit all of the operand info records.
128  OS << "\n";
129  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
130       E = Target.inst_end(); II != E; ++II) {
131    std::vector<Record*> OperandInfo = GetOperandInfo(II->second);
132    unsigned &N = OperandInfosEmitted[OperandInfo];
133    if (N == 0) {
134      N = ++OperandListNum;
135      OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
136      for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) {
137        Record *RC = OperandInfo[i];
138        // FIXME: We only care about register operands for now.
139        if (RC && RC->isSubClassOf("RegisterClass"))
140          OS << "{ " << getQualifiedName(RC) << "RegClassID, 0 }, ";
141        else if (RC && RC->getName() == "ptr_rc")
142          // Ptr value whose register class is resolved via callback.
143          OS << "{ 0, 1 }, ";
144        else
145          OS << "{ 0, 0 }, ";
146      }
147      OS << "};\n";
148    }
149  }
150
151  // Emit all of the TargetInstrDescriptor records in their ENUM ordering.
152  //
153  OS << "\nstatic const TargetInstrDescriptor " << TargetName
154     << "Insts[] = {\n";
155  std::vector<const CodeGenInstruction*> NumberedInstructions;
156  Target.getInstructionsByEnumValue(NumberedInstructions);
157
158  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
159    emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
160               OperandInfosEmitted, OS);
161  OS << "};\n";
162  OS << "} // End llvm namespace \n";
163}
164
165void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
166                                  Record *InstrInfo,
167                         std::map<std::vector<Record*>, unsigned> &EmittedLists,
168                               std::map<std::vector<Record*>, unsigned> &OpInfo,
169                                  std::ostream &OS) {
170  int MinOperands;
171  if (!Inst.OperandList.empty())
172    // Each logical operand can be multiple MI operands.
173    MinOperands = Inst.OperandList.back().MIOperandNo +
174                  Inst.OperandList.back().MINumOperands;
175  else
176    MinOperands = 0;
177
178  OS << "  { \"";
179  if (Inst.Name.empty())
180    OS << Inst.TheDef->getName();
181  else
182    OS << Inst.Name;
183
184  unsigned ItinClass = !IsItineraries ? 0 :
185            ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
186
187  OS << "\",\t" << MinOperands << ", " << ItinClass
188     << ", 0";
189
190  // Try to determine (from the pattern), if the instruction is a store.
191  bool isStore = false;
192  if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) {
193    ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
194    if (LI && LI->getSize() > 0) {
195      DagInit *Dag = (DagInit *)LI->getElement(0);
196      DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
197      if (OpDef) {
198        Record *Operator = OpDef->getDef();
199        if (Operator->isSubClassOf("SDNode")) {
200          const std::string Opcode = Operator->getValueAsString("Opcode");
201          if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
202            isStore = true;
203        }
204      }
205    }
206  }
207
208  // Emit all of the target indepedent flags...
209  if (Inst.isReturn)     OS << "|M_RET_FLAG";
210  if (Inst.isBranch)     OS << "|M_BRANCH_FLAG";
211  if (Inst.isBarrier)    OS << "|M_BARRIER_FLAG";
212  if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
213  if (Inst.isCall)       OS << "|M_CALL_FLAG";
214  if (Inst.isLoad)       OS << "|M_LOAD_FLAG";
215  if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
216  if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
217  if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
218  if (Inst.isCommutable) OS << "|M_COMMUTABLE";
219  if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
220  if (Inst.usesCustomDAGSchedInserter)
221    OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
222  if (Inst.hasVariableNumberOfOperands)
223    OS << "|M_VARIABLE_OPS";
224  OS << ", 0";
225
226  // Emit all of the target-specific flags...
227  ListInit *LI    = InstrInfo->getValueAsListInit("TSFlagsFields");
228  ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
229  if (LI->getSize() != Shift->getSize())
230    throw "Lengths of " + InstrInfo->getName() +
231          ":(TargetInfoFields, TargetInfoPositions) must be equal!";
232
233  for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
234    emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
235                     dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
236
237  OS << ", ";
238
239  // Emit the implicit uses and defs lists...
240  std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
241  if (UseList.empty())
242    OS << "EmptyImpList, ";
243  else
244    OS << "ImplicitList" << EmittedLists[UseList] << ", ";
245
246  std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
247  if (DefList.empty())
248    OS << "EmptyImpList, ";
249  else
250    OS << "ImplicitList" << EmittedLists[DefList] << ", ";
251
252  // Emit the operand info.
253  std::vector<Record*> OperandInfo = GetOperandInfo(Inst);
254  if (OperandInfo.empty())
255    OS << "0";
256  else
257    OS << "OperandInfo" << OpInfo[OperandInfo];
258
259  OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
260}
261
262struct LessRecord {
263  bool operator()(const Record *Rec1, const Record *Rec2) const {
264    return Rec1->getName() < Rec2->getName();
265  }
266};
267void InstrInfoEmitter::GatherItinClasses() {
268  std::vector<Record*> DefList =
269                          Records.getAllDerivedDefinitions("InstrItinClass");
270  IsItineraries = !DefList.empty();
271
272  if (!IsItineraries) return;
273
274  std::sort(DefList.begin(), DefList.end(), LessRecord());
275
276  for (unsigned i = 0, N = DefList.size(); i < N; i++) {
277    Record *Def = DefList[i];
278    ItinClassMap[Def->getName()] = i;
279  }
280}
281
282unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) {
283  return ItinClassMap[ItinName];
284}
285
286void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
287                                        IntInit *ShiftInt, std::ostream &OS) {
288  if (Val == 0 || ShiftInt == 0)
289    throw std::string("Illegal value or shift amount in TargetInfo*!");
290  RecordVal *RV = R->getValue(Val->getValue());
291  int Shift = ShiftInt->getValue();
292
293  if (RV == 0 || RV->getValue() == 0) {
294    // This isn't an error if this is a builtin instruction.
295    if (R->getName() != "PHI" && R->getName() != "INLINEASM")
296      throw R->getName() + " doesn't have a field named '" +
297            Val->getValue() + "'!";
298    return;
299  }
300
301  Init *Value = RV->getValue();
302  if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
303    if (BI->getValue()) OS << "|(1<<" << Shift << ")";
304    return;
305  } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
306    // Convert the Bits to an integer to print...
307    Init *I = BI->convertInitializerTo(new IntRecTy());
308    if (I)
309      if (IntInit *II = dynamic_cast<IntInit*>(I)) {
310        if (II->getValue()) {
311          if (Shift)
312            OS << "|(" << II->getValue() << "<<" << Shift << ")";
313          else
314            OS << "|" << II->getValue();
315        }
316        return;
317      }
318
319  } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
320    if (II->getValue()) {
321      if (Shift)
322        OS << "|(" << II->getValue() << "<<" << Shift << ")";
323      else
324        OS << II->getValue();
325    }
326    return;
327  }
328
329  std::cerr << "Unhandled initializer: " << *Val << "\n";
330  throw "In record '" + R->getName() + "' for TSFlag emission.";
331}
332
333