InstrInfoEmitter.cpp revision 6cee630070b1a7183ed56a8404e812629f5ca538 
1//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend is responsible for emitting a description of the target
11// instruction set for the code generator.
12//
13//===----------------------------------------------------------------------===//
14
15#include "InstrInfoEmitter.h"
16#include "CodeGenTarget.h"
17#include "Record.h"
18#include <algorithm>
19using namespace llvm;
20
21// runEnums - Print out enum values for all of the instructions.
22void InstrInfoEmitter::runEnums(std::ostream &OS) {
23  EmitSourceFileHeader("Target Instruction Enum Values", OS);
24  OS << "namespace llvm {\n\n";
25
26  CodeGenTarget Target;
27
28  // We must emit the PHI opcode first...
29  Record *InstrInfo = Target.getInstructionSet();
30
31  std::string Namespace = Target.inst_begin()->second.Namespace;
32
33  if (!Namespace.empty())
34    OS << "namespace " << Namespace << " {\n";
35  OS << "  enum {\n";
36
37  std::vector<const CodeGenInstruction*> NumberedInstructions;
38  Target.getInstructionsByEnumValue(NumberedInstructions);
39
40  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
41    OS << "    " << NumberedInstructions[i]->TheDef->getName()
42       << ", \t// " << i << "\n";
43  }
44  OS << "    INSTRUCTION_LIST_END\n";
45  OS << "  };\n";
46  if (!Namespace.empty())
47    OS << "}\n";
48  OS << "} // End llvm namespace \n";
49}
50
51void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
52                                    unsigned Num, std::ostream &OS) const {
53  OS << "static const unsigned ImplicitList" << Num << "[] = { ";
54  for (unsigned i = 0, e = Uses.size(); i != e; ++i)
55    OS << getQualifiedName(Uses[i]) << ", ";
56  OS << "0 };\n";
57}
58
59static std::vector<Record*> GetOperandInfo(const CodeGenInstruction &Inst) {
60  std::vector<Record*> Result;
61  if (Inst.hasVariableNumberOfOperands)
62    return Result;  // No info for variable operand instrs.
63
64  for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
65    if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass"))
66      Result.push_back(Inst.OperandList[i].Rec);
67    else {
68      // This might be a multiple operand thing.
69      // FIXME: Targets like X86 have registers in their multi-operand operands.
70      for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j)
71        Result.push_back(0);
72    }
73  }
74  return Result;
75}
76
77
78// run - Emit the main instruction description records for the target...
79void InstrInfoEmitter::run(std::ostream &OS) {
80  GatherItinClasses();
81
82  EmitSourceFileHeader("Target Instruction Descriptors", OS);
83  OS << "namespace llvm {\n\n";
84
85  CodeGenTarget Target;
86  const std::string &TargetName = Target.getName();
87  Record *InstrInfo = Target.getInstructionSet();
88  Record *PHI = InstrInfo->getValueAsDef("PHIInst");
89
90  // Emit empty implicit uses and defs lists
91  OS << "static const unsigned EmptyImpList[] = { 0 };\n";
92
93  // Keep track of all of the def lists we have emitted already.
94  std::map<std::vector<Record*>, unsigned> EmittedLists;
95  unsigned ListNumber = 0;
96
97  // Emit all of the instruction's implicit uses and defs.
98  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
99         E = Target.inst_end(); II != E; ++II) {
100    Record *Inst = II->second.TheDef;
101    std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
102    if (!Uses.empty()) {
103      unsigned &IL = EmittedLists[Uses];
104      if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
105    }
106    std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
107    if (!Defs.empty()) {
108      unsigned &IL = EmittedLists[Defs];
109      if (!IL) printDefList(Defs, IL = ++ListNumber, OS);
110    }
111  }
112
113  std::map<std::vector<Record*>, unsigned> OperandInfosEmitted;
114  unsigned OperandListNum = 0;
115  OperandInfosEmitted[std::vector<Record*>()] = ++OperandListNum;
116
117  // Emit all of the operand info records.
118  OS << "\n";
119  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
120       E = Target.inst_end(); II != E; ++II) {
121    std::vector<Record*> OperandInfo = GetOperandInfo(II->second);
122    unsigned &N = OperandInfosEmitted[OperandInfo];
123    if (N == 0) {
124      N = ++OperandListNum;
125      OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
126      for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) {
127        if (Record *RC = OperandInfo[i]) {
128          OS << "{ &" << getQualifiedName(RC) << "RegClass }, ";
129        } else {
130          OS << "{ 0 }, ";
131        }
132      }
133      OS << "};\n";
134    }
135  }
136
137  // Emit all of the TargetInstrDescriptor records.
138  //
139  OS << "\nstatic const TargetInstrDescriptor " << TargetName
140     << "Insts[] = {\n";
141  emitRecord(Target.getPHIInstruction(), 0, InstrInfo, EmittedLists,
142             OperandInfosEmitted, OS);
143
144  unsigned i = 0;
145  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
146         E = Target.inst_end(); II != E; ++II)
147    if (II->second.TheDef != PHI)
148      emitRecord(II->second, ++i, InstrInfo, EmittedLists,
149                 OperandInfosEmitted, OS);
150  OS << "};\n";
151  OS << "} // End llvm namespace \n";
152}
153
154void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
155                                  Record *InstrInfo,
156                         std::map<std::vector<Record*>, unsigned> &EmittedLists,
157                               std::map<std::vector<Record*>, unsigned> &OpInfo,
158                                  std::ostream &OS) {
159  int NumOperands;
160  if (Inst.hasVariableNumberOfOperands)
161    NumOperands = -1;
162  else if (!Inst.OperandList.empty())
163    // Each logical operand can be multiple MI operands.
164    NumOperands = Inst.OperandList.back().MIOperandNo +
165                  Inst.OperandList.back().MINumOperands;
166  else
167    NumOperands = 0;
168
169  OS << "  { \"";
170  if (Inst.Name.empty())
171    OS << Inst.TheDef->getName();
172  else
173    OS << Inst.Name;
174
175  unsigned ItinClass = !IsItineraries ? 0 :
176            ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
177
178  OS << "\",\t" << NumOperands << ", -1, 0, false, 0, 0, "
179     << ItinClass
180     << ", 0";
181
182  // Emit all of the target indepedent flags...
183  if (Inst.isReturn)     OS << "|M_RET_FLAG";
184  if (Inst.isBranch)     OS << "|M_BRANCH_FLAG";
185  if (Inst.isBarrier)    OS << "|M_BARRIER_FLAG";
186  if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
187  if (Inst.isCall)       OS << "|M_CALL_FLAG";
188  if (Inst.isLoad)       OS << "|M_LOAD_FLAG";
189  if (Inst.isStore)      OS << "|M_STORE_FLAG";
190  if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
191  if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
192  if (Inst.isCommutable) OS << "|M_COMMUTABLE";
193  if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
194  if (Inst.usesCustomDAGSchedInserter)
195    OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
196  OS << ", 0";
197
198  // Emit all of the target-specific flags...
199  ListInit *LI    = InstrInfo->getValueAsListInit("TSFlagsFields");
200  ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
201  if (LI->getSize() != Shift->getSize())
202    throw "Lengths of " + InstrInfo->getName() +
203          ":(TargetInfoFields, TargetInfoPositions) must be equal!";
204
205  for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
206    emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
207                     dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
208
209  OS << ", ";
210
211  // Emit the implicit uses and defs lists...
212  std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
213  if (UseList.empty())
214    OS << "EmptyImpList, ";
215  else
216    OS << "ImplicitList" << EmittedLists[UseList] << ", ";
217
218  std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
219  if (DefList.empty())
220    OS << "EmptyImpList, ";
221  else
222    OS << "ImplicitList" << EmittedLists[DefList] << ", ";
223
224  // Emit the operand info.
225  std::vector<Record*> OperandInfo = GetOperandInfo(Inst);
226  if (OperandInfo.empty())
227    OS << "0";
228  else
229    OS << "OperandInfo" << OpInfo[OperandInfo];
230
231  OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
232}
233
234struct LessRecord {
235  bool operator()(const Record *Rec1, const Record *Rec2) const {
236    return Rec1->getName() < Rec2->getName();
237  }
238};
239void InstrInfoEmitter::GatherItinClasses() {
240  std::vector<Record*> DefList =
241                          Records.getAllDerivedDefinitions("InstrItinClass");
242  IsItineraries = !DefList.empty();
243
244  if (!IsItineraries) return;
245
246  sort(DefList.begin(), DefList.end(), LessRecord());
247
248  for (unsigned i = 0, N = DefList.size(); i < N; i++) {
249    Record *Def = DefList[i];
250    ItinClassMap[Def->getName()] = i;
251  }
252}
253
254unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) {
255  return ItinClassMap[ItinName];
256}
257
258void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
259                                        IntInit *ShiftInt, std::ostream &OS) {
260  if (Val == 0 || ShiftInt == 0)
261    throw std::string("Illegal value or shift amount in TargetInfo*!");
262  RecordVal *RV = R->getValue(Val->getValue());
263  int Shift = ShiftInt->getValue();
264
265  if (RV == 0 || RV->getValue() == 0)
266    throw R->getName() + " doesn't have a field named '" + Val->getValue()+"'!";
267
268  Init *Value = RV->getValue();
269  if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
270    if (BI->getValue()) OS << "|(1<<" << Shift << ")";
271    return;
272  } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
273    // Convert the Bits to an integer to print...
274    Init *I = BI->convertInitializerTo(new IntRecTy());
275    if (I)
276      if (IntInit *II = dynamic_cast<IntInit*>(I)) {
277        if (II->getValue())
278          OS << "|(" << II->getValue() << "<<" << Shift << ")";
279        return;
280      }
281
282  } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
283    if (II->getValue()) OS << "|(" << II->getValue() << "<<" << Shift << ")";
284    return;
285  }
286
287  std::cerr << "Unhandled initializer: " << *Val << "\n";
288  throw "In record '" + R->getName() + "' for TSFlag emission.";
289}
290
291