InstrInfoEmitter.cpp revision 710e995889c71812743f3f33861c24273f4569a7
1//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend is responsible for emitting a description of the target 11// instruction set for the code generator. 12// 13//===----------------------------------------------------------------------===// 14 15#include "InstrInfoEmitter.h" 16#include "CodeGenTarget.h" 17#include "Record.h" 18#include <algorithm> 19#include <iostream> 20using namespace llvm; 21 22static void PrintDefList(const std::vector<Record*> &Uses, 23 unsigned Num, std::ostream &OS) { 24 OS << "static const unsigned ImplicitList" << Num << "[] = { "; 25 for (unsigned i = 0, e = Uses.size(); i != e; ++i) 26 OS << getQualifiedName(Uses[i]) << ", "; 27 OS << "0 };\n"; 28} 29 30//===----------------------------------------------------------------------===// 31// Instruction Itinerary Information. 32//===----------------------------------------------------------------------===// 33 34struct RecordNameComparator { 35 bool operator()(const Record *Rec1, const Record *Rec2) const { 36 return Rec1->getName() < Rec2->getName(); 37 } 38}; 39 40void InstrInfoEmitter::GatherItinClasses() { 41 std::vector<Record*> DefList = 42 Records.getAllDerivedDefinitions("InstrItinClass"); 43 std::sort(DefList.begin(), DefList.end(), RecordNameComparator()); 44 45 for (unsigned i = 0, N = DefList.size(); i < N; i++) 46 ItinClassMap[DefList[i]->getName()] = i; 47} 48 49unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) { 50 return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()]; 51} 52 53//===----------------------------------------------------------------------===// 54// Operand Info Emission. 55//===----------------------------------------------------------------------===// 56 57std::vector<std::string> 58InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { 59 std::vector<std::string> Result; 60 61 for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) { 62 // Handle aggregate operands and normal operands the same way by expanding 63 // either case into a list of operands for this op. 64 std::vector<CodeGenInstruction::OperandInfo> OperandList; 65 66 // This might be a multiple operand thing. Targets like X86 have 67 // registers in their multi-operand operands. It may also be an anonymous 68 // operand, which has a single operand, but no declared class for the 69 // operand. 70 DagInit *MIOI = Inst.OperandList[i].MIOperandInfo; 71 72 if (!MIOI || MIOI->getNumArgs() == 0) { 73 // Single, anonymous, operand. 74 OperandList.push_back(Inst.OperandList[i]); 75 } else { 76 for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) { 77 OperandList.push_back(Inst.OperandList[i]); 78 79 Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef(); 80 OperandList.back().Rec = OpR; 81 } 82 } 83 84 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) { 85 Record *OpR = OperandList[j].Rec; 86 std::string Res; 87 88 if (OpR->isSubClassOf("RegisterClass")) 89 Res += getQualifiedName(OpR) + "RegClassID, "; 90 else 91 Res += "0, "; 92 // Fill in applicable flags. 93 Res += "0"; 94 95 // Ptr value whose register class is resolved via callback. 96 if (OpR->getName() == "ptr_rc") 97 Res += "|(1<<TOI::LookupPtrRegClass)"; 98 99 // Predicate operands. Check to see if the original unexpanded operand 100 // was of type PredicateOperand. 101 if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand")) 102 Res += "|(1<<TOI::Predicate)"; 103 104 // Optional def operands. Check to see if the original unexpanded operand 105 // was of type OptionalDefOperand. 106 if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand")) 107 Res += "|(1<<TOI::OptionalDef)"; 108 109 // Fill in constraint info. 110 Res += ", " + Inst.OperandList[i].Constraints[j]; 111 Result.push_back(Res); 112 } 113 } 114 115 return Result; 116} 117 118void InstrInfoEmitter::EmitOperandInfo(std::ostream &OS, 119 OperandInfoMapTy &OperandInfoIDs) { 120 // ID #0 is for no operand info. 121 unsigned OperandListNum = 0; 122 OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum; 123 124 OS << "\n"; 125 const CodeGenTarget &Target = CDP.getTargetInfo(); 126 for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 127 E = Target.inst_end(); II != E; ++II) { 128 std::vector<std::string> OperandInfo = GetOperandInfo(II->second); 129 unsigned &N = OperandInfoIDs[OperandInfo]; 130 if (N != 0) continue; 131 132 N = ++OperandListNum; 133 OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { "; 134 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) 135 OS << "{ " << OperandInfo[i] << " }, "; 136 OS << "};\n"; 137 } 138} 139 140//===----------------------------------------------------------------------===// 141// Instruction Analysis 142//===----------------------------------------------------------------------===// 143 144class InstAnalyzer { 145 const CodeGenDAGPatterns &CDP; 146 bool &mayStore; 147 bool &mayLoad; 148 bool &NeverHasSideEffects; 149public: 150 InstAnalyzer(const CodeGenDAGPatterns &cdp, 151 bool &maystore, bool &mayload, bool &nhse) 152 : CDP(cdp), mayStore(maystore), mayLoad(mayload), NeverHasSideEffects(nhse){ 153 } 154 155 void Analyze(Record *InstRecord) { 156 const TreePattern *Pattern = CDP.getInstruction(InstRecord).getPattern(); 157 if (Pattern == 0) return; // No pattern. 158 159 // Assume there is no side-effect unless we see one. 160 NeverHasSideEffects = true; 161 162 // FIXME: Assume only the first tree is the pattern. The others are clobber 163 // nodes. 164 AnalyzeNode(Pattern->getTree(0)); 165 } 166 167private: 168 void AnalyzeNode(const TreePatternNode *N) { 169 if (N->isLeaf()) 170 return; 171 172 if (N->getOperator()->getName() != "set") { 173 // Get information about the SDNode for the operator. 174 const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator()); 175 176 // If node writes to memory, it obviously stores to memory. 177 if (OpInfo.hasProperty(SDNPMayStore)) 178 mayStore = true; 179 180 // If it reads memory, remember this. 181 if (OpInfo.hasProperty(SDNPMayLoad)) 182 mayLoad = true; 183 184 if (const CodeGenIntrinsic *IntInfo = N->getIntrinsicInfo(CDP)) { 185 // If this is an intrinsic, analyze it. 186 if (IntInfo->ModRef >= CodeGenIntrinsic::WriteArgMem) { 187 mayStore = true;// Intrinsics that can write to memory are 'mayStore'. 188 } 189 190 if (IntInfo->ModRef >= CodeGenIntrinsic::ReadArgMem) 191 mayLoad = true;// These may also load memory. 192 } 193 } 194 195 for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i) 196 AnalyzeNode(N->getChild(i)); 197 } 198 199}; 200 201void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst, 202 bool &mayStore, bool &mayLoad, 203 bool &NeverHasSideEffects) { 204 mayStore = mayLoad = NeverHasSideEffects = false; 205 206 InstAnalyzer(CDP, mayStore, mayLoad,NeverHasSideEffects).Analyze(Inst.TheDef); 207 208 // InstAnalyzer only correctly analyzes mayStore so far. 209 if (Inst.mayStore) { // If the .td file explicitly sets mayStore, use it. 210 // If we decided that this is a store from the pattern, then the .td file 211 // entry is redundant. 212 if (mayStore) 213 fprintf(stderr, 214 "Warning: mayStore flag explicitly set on instruction '%s'" 215 " but flag already inferred from pattern.\n", 216 Inst.TheDef->getName().c_str()); 217 mayStore = true; 218 } 219 220 // These two override everything. 221 mayLoad = Inst.mayLoad; 222 NeverHasSideEffects = Inst.neverHasSideEffects; 223 224#if 0 225 // If the .td file explicitly says there is no side effect, believe it. 226 if (Inst.neverHasSideEffects) 227 NeverHasSideEffects = true; 228#endif 229} 230 231 232//===----------------------------------------------------------------------===// 233// Main Output. 234//===----------------------------------------------------------------------===// 235 236// run - Emit the main instruction description records for the target... 237void InstrInfoEmitter::run(std::ostream &OS) { 238 GatherItinClasses(); 239 240 EmitSourceFileHeader("Target Instruction Descriptors", OS); 241 OS << "namespace llvm {\n\n"; 242 243 CodeGenTarget Target; 244 const std::string &TargetName = Target.getName(); 245 Record *InstrInfo = Target.getInstructionSet(); 246 247 // Keep track of all of the def lists we have emitted already. 248 std::map<std::vector<Record*>, unsigned> EmittedLists; 249 unsigned ListNumber = 0; 250 251 // Emit all of the instruction's implicit uses and defs. 252 for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 253 E = Target.inst_end(); II != E; ++II) { 254 Record *Inst = II->second.TheDef; 255 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses"); 256 if (!Uses.empty()) { 257 unsigned &IL = EmittedLists[Uses]; 258 if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS); 259 } 260 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs"); 261 if (!Defs.empty()) { 262 unsigned &IL = EmittedLists[Defs]; 263 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS); 264 } 265 } 266 267 OperandInfoMapTy OperandInfoIDs; 268 269 // Emit all of the operand info records. 270 EmitOperandInfo(OS, OperandInfoIDs); 271 272 // Emit all of the TargetInstrDesc records in their ENUM ordering. 273 // 274 OS << "\nstatic const TargetInstrDesc " << TargetName 275 << "Insts[] = {\n"; 276 std::vector<const CodeGenInstruction*> NumberedInstructions; 277 Target.getInstructionsByEnumValue(NumberedInstructions); 278 279 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) 280 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists, 281 OperandInfoIDs, OS); 282 OS << "};\n"; 283 OS << "} // End llvm namespace \n"; 284} 285 286void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, 287 Record *InstrInfo, 288 std::map<std::vector<Record*>, unsigned> &EmittedLists, 289 const OperandInfoMapTy &OpInfo, 290 std::ostream &OS) { 291 // Determine properties of the instruction from its pattern. 292 bool mayStore, mayLoad, NeverHasSideEffects; 293 InferFromPattern(Inst, mayStore, mayLoad, NeverHasSideEffects); 294 295 if (NeverHasSideEffects && Inst.mayHaveSideEffects) { 296 std::cerr << "error: Instruction '" << Inst.TheDef->getName() 297 << "' is marked with 'mayHaveSideEffects', but it can never have them!\n"; 298 exit(1); 299 } 300 301 int MinOperands = 0; 302 if (!Inst.OperandList.empty()) 303 // Each logical operand can be multiple MI operands. 304 MinOperands = Inst.OperandList.back().MIOperandNo + 305 Inst.OperandList.back().MINumOperands; 306 307 OS << " { "; 308 OS << Num << ",\t" << MinOperands << ",\t" 309 << Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef) 310 << ",\t\"" << Inst.TheDef->getName() << "\", 0"; 311 312 // Emit all of the target indepedent flags... 313 if (Inst.isReturn) OS << "|(1<<TID::Return)"; 314 if (Inst.isBranch) OS << "|(1<<TID::Branch)"; 315 if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)"; 316 if (Inst.isBarrier) OS << "|(1<<TID::Barrier)"; 317 if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)"; 318 if (Inst.isCall) OS << "|(1<<TID::Call)"; 319 if (Inst.isSimpleLoad) OS << "|(1<<TID::SimpleLoad)"; 320 if (mayLoad) OS << "|(1<<TID::MayLoad)"; 321 if (mayStore) OS << "|(1<<TID::MayStore)"; 322 if (Inst.isImplicitDef)OS << "|(1<<TID::ImplicitDef)"; 323 if (Inst.isPredicable) OS << "|(1<<TID::Predicable)"; 324 if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)"; 325 if (Inst.isCommutable) OS << "|(1<<TID::Commutable)"; 326 if (Inst.isTerminator) OS << "|(1<<TID::Terminator)"; 327 if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)"; 328 if (Inst.isNotDuplicable) OS << "|(1<<TID::NotDuplicable)"; 329 if (Inst.hasOptionalDef) OS << "|(1<<TID::HasOptionalDef)"; 330 if (Inst.usesCustomDAGSchedInserter) 331 OS << "|(1<<TID::UsesCustomDAGSchedInserter)"; 332 if (Inst.isVariadic) OS << "|(1<<TID::Variadic)"; 333 if (Inst.mayHaveSideEffects) OS << "|(1<<TID::MayHaveSideEffects)"; 334 if (NeverHasSideEffects) OS << "|(1<<TID::NeverHasSideEffects)"; 335 OS << ", 0"; 336 337 // Emit all of the target-specific flags... 338 ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields"); 339 ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts"); 340 if (LI->getSize() != Shift->getSize()) 341 throw "Lengths of " + InstrInfo->getName() + 342 ":(TargetInfoFields, TargetInfoPositions) must be equal!"; 343 344 for (unsigned i = 0, e = LI->getSize(); i != e; ++i) 345 emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)), 346 dynamic_cast<IntInit*>(Shift->getElement(i)), OS); 347 348 OS << ", "; 349 350 // Emit the implicit uses and defs lists... 351 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses"); 352 if (UseList.empty()) 353 OS << "NULL, "; 354 else 355 OS << "ImplicitList" << EmittedLists[UseList] << ", "; 356 357 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs"); 358 if (DefList.empty()) 359 OS << "NULL, "; 360 else 361 OS << "ImplicitList" << EmittedLists[DefList] << ", "; 362 363 // Emit the operand info. 364 std::vector<std::string> OperandInfo = GetOperandInfo(Inst); 365 if (OperandInfo.empty()) 366 OS << "0"; 367 else 368 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second; 369 370 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n"; 371} 372 373 374void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val, 375 IntInit *ShiftInt, std::ostream &OS) { 376 if (Val == 0 || ShiftInt == 0) 377 throw std::string("Illegal value or shift amount in TargetInfo*!"); 378 RecordVal *RV = R->getValue(Val->getValue()); 379 int Shift = ShiftInt->getValue(); 380 381 if (RV == 0 || RV->getValue() == 0) { 382 // This isn't an error if this is a builtin instruction. 383 if (R->getName() != "PHI" && 384 R->getName() != "INLINEASM" && 385 R->getName() != "LABEL" && 386 R->getName() != "EXTRACT_SUBREG" && 387 R->getName() != "INSERT_SUBREG") 388 throw R->getName() + " doesn't have a field named '" + 389 Val->getValue() + "'!"; 390 return; 391 } 392 393 Init *Value = RV->getValue(); 394 if (BitInit *BI = dynamic_cast<BitInit*>(Value)) { 395 if (BI->getValue()) OS << "|(1<<" << Shift << ")"; 396 return; 397 } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) { 398 // Convert the Bits to an integer to print... 399 Init *I = BI->convertInitializerTo(new IntRecTy()); 400 if (I) 401 if (IntInit *II = dynamic_cast<IntInit*>(I)) { 402 if (II->getValue()) { 403 if (Shift) 404 OS << "|(" << II->getValue() << "<<" << Shift << ")"; 405 else 406 OS << "|" << II->getValue(); 407 } 408 return; 409 } 410 411 } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) { 412 if (II->getValue()) { 413 if (Shift) 414 OS << "|(" << II->getValue() << "<<" << Shift << ")"; 415 else 416 OS << II->getValue(); 417 } 418 return; 419 } 420 421 std::cerr << "Unhandled initializer: " << *Val << "\n"; 422 throw "In record '" + R->getName() + "' for TSFlag emission."; 423} 424 425