InstrInfoEmitter.cpp revision b5910820ce8608b75cb88e6c4efd2d1a5858159a 
1//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend is responsible for emitting a description of the target
11// instruction set for the code generator.
12//
13//===----------------------------------------------------------------------===//
14
15#include "InstrInfoEmitter.h"
16#include "CodeGenTarget.h"
17#include "llvm/Target/TargetInstrInfo.h"
18#include "Record.h"
19#include <algorithm>
20using namespace llvm;
21
22// runEnums - Print out enum values for all of the instructions.
23void InstrInfoEmitter::runEnums(std::ostream &OS) {
24  EmitSourceFileHeader("Target Instruction Enum Values", OS);
25  OS << "namespace llvm {\n\n";
26
27  CodeGenTarget Target;
28
29  // We must emit the PHI opcode first...
30  std::string Namespace;
31  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
32       E = Target.inst_end(); II != E; ++II) {
33    if (II->second.Namespace != "TargetInstrInfo") {
34      Namespace = II->second.Namespace;
35      break;
36    }
37  }
38
39  if (Namespace.empty()) {
40    cerr << "No instructions defined!\n";
41    exit(1);
42  }
43
44  std::vector<const CodeGenInstruction*> NumberedInstructions;
45  Target.getInstructionsByEnumValue(NumberedInstructions);
46
47  OS << "namespace " << Namespace << " {\n";
48  OS << "  enum {\n";
49  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
50    OS << "    " << NumberedInstructions[i]->TheDef->getName()
51       << "\t= " << i << ",\n";
52  }
53  OS << "    INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
54  OS << "  };\n}\n";
55  OS << "} // End llvm namespace \n";
56}
57
58void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
59                                    unsigned Num, std::ostream &OS) const {
60  OS << "static const unsigned ImplicitList" << Num << "[] = { ";
61  for (unsigned i = 0, e = Uses.size(); i != e; ++i)
62    OS << getQualifiedName(Uses[i]) << ", ";
63  OS << "0 };\n";
64}
65
66std::vector<std::string>
67InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
68  std::vector<std::string> Result;
69
70  for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
71    // Handle aggregate operands and normal operands the same way by expanding
72    // either case into a list of operands for this op.
73    std::vector<CodeGenInstruction::OperandInfo> OperandList;
74
75    // This might be a multiple operand thing.  Targets like X86 have
76    // registers in their multi-operand operands.  It may also be an anonymous
77    // operand, which has a single operand, but no declared class for the
78    // operand.
79    DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
80
81    if (!MIOI || MIOI->getNumArgs() == 0) {
82      // Single, anonymous, operand.
83      OperandList.push_back(Inst.OperandList[i]);
84    } else {
85      for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
86        OperandList.push_back(Inst.OperandList[i]);
87
88        Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
89        OperandList.back().Rec = OpR;
90      }
91    }
92
93    for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
94      Record *OpR = OperandList[j].Rec;
95      std::string Res;
96
97      if (OpR->isSubClassOf("RegisterClass"))
98        Res += getQualifiedName(OpR) + "RegClassID, ";
99      else
100        Res += "0, ";
101      // Fill in applicable flags.
102      Res += "0";
103
104      // Ptr value whose register class is resolved via callback.
105      if (OpR->getName() == "ptr_rc")
106        Res += "|M_LOOK_UP_PTR_REG_CLASS";
107
108      // Predicate operands.  Check to see if the original unexpanded operand
109      // was of type PredicateOperand.
110      if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
111        Res += "|M_PREDICATE_OPERAND";
112
113      // Optional def operands.  Check to see if the original unexpanded operand
114      // was of type OptionalDefOperand.
115      if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand"))
116        Res += "|M_OPTIONAL_DEF_OPERAND";
117
118      // Fill in constraint info.
119      Res += ", " + Inst.OperandList[i].Constraints[j];
120      Result.push_back(Res);
121    }
122  }
123
124  return Result;
125}
126
127
128// run - Emit the main instruction description records for the target...
129void InstrInfoEmitter::run(std::ostream &OS) {
130  GatherItinClasses();
131
132  EmitSourceFileHeader("Target Instruction Descriptors", OS);
133  OS << "namespace llvm {\n\n";
134
135  CodeGenTarget Target;
136  const std::string &TargetName = Target.getName();
137  Record *InstrInfo = Target.getInstructionSet();
138
139  // Keep track of all of the def lists we have emitted already.
140  std::map<std::vector<Record*>, unsigned> EmittedLists;
141  unsigned ListNumber = 0;
142
143  // Emit all of the instruction's implicit uses and defs.
144  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
145         E = Target.inst_end(); II != E; ++II) {
146    Record *Inst = II->second.TheDef;
147    std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
148    if (!Uses.empty()) {
149      unsigned &IL = EmittedLists[Uses];
150      if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
151    }
152    std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
153    if (!Defs.empty()) {
154      unsigned &IL = EmittedLists[Defs];
155      if (!IL) printDefList(Defs, IL = ++ListNumber, OS);
156    }
157  }
158
159  std::map<std::vector<std::string>, unsigned> OperandInfosEmitted;
160  unsigned OperandListNum = 0;
161  OperandInfosEmitted[std::vector<std::string>()] = ++OperandListNum;
162
163  // Emit all of the operand info records.
164  OS << "\n";
165  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
166       E = Target.inst_end(); II != E; ++II) {
167    std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
168    unsigned &N = OperandInfosEmitted[OperandInfo];
169    if (N == 0) {
170      N = ++OperandListNum;
171      OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
172      for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
173        OS << "{ " << OperandInfo[i] << " }, ";
174      OS << "};\n";
175    }
176  }
177
178  // Emit all of the TargetInstrDescriptor records in their ENUM ordering.
179  //
180  OS << "\nstatic const TargetInstrDescriptor " << TargetName
181     << "Insts[] = {\n";
182  std::vector<const CodeGenInstruction*> NumberedInstructions;
183  Target.getInstructionsByEnumValue(NumberedInstructions);
184
185  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
186    emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
187               OperandInfosEmitted, OS);
188  OS << "};\n";
189  OS << "} // End llvm namespace \n";
190}
191
192void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
193                                  Record *InstrInfo,
194                         std::map<std::vector<Record*>, unsigned> &EmittedLists,
195                           std::map<std::vector<std::string>, unsigned> &OpInfo,
196                                  std::ostream &OS) {
197  int MinOperands;
198  if (!Inst.OperandList.empty())
199    // Each logical operand can be multiple MI operands.
200    MinOperands = Inst.OperandList.back().MIOperandNo +
201                  Inst.OperandList.back().MINumOperands;
202  else
203    MinOperands = 0;
204
205  OS << "  { ";
206  OS << Num << ",\t" << MinOperands << ",\t"
207     << Inst.NumDefs << ",\t\"";
208
209  if (Inst.Name.empty())
210    OS << Inst.TheDef->getName();
211  else
212    OS << Inst.Name;
213
214  unsigned ItinClass = !IsItineraries ? 0 :
215            ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
216
217  OS << "\",\t" << ItinClass << ", 0";
218
219  // Try to determine (from the pattern), if the instruction is a store.
220  bool isStore = false;
221  if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) {
222    ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
223    if (LI && LI->getSize() > 0) {
224      DagInit *Dag = (DagInit *)LI->getElement(0);
225      DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
226      if (OpDef) {
227        Record *Operator = OpDef->getDef();
228        if (Operator->isSubClassOf("SDNode")) {
229          const std::string Opcode = Operator->getValueAsString("Opcode");
230          if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
231            isStore = true;
232        }
233      }
234    }
235  }
236
237  // Emit all of the target indepedent flags...
238  if (Inst.isReturn)     OS << "|M_RET_FLAG";
239  if (Inst.isBranch)     OS << "|M_BRANCH_FLAG";
240  if (Inst.isBarrier)    OS << "|M_BARRIER_FLAG";
241  if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
242  if (Inst.isCall)       OS << "|M_CALL_FLAG";
243  if (Inst.isLoad)       OS << "|M_LOAD_FLAG";
244  if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
245  if (Inst.isPredicable) OS << "|M_PREDICABLE";
246  if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
247  if (Inst.isCommutable) OS << "|M_COMMUTABLE";
248  if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
249  if (Inst.isReMaterializable) OS << "|M_REMATERIALIZIBLE";
250  if (Inst.isNotDuplicable) OS << "|M_NOT_DUPLICABLE";
251  if (Inst.hasOptionalDef) OS << "|M_HAS_OPTIONAL_DEF";
252  if (Inst.usesCustomDAGSchedInserter)
253    OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
254  if (Inst.hasVariableNumberOfOperands)
255    OS << "|M_VARIABLE_OPS";
256  OS << ", 0";
257
258  // Emit all of the target-specific flags...
259  ListInit *LI    = InstrInfo->getValueAsListInit("TSFlagsFields");
260  ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
261  if (LI->getSize() != Shift->getSize())
262    throw "Lengths of " + InstrInfo->getName() +
263          ":(TargetInfoFields, TargetInfoPositions) must be equal!";
264
265  for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
266    emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
267                     dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
268
269  OS << ", ";
270
271  // Emit the implicit uses and defs lists...
272  std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
273  if (UseList.empty())
274    OS << "NULL, ";
275  else
276    OS << "ImplicitList" << EmittedLists[UseList] << ", ";
277
278  std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
279  if (DefList.empty())
280    OS << "NULL, ";
281  else
282    OS << "ImplicitList" << EmittedLists[DefList] << ", ";
283
284  // Emit the operand info.
285  std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
286  if (OperandInfo.empty())
287    OS << "0";
288  else
289    OS << "OperandInfo" << OpInfo[OperandInfo];
290
291  OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
292}
293
294struct LessRecord {
295  bool operator()(const Record *Rec1, const Record *Rec2) const {
296    return Rec1->getName() < Rec2->getName();
297  }
298};
299void InstrInfoEmitter::GatherItinClasses() {
300  std::vector<Record*> DefList =
301                          Records.getAllDerivedDefinitions("InstrItinClass");
302  IsItineraries = !DefList.empty();
303
304  if (!IsItineraries) return;
305
306  std::sort(DefList.begin(), DefList.end(), LessRecord());
307
308  for (unsigned i = 0, N = DefList.size(); i < N; i++) {
309    Record *Def = DefList[i];
310    ItinClassMap[Def->getName()] = i;
311  }
312}
313
314unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) {
315  return ItinClassMap[ItinName];
316}
317
318void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
319                                        IntInit *ShiftInt, std::ostream &OS) {
320  if (Val == 0 || ShiftInt == 0)
321    throw std::string("Illegal value or shift amount in TargetInfo*!");
322  RecordVal *RV = R->getValue(Val->getValue());
323  int Shift = ShiftInt->getValue();
324
325  if (RV == 0 || RV->getValue() == 0) {
326    // This isn't an error if this is a builtin instruction.
327    if (R->getName() != "PHI" &&
328        R->getName() != "INLINEASM" &&
329        R->getName() != "LABEL" &&
330        R->getName() != "EXTRACT_SUBREG" &&
331        R->getName() != "INSERT_SUBREG")
332      throw R->getName() + " doesn't have a field named '" +
333            Val->getValue() + "'!";
334    return;
335  }
336
337  Init *Value = RV->getValue();
338  if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
339    if (BI->getValue()) OS << "|(1<<" << Shift << ")";
340    return;
341  } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
342    // Convert the Bits to an integer to print...
343    Init *I = BI->convertInitializerTo(new IntRecTy());
344    if (I)
345      if (IntInit *II = dynamic_cast<IntInit*>(I)) {
346        if (II->getValue()) {
347          if (Shift)
348            OS << "|(" << II->getValue() << "<<" << Shift << ")";
349          else
350            OS << "|" << II->getValue();
351        }
352        return;
353      }
354
355  } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
356    if (II->getValue()) {
357      if (Shift)
358        OS << "|(" << II->getValue() << "<<" << Shift << ")";
359      else
360        OS << II->getValue();
361    }
362    return;
363  }
364
365  cerr << "Unhandled initializer: " << *Val << "\n";
366  throw "In record '" + R->getName() + "' for TSFlag emission.";
367}
368
369