InstrInfoEmitter.cpp revision c51737f46ff3bd4379b576630c1b83ce163738c5
1//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend is responsible for emitting a description of the target 11// instruction set for the code generator. 12// 13//===----------------------------------------------------------------------===// 14 15#include "InstrInfoEmitter.h" 16#include "CodeGenTarget.h" 17#include "llvm/Target/TargetInstrInfo.h" 18#include "Record.h" 19#include <algorithm> 20using namespace llvm; 21 22// runEnums - Print out enum values for all of the instructions. 23void InstrInfoEmitter::runEnums(std::ostream &OS) { 24 EmitSourceFileHeader("Target Instruction Enum Values", OS); 25 OS << "namespace llvm {\n\n"; 26 27 CodeGenTarget Target; 28 29 // We must emit the PHI opcode first... 30 std::string Namespace; 31 for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 32 E = Target.inst_end(); II != E; ++II) { 33 if (II->second.Namespace != "TargetInstrInfo") { 34 Namespace = II->second.Namespace; 35 break; 36 } 37 } 38 39 if (Namespace.empty()) { 40 std::cerr << "No instructions defined!\n"; 41 exit(1); 42 } 43 44 std::vector<const CodeGenInstruction*> NumberedInstructions; 45 Target.getInstructionsByEnumValue(NumberedInstructions); 46 47 OS << "namespace " << Namespace << " {\n"; 48 OS << " enum {\n"; 49 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 50 OS << " " << NumberedInstructions[i]->TheDef->getName() 51 << "\t= " << i << ",\n"; 52 } 53 OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n"; 54 OS << " };\n}\n"; 55 OS << "} // End llvm namespace \n"; 56} 57 58void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses, 59 unsigned Num, std::ostream &OS) const { 60 OS << "static const unsigned ImplicitList" << Num << "[] = { "; 61 for (unsigned i = 0, e = Uses.size(); i != e; ++i) 62 OS << getQualifiedName(Uses[i]) << ", "; 63 OS << "0 };\n"; 64} 65 66static std::vector<std::pair<Record*, unsigned> > 67GetOperandInfo(const CodeGenInstruction &Inst) { 68 std::vector<std::pair<Record*, unsigned> > Result; 69 for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) { 70 if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass")) { 71 Result.push_back(std::make_pair(Inst.OperandList[i].Rec, 72 Inst.ConstraintsList[i])); 73 } else { 74 // This might be a multiple operand thing. 75 // Targets like X86 have registers in their multi-operand operands. 76 DagInit *MIOI = Inst.OperandList[i].MIOperandInfo; 77 unsigned NumDefs = MIOI->getNumArgs(); 78 for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) { 79 if (NumDefs <= j) { 80 Result.push_back(std::make_pair((Record*)0, Inst.ConstraintsList[i])); 81 } else { 82 DefInit *Def = dynamic_cast<DefInit*>(MIOI->getArg(j)); 83 Result.push_back(std::make_pair(Def ? Def->getDef() : 0, 84 Inst.ConstraintsList[i])); 85 } 86 } 87 } 88 } 89 90 // For backward compatibility: isTwoAddress means operand 1 is tied to 91 // operand 0. 92 if (Inst.isTwoAddress) 93 Result[1].second |= (0 << 16) | (1 << (unsigned)TargetInstrInfo::TIED_TO); 94 95 return Result; 96} 97 98 99// run - Emit the main instruction description records for the target... 100void InstrInfoEmitter::run(std::ostream &OS) { 101 GatherItinClasses(); 102 103 EmitSourceFileHeader("Target Instruction Descriptors", OS); 104 OS << "namespace llvm {\n\n"; 105 106 CodeGenTarget Target; 107 const std::string &TargetName = Target.getName(); 108 Record *InstrInfo = Target.getInstructionSet(); 109 110 // Keep track of all of the def lists we have emitted already. 111 std::map<std::vector<Record*>, unsigned> EmittedLists; 112 unsigned ListNumber = 0; 113 114 // Emit all of the instruction's implicit uses and defs. 115 for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 116 E = Target.inst_end(); II != E; ++II) { 117 Record *Inst = II->second.TheDef; 118 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses"); 119 if (!Uses.empty()) { 120 unsigned &IL = EmittedLists[Uses]; 121 if (!IL) printDefList(Uses, IL = ++ListNumber, OS); 122 } 123 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs"); 124 if (!Defs.empty()) { 125 unsigned &IL = EmittedLists[Defs]; 126 if (!IL) printDefList(Defs, IL = ++ListNumber, OS); 127 } 128 } 129 130 std::map<std::vector<std::pair<Record*, unsigned> >, unsigned> 131 OperandInfosEmitted; 132 unsigned OperandListNum = 0; 133 OperandInfosEmitted[std::vector<std::pair<Record*, unsigned> >()] = 134 ++OperandListNum; 135 136 // Emit all of the operand info records. 137 OS << "\n"; 138 for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 139 E = Target.inst_end(); II != E; ++II) { 140 std::vector<std::pair<Record*, unsigned> > OperandInfo = 141 GetOperandInfo(II->second); 142 unsigned &N = OperandInfosEmitted[OperandInfo]; 143 if (N == 0) { 144 N = ++OperandListNum; 145 OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { "; 146 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) { 147 Record *RC = OperandInfo[i].first; 148 // FIXME: We only care about register operands for now. 149 if (RC && RC->isSubClassOf("RegisterClass")) 150 OS << "{ " << getQualifiedName(RC) << "RegClassID, 0, "; 151 else if (RC && RC->getName() == "ptr_rc") 152 // Ptr value whose register class is resolved via callback. 153 OS << "{ 0, 1, "; 154 else 155 OS << "{ 0, 0, "; 156 OS << OperandInfo[i].second << " }, "; 157 } 158 OS << "};\n"; 159 } 160 } 161 162 // Emit all of the TargetInstrDescriptor records in their ENUM ordering. 163 // 164 OS << "\nstatic const TargetInstrDescriptor " << TargetName 165 << "Insts[] = {\n"; 166 std::vector<const CodeGenInstruction*> NumberedInstructions; 167 Target.getInstructionsByEnumValue(NumberedInstructions); 168 169 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) 170 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists, 171 OperandInfosEmitted, OS); 172 OS << "};\n"; 173 OS << "} // End llvm namespace \n"; 174} 175 176void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, 177 Record *InstrInfo, 178 std::map<std::vector<Record*>, unsigned> &EmittedLists, 179 std::map<std::vector<std::pair<Record*,unsigned> >, unsigned> &OpInfo, 180 std::ostream &OS) { 181 int MinOperands; 182 if (!Inst.OperandList.empty()) 183 // Each logical operand can be multiple MI operands. 184 MinOperands = Inst.OperandList.back().MIOperandNo + 185 Inst.OperandList.back().MINumOperands; 186 else 187 MinOperands = 0; 188 189 OS << " { \""; 190 if (Inst.Name.empty()) 191 OS << Inst.TheDef->getName(); 192 else 193 OS << Inst.Name; 194 195 unsigned ItinClass = !IsItineraries ? 0 : 196 ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName()); 197 198 OS << "\",\t" << MinOperands << ", " << ItinClass 199 << ", 0"; 200 201 // Try to determine (from the pattern), if the instruction is a store. 202 bool isStore = false; 203 if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) { 204 ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern"); 205 if (LI && LI->getSize() > 0) { 206 DagInit *Dag = (DagInit *)LI->getElement(0); 207 DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator()); 208 if (OpDef) { 209 Record *Operator = OpDef->getDef(); 210 if (Operator->isSubClassOf("SDNode")) { 211 const std::string Opcode = Operator->getValueAsString("Opcode"); 212 if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE") 213 isStore = true; 214 } 215 } 216 } 217 } 218 219 // Emit all of the target indepedent flags... 220 if (Inst.isReturn) OS << "|M_RET_FLAG"; 221 if (Inst.isBranch) OS << "|M_BRANCH_FLAG"; 222 if (Inst.isBarrier) OS << "|M_BARRIER_FLAG"; 223 if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG"; 224 if (Inst.isCall) OS << "|M_CALL_FLAG"; 225 if (Inst.isLoad) OS << "|M_LOAD_FLAG"; 226 if (Inst.isStore || isStore) OS << "|M_STORE_FLAG"; 227 if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG"; 228 if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR"; 229 if (Inst.isCommutable) OS << "|M_COMMUTABLE"; 230 if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG"; 231 if (Inst.usesCustomDAGSchedInserter) 232 OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION"; 233 if (Inst.hasVariableNumberOfOperands) 234 OS << "|M_VARIABLE_OPS"; 235 OS << ", 0"; 236 237 // Emit all of the target-specific flags... 238 ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields"); 239 ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts"); 240 if (LI->getSize() != Shift->getSize()) 241 throw "Lengths of " + InstrInfo->getName() + 242 ":(TargetInfoFields, TargetInfoPositions) must be equal!"; 243 244 for (unsigned i = 0, e = LI->getSize(); i != e; ++i) 245 emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)), 246 dynamic_cast<IntInit*>(Shift->getElement(i)), OS); 247 248 OS << ", "; 249 250 // Emit the implicit uses and defs lists... 251 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses"); 252 if (UseList.empty()) 253 OS << "NULL, "; 254 else 255 OS << "ImplicitList" << EmittedLists[UseList] << ", "; 256 257 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs"); 258 if (DefList.empty()) 259 OS << "NULL, "; 260 else 261 OS << "ImplicitList" << EmittedLists[DefList] << ", "; 262 263 // Emit the operand info. 264 std::vector<std::pair<Record*,unsigned> > OperandInfo = GetOperandInfo(Inst); 265 if (OperandInfo.empty()) 266 OS << "0"; 267 else 268 OS << "OperandInfo" << OpInfo[OperandInfo]; 269 270 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n"; 271} 272 273struct LessRecord { 274 bool operator()(const Record *Rec1, const Record *Rec2) const { 275 return Rec1->getName() < Rec2->getName(); 276 } 277}; 278void InstrInfoEmitter::GatherItinClasses() { 279 std::vector<Record*> DefList = 280 Records.getAllDerivedDefinitions("InstrItinClass"); 281 IsItineraries = !DefList.empty(); 282 283 if (!IsItineraries) return; 284 285 std::sort(DefList.begin(), DefList.end(), LessRecord()); 286 287 for (unsigned i = 0, N = DefList.size(); i < N; i++) { 288 Record *Def = DefList[i]; 289 ItinClassMap[Def->getName()] = i; 290 } 291} 292 293unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) { 294 return ItinClassMap[ItinName]; 295} 296 297void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val, 298 IntInit *ShiftInt, std::ostream &OS) { 299 if (Val == 0 || ShiftInt == 0) 300 throw std::string("Illegal value or shift amount in TargetInfo*!"); 301 RecordVal *RV = R->getValue(Val->getValue()); 302 int Shift = ShiftInt->getValue(); 303 304 if (RV == 0 || RV->getValue() == 0) { 305 // This isn't an error if this is a builtin instruction. 306 if (R->getName() != "PHI" && R->getName() != "INLINEASM") 307 throw R->getName() + " doesn't have a field named '" + 308 Val->getValue() + "'!"; 309 return; 310 } 311 312 Init *Value = RV->getValue(); 313 if (BitInit *BI = dynamic_cast<BitInit*>(Value)) { 314 if (BI->getValue()) OS << "|(1<<" << Shift << ")"; 315 return; 316 } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) { 317 // Convert the Bits to an integer to print... 318 Init *I = BI->convertInitializerTo(new IntRecTy()); 319 if (I) 320 if (IntInit *II = dynamic_cast<IntInit*>(I)) { 321 if (II->getValue()) { 322 if (Shift) 323 OS << "|(" << II->getValue() << "<<" << Shift << ")"; 324 else 325 OS << "|" << II->getValue(); 326 } 327 return; 328 } 329 330 } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) { 331 if (II->getValue()) { 332 if (Shift) 333 OS << "|(" << II->getValue() << "<<" << Shift << ")"; 334 else 335 OS << II->getValue(); 336 } 337 return; 338 } 339 340 std::cerr << "Unhandled initializer: " << *Val << "\n"; 341 throw "In record '" + R->getName() + "' for TSFlag emission."; 342} 343 344