InstrInfoEmitter.cpp revision d2035203a0359eedbc1cf4ae77d43176e8455cd4 
1//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend is responsible for emitting a description of the target
11// instruction set for the code generator.
12//
13//===----------------------------------------------------------------------===//
14
15#include "InstrInfoEmitter.h"
16#include "CodeGenTarget.h"
17#include "Record.h"
18#include "llvm/ADT/StringExtras.h"
19#include <algorithm>
20using namespace llvm;
21
22static void PrintDefList(const std::vector<Record*> &Uses,
23                         unsigned Num, raw_ostream &OS) {
24  OS << "static const unsigned ImplicitList" << Num << "[] = { ";
25  for (unsigned i = 0, e = Uses.size(); i != e; ++i)
26    OS << getQualifiedName(Uses[i]) << ", ";
27  OS << "0 };\n";
28}
29
30static void PrintBarriers(std::vector<Record*> &Barriers,
31                          unsigned Num, raw_ostream &OS) {
32  OS << "static const TargetRegisterClass* Barriers" << Num << "[] = { ";
33  for (unsigned i = 0, e = Barriers.size(); i != e; ++i)
34    OS << "&" << getQualifiedName(Barriers[i]) << "RegClass, ";
35  OS << "NULL };\n";
36}
37
38//===----------------------------------------------------------------------===//
39// Instruction Itinerary Information.
40//===----------------------------------------------------------------------===//
41
42struct RecordNameComparator {
43  bool operator()(const Record *Rec1, const Record *Rec2) const {
44    return Rec1->getName() < Rec2->getName();
45  }
46};
47
48void InstrInfoEmitter::GatherItinClasses() {
49  std::vector<Record*> DefList =
50  Records.getAllDerivedDefinitions("InstrItinClass");
51  std::sort(DefList.begin(), DefList.end(), RecordNameComparator());
52
53  for (unsigned i = 0, N = DefList.size(); i < N; i++)
54    ItinClassMap[DefList[i]->getName()] = i;
55}
56
57unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
58  return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
59}
60
61//===----------------------------------------------------------------------===//
62// Operand Info Emission.
63//===----------------------------------------------------------------------===//
64
65std::vector<std::string>
66InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
67  std::vector<std::string> Result;
68
69  for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
70    // Handle aggregate operands and normal operands the same way by expanding
71    // either case into a list of operands for this op.
72    std::vector<CodeGenInstruction::OperandInfo> OperandList;
73
74    // This might be a multiple operand thing.  Targets like X86 have
75    // registers in their multi-operand operands.  It may also be an anonymous
76    // operand, which has a single operand, but no declared class for the
77    // operand.
78    DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
79
80    if (!MIOI || MIOI->getNumArgs() == 0) {
81      // Single, anonymous, operand.
82      OperandList.push_back(Inst.OperandList[i]);
83    } else {
84      for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
85        OperandList.push_back(Inst.OperandList[i]);
86
87        Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
88        OperandList.back().Rec = OpR;
89      }
90    }
91
92    for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
93      Record *OpR = OperandList[j].Rec;
94      std::string Res;
95
96      if (OpR->isSubClassOf("RegisterClass"))
97        Res += getQualifiedName(OpR) + "RegClassID, ";
98      else if (OpR->isSubClassOf("PointerLikeRegClass"))
99        Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
100      else
101        Res += "0, ";
102
103      // Fill in applicable flags.
104      Res += "0";
105
106      // Ptr value whose register class is resolved via callback.
107      if (OpR->isSubClassOf("PointerLikeRegClass"))
108        Res += "|(1<<TOI::LookupPtrRegClass)";
109
110      // Predicate operands.  Check to see if the original unexpanded operand
111      // was of type PredicateOperand.
112      if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
113        Res += "|(1<<TOI::Predicate)";
114
115      // Optional def operands.  Check to see if the original unexpanded operand
116      // was of type OptionalDefOperand.
117      if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand"))
118        Res += "|(1<<TOI::OptionalDef)";
119
120      // Fill in constraint info.
121      Res += ", " + Inst.OperandList[i].Constraints[j];
122      Result.push_back(Res);
123    }
124  }
125
126  return Result;
127}
128
129void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
130                                       OperandInfoMapTy &OperandInfoIDs) {
131  // ID #0 is for no operand info.
132  unsigned OperandListNum = 0;
133  OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
134
135  OS << "\n";
136  const CodeGenTarget &Target = CDP.getTargetInfo();
137  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
138       E = Target.inst_end(); II != E; ++II) {
139    std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
140    unsigned &N = OperandInfoIDs[OperandInfo];
141    if (N != 0) continue;
142
143    N = ++OperandListNum;
144    OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
145    for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
146      OS << "{ " << OperandInfo[i] << " }, ";
147    OS << "};\n";
148  }
149}
150
151void InstrInfoEmitter::DetectRegisterClassBarriers(std::vector<Record*> &Defs,
152                                  const std::vector<CodeGenRegisterClass> &RCs,
153                                  std::vector<Record*> &Barriers) {
154  std::set<Record*> DefSet;
155  unsigned NumDefs = Defs.size();
156  for (unsigned i = 0; i < NumDefs; ++i)
157    DefSet.insert(Defs[i]);
158
159  for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
160    const CodeGenRegisterClass &RC = RCs[i];
161    unsigned NumRegs = RC.Elements.size();
162    if (NumRegs > NumDefs)
163      continue; // Can't possibly clobber this RC.
164
165    bool Clobber = true;
166    for (unsigned j = 0; j < NumRegs; ++j) {
167      Record *Reg = RC.Elements[j];
168      if (!DefSet.count(Reg)) {
169        Clobber = false;
170        break;
171      }
172    }
173    if (Clobber)
174      Barriers.push_back(RC.TheDef);
175  }
176}
177
178//===----------------------------------------------------------------------===//
179// Main Output.
180//===----------------------------------------------------------------------===//
181
182// run - Emit the main instruction description records for the target...
183void InstrInfoEmitter::run(raw_ostream &OS) {
184  GatherItinClasses();
185
186  EmitSourceFileHeader("Target Instruction Descriptors", OS);
187  OS << "namespace llvm {\n\n";
188
189  CodeGenTarget &Target = CDP.getTargetInfo();
190  const std::string &TargetName = Target.getName();
191  Record *InstrInfo = Target.getInstructionSet();
192  const std::vector<CodeGenRegisterClass> &RCs = Target.getRegisterClasses();
193
194  // Keep track of all of the def lists we have emitted already.
195  std::map<std::vector<Record*>, unsigned> EmittedLists;
196  unsigned ListNumber = 0;
197  std::map<std::vector<Record*>, unsigned> EmittedBarriers;
198  unsigned BarrierNumber = 0;
199  std::map<Record*, unsigned> BarriersMap;
200
201  // Emit all of the instruction's implicit uses and defs.
202  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
203         E = Target.inst_end(); II != E; ++II) {
204    Record *Inst = II->second.TheDef;
205    std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
206    if (!Uses.empty()) {
207      unsigned &IL = EmittedLists[Uses];
208      if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
209    }
210    std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
211    if (!Defs.empty()) {
212      std::vector<Record*> RCBarriers;
213      DetectRegisterClassBarriers(Defs, RCs, RCBarriers);
214      if (!RCBarriers.empty()) {
215        unsigned &IB = EmittedBarriers[RCBarriers];
216        if (!IB) PrintBarriers(RCBarriers, IB = ++BarrierNumber, OS);
217        BarriersMap.insert(std::make_pair(Inst, IB));
218      }
219
220      unsigned &IL = EmittedLists[Defs];
221      if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
222    }
223  }
224
225  OperandInfoMapTy OperandInfoIDs;
226
227  // Emit all of the operand info records.
228  EmitOperandInfo(OS, OperandInfoIDs);
229
230  // Emit all of the TargetInstrDesc records in their ENUM ordering.
231  //
232  OS << "\nstatic const TargetInstrDesc " << TargetName
233     << "Insts[] = {\n";
234  std::vector<const CodeGenInstruction*> NumberedInstructions;
235  Target.getInstructionsByEnumValue(NumberedInstructions);
236
237  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
238    emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
239               BarriersMap, OperandInfoIDs, OS);
240  OS << "};\n";
241  OS << "} // End llvm namespace \n";
242}
243
244void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
245                                  Record *InstrInfo,
246                         std::map<std::vector<Record*>, unsigned> &EmittedLists,
247                                  std::map<Record*, unsigned> &BarriersMap,
248                                  const OperandInfoMapTy &OpInfo,
249                                  raw_ostream &OS) {
250  int MinOperands = 0;
251  if (!Inst.OperandList.empty())
252    // Each logical operand can be multiple MI operands.
253    MinOperands = Inst.OperandList.back().MIOperandNo +
254                  Inst.OperandList.back().MINumOperands;
255
256  OS << "  { ";
257  OS << Num << ",\t" << MinOperands << ",\t"
258     << Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef)
259     << ",\t\"" << Inst.TheDef->getName() << "\", 0";
260
261  // Emit all of the target indepedent flags...
262  if (Inst.isReturn)           OS << "|(1<<TID::Return)";
263  if (Inst.isBranch)           OS << "|(1<<TID::Branch)";
264  if (Inst.isIndirectBranch)   OS << "|(1<<TID::IndirectBranch)";
265  if (Inst.isBarrier)          OS << "|(1<<TID::Barrier)";
266  if (Inst.hasDelaySlot)       OS << "|(1<<TID::DelaySlot)";
267  if (Inst.isCall)             OS << "|(1<<TID::Call)";
268  if (Inst.canFoldAsLoad)      OS << "|(1<<TID::FoldableAsLoad)";
269  if (Inst.mayLoad)            OS << "|(1<<TID::MayLoad)";
270  if (Inst.mayStore)           OS << "|(1<<TID::MayStore)";
271  if (Inst.isPredicable)       OS << "|(1<<TID::Predicable)";
272  if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)";
273  if (Inst.isCommutable)       OS << "|(1<<TID::Commutable)";
274  if (Inst.isTerminator)       OS << "|(1<<TID::Terminator)";
275  if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)";
276  if (Inst.isNotDuplicable)    OS << "|(1<<TID::NotDuplicable)";
277  if (Inst.hasOptionalDef)     OS << "|(1<<TID::HasOptionalDef)";
278  if (Inst.usesCustomInserter) OS << "|(1<<TID::UsesCustomInserter)";
279  if (Inst.isVariadic)         OS << "|(1<<TID::Variadic)";
280  if (Inst.hasSideEffects)     OS << "|(1<<TID::UnmodeledSideEffects)";
281  if (Inst.isAsCheapAsAMove)   OS << "|(1<<TID::CheapAsAMove)";
282  if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<TID::ExtraSrcRegAllocReq)";
283  if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<TID::ExtraDefRegAllocReq)";
284  OS << ", 0";
285
286  // Emit all of the target-specific flags...
287  ListInit *LI    = InstrInfo->getValueAsListInit("TSFlagsFields");
288  ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
289  if (LI->getSize() != Shift->getSize())
290    throw "Lengths of " + InstrInfo->getName() +
291          ":(TargetInfoFields, TargetInfoPositions) must be equal!";
292
293  for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
294    emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
295                     dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
296
297  OS << ", ";
298
299  // Emit the implicit uses and defs lists...
300  std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
301  if (UseList.empty())
302    OS << "NULL, ";
303  else
304    OS << "ImplicitList" << EmittedLists[UseList] << ", ";
305
306  std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
307  if (DefList.empty())
308    OS << "NULL, ";
309  else
310    OS << "ImplicitList" << EmittedLists[DefList] << ", ";
311
312  std::map<Record*, unsigned>::iterator BI = BarriersMap.find(Inst.TheDef);
313  if (BI == BarriersMap.end())
314    OS << "NULL, ";
315  else
316    OS << "Barriers" << BI->second << ", ";
317
318  // Emit the operand info.
319  std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
320  if (OperandInfo.empty())
321    OS << "0";
322  else
323    OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
324
325  OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
326}
327
328
329void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
330                                        IntInit *ShiftInt, raw_ostream &OS) {
331  if (Val == 0 || ShiftInt == 0)
332    throw std::string("Illegal value or shift amount in TargetInfo*!");
333  RecordVal *RV = R->getValue(Val->getValue());
334  int Shift = ShiftInt->getValue();
335
336  if (RV == 0 || RV->getValue() == 0) {
337    // This isn't an error if this is a builtin instruction.
338    if (R->getName() != "PHI" &&
339        R->getName() != "INLINEASM" &&
340        R->getName() != "DBG_LABEL" &&
341        R->getName() != "EH_LABEL" &&
342        R->getName() != "GC_LABEL" &&
343        R->getName() != "KILL" &&
344        R->getName() != "EXTRACT_SUBREG" &&
345        R->getName() != "INSERT_SUBREG" &&
346        R->getName() != "IMPLICIT_DEF" &&
347        R->getName() != "SUBREG_TO_REG" &&
348        R->getName() != "COPY_TO_REGCLASS" &&
349        R->getName() != "DEBUG_VALUE" &&
350        R->getName() != "DEBUG_DECLARE")
351      throw R->getName() + " doesn't have a field named '" +
352            Val->getValue() + "'!";
353    return;
354  }
355
356  Init *Value = RV->getValue();
357  if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
358    if (BI->getValue()) OS << "|(1<<" << Shift << ")";
359    return;
360  } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
361    // Convert the Bits to an integer to print...
362    Init *I = BI->convertInitializerTo(new IntRecTy());
363    if (I)
364      if (IntInit *II = dynamic_cast<IntInit*>(I)) {
365        if (II->getValue()) {
366          if (Shift)
367            OS << "|(" << II->getValue() << "<<" << Shift << ")";
368          else
369            OS << "|" << II->getValue();
370        }
371        return;
372      }
373
374  } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
375    if (II->getValue()) {
376      if (Shift)
377        OS << "|(" << II->getValue() << "<<" << Shift << ")";
378      else
379        OS << II->getValue();
380    }
381    return;
382  }
383
384  errs() << "Unhandled initializer: " << *Val << "\n";
385  throw "In record '" + R->getName() + "' for TSFlag emission.";
386}
387
388