InstrInfoEmitter.cpp revision d35121ad00667d93ea779a722dbee7d022410815 
1//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend is responsible for emitting a description of the target
11// instruction set for the code generator.
12//
13//===----------------------------------------------------------------------===//
14
15#include "InstrInfoEmitter.h"
16#include "CodeGenTarget.h"
17#include "Record.h"
18#include <algorithm>
19#include <iostream>
20using namespace llvm;
21
22static void PrintDefList(const std::vector<Record*> &Uses,
23                         unsigned Num, std::ostream &OS) {
24  OS << "static const unsigned ImplicitList" << Num << "[] = { ";
25  for (unsigned i = 0, e = Uses.size(); i != e; ++i)
26    OS << getQualifiedName(Uses[i]) << ", ";
27  OS << "0 };\n";
28}
29
30//===----------------------------------------------------------------------===//
31// Instruction Itinerary Information.
32//===----------------------------------------------------------------------===//
33
34struct RecordNameComparator {
35  bool operator()(const Record *Rec1, const Record *Rec2) const {
36    return Rec1->getName() < Rec2->getName();
37  }
38};
39
40void InstrInfoEmitter::GatherItinClasses() {
41  std::vector<Record*> DefList =
42  Records.getAllDerivedDefinitions("InstrItinClass");
43  std::sort(DefList.begin(), DefList.end(), RecordNameComparator());
44
45  for (unsigned i = 0, N = DefList.size(); i < N; i++)
46    ItinClassMap[DefList[i]->getName()] = i;
47}
48
49unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
50  return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
51}
52
53//===----------------------------------------------------------------------===//
54// Operand Info Emission.
55//===----------------------------------------------------------------------===//
56
57std::vector<std::string>
58InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
59  std::vector<std::string> Result;
60
61  for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
62    // Handle aggregate operands and normal operands the same way by expanding
63    // either case into a list of operands for this op.
64    std::vector<CodeGenInstruction::OperandInfo> OperandList;
65
66    // This might be a multiple operand thing.  Targets like X86 have
67    // registers in their multi-operand operands.  It may also be an anonymous
68    // operand, which has a single operand, but no declared class for the
69    // operand.
70    DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
71
72    if (!MIOI || MIOI->getNumArgs() == 0) {
73      // Single, anonymous, operand.
74      OperandList.push_back(Inst.OperandList[i]);
75    } else {
76      for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
77        OperandList.push_back(Inst.OperandList[i]);
78
79        Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
80        OperandList.back().Rec = OpR;
81      }
82    }
83
84    for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
85      Record *OpR = OperandList[j].Rec;
86      std::string Res;
87
88      // Discard "discard" operands.
89      if (OpR->getName() == "discard")
90        continue;
91
92      if (OpR->isSubClassOf("RegisterClass"))
93        Res += getQualifiedName(OpR) + "RegClassID, ";
94      else
95        Res += "0, ";
96      // Fill in applicable flags.
97      Res += "0";
98
99      // Ptr value whose register class is resolved via callback.
100      if (OpR->getName() == "ptr_rc")
101        Res += "|(1<<TOI::LookupPtrRegClass)";
102
103      // Predicate operands.  Check to see if the original unexpanded operand
104      // was of type PredicateOperand.
105      if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
106        Res += "|(1<<TOI::Predicate)";
107
108      // Optional def operands.  Check to see if the original unexpanded operand
109      // was of type OptionalDefOperand.
110      if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand"))
111        Res += "|(1<<TOI::OptionalDef)";
112
113      // Fill in constraint info.
114      Res += ", " + Inst.OperandList[i].Constraints[j];
115      Result.push_back(Res);
116    }
117  }
118
119  return Result;
120}
121
122void InstrInfoEmitter::EmitOperandInfo(std::ostream &OS,
123                                       OperandInfoMapTy &OperandInfoIDs) {
124  // ID #0 is for no operand info.
125  unsigned OperandListNum = 0;
126  OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
127
128  OS << "\n";
129  const CodeGenTarget &Target = CDP.getTargetInfo();
130  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
131       E = Target.inst_end(); II != E; ++II) {
132    std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
133    unsigned &N = OperandInfoIDs[OperandInfo];
134    if (N != 0) continue;
135
136    N = ++OperandListNum;
137    OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
138    for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
139      OS << "{ " << OperandInfo[i] << " }, ";
140    OS << "};\n";
141  }
142}
143
144//===----------------------------------------------------------------------===//
145// Main Output.
146//===----------------------------------------------------------------------===//
147
148// run - Emit the main instruction description records for the target...
149void InstrInfoEmitter::run(std::ostream &OS) {
150  GatherItinClasses();
151
152  EmitSourceFileHeader("Target Instruction Descriptors", OS);
153  OS << "namespace llvm {\n\n";
154
155  CodeGenTarget &Target = CDP.getTargetInfo();
156  const std::string &TargetName = Target.getName();
157  Record *InstrInfo = Target.getInstructionSet();
158
159  // Keep track of all of the def lists we have emitted already.
160  std::map<std::vector<Record*>, unsigned> EmittedLists;
161  unsigned ListNumber = 0;
162
163  // Emit all of the instruction's implicit uses and defs.
164  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
165         E = Target.inst_end(); II != E; ++II) {
166    Record *Inst = II->second.TheDef;
167    std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
168    if (!Uses.empty()) {
169      unsigned &IL = EmittedLists[Uses];
170      if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
171    }
172    std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
173    if (!Defs.empty()) {
174      unsigned &IL = EmittedLists[Defs];
175      if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
176    }
177  }
178
179  OperandInfoMapTy OperandInfoIDs;
180
181  // Emit all of the operand info records.
182  EmitOperandInfo(OS, OperandInfoIDs);
183
184  // Emit all of the TargetInstrDesc records in their ENUM ordering.
185  //
186  OS << "\nstatic const TargetInstrDesc " << TargetName
187     << "Insts[] = {\n";
188  std::vector<const CodeGenInstruction*> NumberedInstructions;
189  Target.getInstructionsByEnumValue(NumberedInstructions);
190
191  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
192    emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
193               OperandInfoIDs, OS);
194  OS << "};\n";
195  OS << "} // End llvm namespace \n";
196}
197
198void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
199                                  Record *InstrInfo,
200                         std::map<std::vector<Record*>, unsigned> &EmittedLists,
201                                  const OperandInfoMapTy &OpInfo,
202                                  std::ostream &OS) {
203  int MinOperands = 0;
204  if (!Inst.OperandList.empty())
205    // Each logical operand can be multiple MI operands.
206    MinOperands = Inst.OperandList.back().MIOperandNo +
207                  Inst.OperandList.back().MINumOperands;
208
209  // Subtract the number of "discard" operands, which we'll be skipping
210  // when emitting OperandInfo records.
211  for (unsigned j = 0, e = Inst.OperandList.size(); j != e; ++j) {
212    Record *OpR = Inst.OperandList[j].Rec;
213    if (OpR->getName() == "discard")
214      --MinOperands;
215  }
216
217  OS << "  { ";
218  OS << Num << ",\t" << MinOperands << ",\t"
219     << Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef)
220     << ",\t\"" << Inst.TheDef->getName() << "\", 0";
221
222  // Emit all of the target indepedent flags...
223  if (Inst.isReturn)           OS << "|(1<<TID::Return)";
224  if (Inst.isBranch)           OS << "|(1<<TID::Branch)";
225  if (Inst.isIndirectBranch)   OS << "|(1<<TID::IndirectBranch)";
226  if (Inst.isBarrier)          OS << "|(1<<TID::Barrier)";
227  if (Inst.hasDelaySlot)       OS << "|(1<<TID::DelaySlot)";
228  if (Inst.isCall)             OS << "|(1<<TID::Call)";
229  if (Inst.isSimpleLoad)       OS << "|(1<<TID::SimpleLoad)";
230  if (Inst.mayLoad)            OS << "|(1<<TID::MayLoad)";
231  if (Inst.mayStore)           OS << "|(1<<TID::MayStore)";
232  if (Inst.isPredicable)       OS << "|(1<<TID::Predicable)";
233  if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)";
234  if (Inst.isCommutable)       OS << "|(1<<TID::Commutable)";
235  if (Inst.isTerminator)       OS << "|(1<<TID::Terminator)";
236  if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)";
237  if (Inst.isNotDuplicable)    OS << "|(1<<TID::NotDuplicable)";
238  if (Inst.hasOptionalDef)     OS << "|(1<<TID::HasOptionalDef)";
239  if (Inst.usesCustomDAGSchedInserter)
240    OS << "|(1<<TID::UsesCustomDAGSchedInserter)";
241  if (Inst.isVariadic)         OS << "|(1<<TID::Variadic)";
242  if (Inst.hasSideEffects)     OS << "|(1<<TID::UnmodeledSideEffects)";
243  if (Inst.isAsCheapAsAMove)   OS << "|(1<<TID::CheapAsAMove)";
244  OS << ", 0";
245
246  // Emit all of the target-specific flags...
247  ListInit *LI    = InstrInfo->getValueAsListInit("TSFlagsFields");
248  ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
249  if (LI->getSize() != Shift->getSize())
250    throw "Lengths of " + InstrInfo->getName() +
251          ":(TargetInfoFields, TargetInfoPositions) must be equal!";
252
253  for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
254    emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
255                     dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
256
257  OS << ", ";
258
259  // Emit the implicit uses and defs lists...
260  std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
261  if (UseList.empty())
262    OS << "NULL, ";
263  else
264    OS << "ImplicitList" << EmittedLists[UseList] << ", ";
265
266  std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
267  if (DefList.empty())
268    OS << "NULL, ";
269  else
270    OS << "ImplicitList" << EmittedLists[DefList] << ", ";
271
272  // Emit the operand info.
273  std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
274  if (OperandInfo.empty())
275    OS << "0";
276  else
277    OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
278
279  OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
280}
281
282
283void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
284                                        IntInit *ShiftInt, std::ostream &OS) {
285  if (Val == 0 || ShiftInt == 0)
286    throw std::string("Illegal value or shift amount in TargetInfo*!");
287  RecordVal *RV = R->getValue(Val->getValue());
288  int Shift = ShiftInt->getValue();
289
290  if (RV == 0 || RV->getValue() == 0) {
291    // This isn't an error if this is a builtin instruction.
292    if (R->getName() != "PHI" &&
293        R->getName() != "INLINEASM" &&
294        R->getName() != "LABEL" &&
295        R->getName() != "DECLARE" &&
296        R->getName() != "EXTRACT_SUBREG" &&
297        R->getName() != "INSERT_SUBREG" &&
298        R->getName() != "IMPLICIT_DEF" &&
299        R->getName() != "SUBREG_TO_REG")
300      throw R->getName() + " doesn't have a field named '" +
301            Val->getValue() + "'!";
302    return;
303  }
304
305  Init *Value = RV->getValue();
306  if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
307    if (BI->getValue()) OS << "|(1<<" << Shift << ")";
308    return;
309  } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
310    // Convert the Bits to an integer to print...
311    Init *I = BI->convertInitializerTo(new IntRecTy());
312    if (I)
313      if (IntInit *II = dynamic_cast<IntInit*>(I)) {
314        if (II->getValue()) {
315          if (Shift)
316            OS << "|(" << II->getValue() << "<<" << Shift << ")";
317          else
318            OS << "|" << II->getValue();
319        }
320        return;
321      }
322
323  } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
324    if (II->getValue()) {
325      if (Shift)
326        OS << "|(" << II->getValue() << "<<" << Shift << ")";
327      else
328        OS << II->getValue();
329    }
330    return;
331  }
332
333  std::cerr << "Unhandled initializer: " << *Val << "\n";
334  throw "In record '" + R->getName() + "' for TSFlag emission.";
335}
336
337