InstrInfoEmitter.cpp revision d9a7f4db5f996cce8b3a7f95f8dbac3c996a6625
1//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend is responsible for emitting a description of the target 11// instruction set for the code generator. 12// 13//===----------------------------------------------------------------------===// 14 15#include "InstrInfoEmitter.h" 16#include "CodeGenTarget.h" 17#include "llvm/Target/TargetInstrInfo.h" 18#include "Record.h" 19#include <algorithm> 20using namespace llvm; 21 22// runEnums - Print out enum values for all of the instructions. 23void InstrInfoEmitter::runEnums(std::ostream &OS) { 24 EmitSourceFileHeader("Target Instruction Enum Values", OS); 25 OS << "namespace llvm {\n\n"; 26 27 CodeGenTarget Target; 28 29 // We must emit the PHI opcode first... 30 std::string Namespace; 31 for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 32 E = Target.inst_end(); II != E; ++II) { 33 if (II->second.Namespace != "TargetInstrInfo") { 34 Namespace = II->second.Namespace; 35 break; 36 } 37 } 38 39 if (Namespace.empty()) { 40 std::cerr << "No instructions defined!\n"; 41 exit(1); 42 } 43 44 std::vector<const CodeGenInstruction*> NumberedInstructions; 45 Target.getInstructionsByEnumValue(NumberedInstructions); 46 47 OS << "namespace " << Namespace << " {\n"; 48 OS << " enum {\n"; 49 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 50 OS << " " << NumberedInstructions[i]->TheDef->getName() 51 << "\t= " << i << ",\n"; 52 } 53 OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n"; 54 OS << " };\n}\n"; 55 OS << "} // End llvm namespace \n"; 56} 57 58void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses, 59 unsigned Num, std::ostream &OS) const { 60 OS << "static const unsigned ImplicitList" << Num << "[] = { "; 61 for (unsigned i = 0, e = Uses.size(); i != e; ++i) 62 OS << getQualifiedName(Uses[i]) << ", "; 63 OS << "0 };\n"; 64} 65 66std::vector<std::string> 67InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { 68 std::vector<std::string> Result; 69 for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) { 70 if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass")) { 71 std::string OpStr = getQualifiedName(Inst.OperandList[i].Rec); 72 OpStr += "RegClassID, 0, "; 73 OpStr += Inst.OperandList[i].Constraint; 74 75 Result.push_back(OpStr); 76 } else { 77 // This might be a multiple operand thing. Targets like X86 have 78 // registers in their multi-operand operands. It may also be an anonymous 79 // operand, which has a single operand, but no declared class for the 80 // operand. 81 DagInit *MIOI = Inst.OperandList[i].MIOperandInfo; 82 83 for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) { 84 Record *OpR = 0; 85 if (MIOI && j < MIOI->getNumArgs()) 86 if (DefInit *Def = dynamic_cast<DefInit*>(MIOI->getArg(j))) 87 OpR = Def->getDef(); 88 89 90 std::string Res; 91 92 if (OpR && OpR->isSubClassOf("RegisterClass")) 93 Res += getQualifiedName(OpR) + "RegClassID, "; 94 else 95 Res += "0, "; 96 97 // Fill in applicable flags. 98 Res += "0"; 99 100 // Ptr value whose register class is resolved via callback. 101 if (OpR && OpR->getName() == "ptr_rc") 102 Res += "|M_LOOK_UP_PTR_REG_CLASS"; 103 104 // Predicate operands. 105 if (j == 0 && Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand")) 106 Res += "|M_PREDICATE_OPERAND"; 107 108 // fill in constraint info. 109 Res += ", " + Inst.OperandList[i].Constraint; 110 111 Result.push_back(Res); 112 } 113 } 114 } 115 116 return Result; 117} 118 119 120// run - Emit the main instruction description records for the target... 121void InstrInfoEmitter::run(std::ostream &OS) { 122 GatherItinClasses(); 123 124 EmitSourceFileHeader("Target Instruction Descriptors", OS); 125 OS << "namespace llvm {\n\n"; 126 127 CodeGenTarget Target; 128 const std::string &TargetName = Target.getName(); 129 Record *InstrInfo = Target.getInstructionSet(); 130 131 // Keep track of all of the def lists we have emitted already. 132 std::map<std::vector<Record*>, unsigned> EmittedLists; 133 unsigned ListNumber = 0; 134 135 // Emit all of the instruction's implicit uses and defs. 136 for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 137 E = Target.inst_end(); II != E; ++II) { 138 Record *Inst = II->second.TheDef; 139 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses"); 140 if (!Uses.empty()) { 141 unsigned &IL = EmittedLists[Uses]; 142 if (!IL) printDefList(Uses, IL = ++ListNumber, OS); 143 } 144 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs"); 145 if (!Defs.empty()) { 146 unsigned &IL = EmittedLists[Defs]; 147 if (!IL) printDefList(Defs, IL = ++ListNumber, OS); 148 } 149 } 150 151 std::map<std::vector<std::string>, unsigned> OperandInfosEmitted; 152 unsigned OperandListNum = 0; 153 OperandInfosEmitted[std::vector<std::string>()] = ++OperandListNum; 154 155 // Emit all of the operand info records. 156 OS << "\n"; 157 for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 158 E = Target.inst_end(); II != E; ++II) { 159 std::vector<std::string> OperandInfo = GetOperandInfo(II->second); 160 unsigned &N = OperandInfosEmitted[OperandInfo]; 161 if (N == 0) { 162 N = ++OperandListNum; 163 OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { "; 164 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) 165 OS << "{ " << OperandInfo[i] << " }, "; 166 OS << "};\n"; 167 } 168 } 169 170 // Emit all of the TargetInstrDescriptor records in their ENUM ordering. 171 // 172 OS << "\nstatic const TargetInstrDescriptor " << TargetName 173 << "Insts[] = {\n"; 174 std::vector<const CodeGenInstruction*> NumberedInstructions; 175 Target.getInstructionsByEnumValue(NumberedInstructions); 176 177 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) 178 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists, 179 OperandInfosEmitted, OS); 180 OS << "};\n"; 181 OS << "} // End llvm namespace \n"; 182} 183 184void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, 185 Record *InstrInfo, 186 std::map<std::vector<Record*>, unsigned> &EmittedLists, 187 std::map<std::vector<std::string>, unsigned> &OpInfo, 188 std::ostream &OS) { 189 int MinOperands; 190 if (!Inst.OperandList.empty()) 191 // Each logical operand can be multiple MI operands. 192 MinOperands = Inst.OperandList.back().MIOperandNo + 193 Inst.OperandList.back().MINumOperands; 194 else 195 MinOperands = 0; 196 197 OS << " { \""; 198 if (Inst.Name.empty()) 199 OS << Inst.TheDef->getName(); 200 else 201 OS << Inst.Name; 202 203 unsigned ItinClass = !IsItineraries ? 0 : 204 ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName()); 205 206 OS << "\",\t" << MinOperands << ", " << ItinClass 207 << ", 0"; 208 209 // Try to determine (from the pattern), if the instruction is a store. 210 bool isStore = false; 211 if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) { 212 ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern"); 213 if (LI && LI->getSize() > 0) { 214 DagInit *Dag = (DagInit *)LI->getElement(0); 215 DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator()); 216 if (OpDef) { 217 Record *Operator = OpDef->getDef(); 218 if (Operator->isSubClassOf("SDNode")) { 219 const std::string Opcode = Operator->getValueAsString("Opcode"); 220 if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE") 221 isStore = true; 222 } 223 } 224 } 225 } 226 227 // Emit all of the target indepedent flags... 228 if (Inst.isReturn) OS << "|M_RET_FLAG"; 229 if (Inst.isBranch) OS << "|M_BRANCH_FLAG"; 230 if (Inst.isBarrier) OS << "|M_BARRIER_FLAG"; 231 if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG"; 232 if (Inst.isCall) OS << "|M_CALL_FLAG"; 233 if (Inst.isLoad) OS << "|M_LOAD_FLAG"; 234 if (Inst.isStore || isStore) OS << "|M_STORE_FLAG"; 235 if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG"; 236 if (Inst.isPredicated) OS << "|M_PREDICATED"; 237 if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR"; 238 if (Inst.isCommutable) OS << "|M_COMMUTABLE"; 239 if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG"; 240 if (Inst.usesCustomDAGSchedInserter) 241 OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION"; 242 if (Inst.hasVariableNumberOfOperands) 243 OS << "|M_VARIABLE_OPS"; 244 OS << ", 0"; 245 246 // Emit all of the target-specific flags... 247 ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields"); 248 ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts"); 249 if (LI->getSize() != Shift->getSize()) 250 throw "Lengths of " + InstrInfo->getName() + 251 ":(TargetInfoFields, TargetInfoPositions) must be equal!"; 252 253 for (unsigned i = 0, e = LI->getSize(); i != e; ++i) 254 emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)), 255 dynamic_cast<IntInit*>(Shift->getElement(i)), OS); 256 257 OS << ", "; 258 259 // Emit the implicit uses and defs lists... 260 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses"); 261 if (UseList.empty()) 262 OS << "NULL, "; 263 else 264 OS << "ImplicitList" << EmittedLists[UseList] << ", "; 265 266 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs"); 267 if (DefList.empty()) 268 OS << "NULL, "; 269 else 270 OS << "ImplicitList" << EmittedLists[DefList] << ", "; 271 272 // Emit the operand info. 273 std::vector<std::string> OperandInfo = GetOperandInfo(Inst); 274 if (OperandInfo.empty()) 275 OS << "0"; 276 else 277 OS << "OperandInfo" << OpInfo[OperandInfo]; 278 279 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n"; 280} 281 282struct LessRecord { 283 bool operator()(const Record *Rec1, const Record *Rec2) const { 284 return Rec1->getName() < Rec2->getName(); 285 } 286}; 287void InstrInfoEmitter::GatherItinClasses() { 288 std::vector<Record*> DefList = 289 Records.getAllDerivedDefinitions("InstrItinClass"); 290 IsItineraries = !DefList.empty(); 291 292 if (!IsItineraries) return; 293 294 std::sort(DefList.begin(), DefList.end(), LessRecord()); 295 296 for (unsigned i = 0, N = DefList.size(); i < N; i++) { 297 Record *Def = DefList[i]; 298 ItinClassMap[Def->getName()] = i; 299 } 300} 301 302unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) { 303 return ItinClassMap[ItinName]; 304} 305 306void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val, 307 IntInit *ShiftInt, std::ostream &OS) { 308 if (Val == 0 || ShiftInt == 0) 309 throw std::string("Illegal value or shift amount in TargetInfo*!"); 310 RecordVal *RV = R->getValue(Val->getValue()); 311 int Shift = ShiftInt->getValue(); 312 313 if (RV == 0 || RV->getValue() == 0) { 314 // This isn't an error if this is a builtin instruction. 315 if (R->getName() != "PHI" && R->getName() != "INLINEASM") 316 throw R->getName() + " doesn't have a field named '" + 317 Val->getValue() + "'!"; 318 return; 319 } 320 321 Init *Value = RV->getValue(); 322 if (BitInit *BI = dynamic_cast<BitInit*>(Value)) { 323 if (BI->getValue()) OS << "|(1<<" << Shift << ")"; 324 return; 325 } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) { 326 // Convert the Bits to an integer to print... 327 Init *I = BI->convertInitializerTo(new IntRecTy()); 328 if (I) 329 if (IntInit *II = dynamic_cast<IntInit*>(I)) { 330 if (II->getValue()) { 331 if (Shift) 332 OS << "|(" << II->getValue() << "<<" << Shift << ")"; 333 else 334 OS << "|" << II->getValue(); 335 } 336 return; 337 } 338 339 } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) { 340 if (II->getValue()) { 341 if (Shift) 342 OS << "|(" << II->getValue() << "<<" << Shift << ")"; 343 else 344 OS << II->getValue(); 345 } 346 return; 347 } 348 349 std::cerr << "Unhandled initializer: " << *Val << "\n"; 350 throw "In record '" + R->getName() + "' for TSFlag emission."; 351} 352 353